Lines Matching +full:spi +full:- +full:src +full:- +full:clk
1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2017-2018, The Linux foundation. All rights reserved.
4 #include <linux/clk.h>
12 #include <linux/qcom-geni-se.h>
13 #include <linux/spi/spi.h>
16 /* SPI SE specific registers and respective register fields */
52 /* M_CMD OP codes for SPI */
59 /* M_CMD params for SPI */
98 ret = geni_se_clk_freq_match(&mas->se, in get_spi_clk_cfg()
99 speed_hz * mas->oversampling, in get_spi_clk_cfg()
102 dev_err(mas->dev, "Failed(%d) to find src clk for %dHz\n", in get_spi_clk_cfg()
107 *clk_div = DIV_ROUND_UP(sclk_freq, mas->oversampling * speed_hz); in get_spi_clk_cfg()
108 actual_hz = sclk_freq / (mas->oversampling * *clk_div); in get_spi_clk_cfg()
110 dev_dbg(mas->dev, "req %u=>%u sclk %lu, idx %d, div %d\n", speed_hz, in get_spi_clk_cfg()
112 ret = dev_pm_opp_set_rate(mas->dev, sclk_freq); in get_spi_clk_cfg()
114 dev_err(mas->dev, "dev_pm_opp_set_rate failed %d\n", ret); in get_spi_clk_cfg()
116 mas->cur_sclk_hz = sclk_freq; in get_spi_clk_cfg()
121 static void handle_fifo_timeout(struct spi_master *spi, in handle_fifo_timeout() argument
124 struct spi_geni_master *mas = spi_master_get_devdata(spi); in handle_fifo_timeout()
126 struct geni_se *se = &mas->se; in handle_fifo_timeout()
128 spin_lock_irq(&mas->lock); in handle_fifo_timeout()
129 reinit_completion(&mas->cancel_done); in handle_fifo_timeout()
130 writel(0, se->base + SE_GENI_TX_WATERMARK_REG); in handle_fifo_timeout()
131 mas->cur_xfer = NULL; in handle_fifo_timeout()
133 spin_unlock_irq(&mas->lock); in handle_fifo_timeout()
135 time_left = wait_for_completion_timeout(&mas->cancel_done, HZ); in handle_fifo_timeout()
139 spin_lock_irq(&mas->lock); in handle_fifo_timeout()
140 reinit_completion(&mas->abort_done); in handle_fifo_timeout()
142 spin_unlock_irq(&mas->lock); in handle_fifo_timeout()
144 time_left = wait_for_completion_timeout(&mas->abort_done, HZ); in handle_fifo_timeout()
146 dev_err(mas->dev, "Failed to cancel/abort m_cmd\n"); in handle_fifo_timeout()
149 * No need for a lock since SPI core has a lock and we never in handle_fifo_timeout()
152 mas->abort_failed = true; in handle_fifo_timeout()
158 struct geni_se *se = &mas->se; in spi_geni_is_abort_still_pending()
161 if (!mas->abort_failed) in spi_geni_is_abort_still_pending()
170 spin_lock_irq(&mas->lock); in spi_geni_is_abort_still_pending()
171 m_irq = readl(se->base + SE_GENI_M_IRQ_STATUS); in spi_geni_is_abort_still_pending()
172 m_irq_en = readl(se->base + SE_GENI_M_IRQ_EN); in spi_geni_is_abort_still_pending()
173 spin_unlock_irq(&mas->lock); in spi_geni_is_abort_still_pending()
176 dev_err(mas->dev, "Interrupts pending after abort: %#010x\n", in spi_geni_is_abort_still_pending()
185 mas->abort_failed = false; in spi_geni_is_abort_still_pending()
192 struct spi_geni_master *mas = spi_master_get_devdata(slv->master); in spi_geni_set_cs()
193 struct spi_master *spi = dev_get_drvdata(mas->dev); in spi_geni_set_cs() local
194 struct geni_se *se = &mas->se; in spi_geni_set_cs()
197 if (!(slv->mode & SPI_CS_HIGH)) in spi_geni_set_cs()
200 if (set_flag == mas->cs_flag) in spi_geni_set_cs()
203 pm_runtime_get_sync(mas->dev); in spi_geni_set_cs()
206 dev_err(mas->dev, "Can't set chip select\n"); in spi_geni_set_cs()
210 mas->cs_flag = set_flag; in spi_geni_set_cs()
212 spin_lock_irq(&mas->lock); in spi_geni_set_cs()
213 reinit_completion(&mas->cs_done); in spi_geni_set_cs()
218 spin_unlock_irq(&mas->lock); in spi_geni_set_cs()
220 time_left = wait_for_completion_timeout(&mas->cs_done, HZ); in spi_geni_set_cs()
222 handle_fifo_timeout(spi, NULL); in spi_geni_set_cs()
225 pm_runtime_put(mas->dev); in spi_geni_set_cs()
233 struct geni_se *se = &mas->se; in spi_setup_word_len()
238 * 1 SPI word per FIFO word. in spi_setup_word_len()
240 if (!(mas->fifo_width_bits % bits_per_word)) in spi_setup_word_len()
241 pack_words = mas->fifo_width_bits / bits_per_word; in spi_setup_word_len()
244 geni_se_config_packing(&mas->se, bits_per_word, pack_words, msb_first, in spi_setup_word_len()
246 word_len = (bits_per_word - MIN_WORD_LEN) & WORD_LEN_MSK; in spi_setup_word_len()
247 writel(word_len, se->base + SE_SPI_WORD_LEN); in spi_setup_word_len()
254 struct geni_se *se = &mas->se; in geni_spi_set_clock_and_bw()
257 if (clk_hz == mas->cur_speed_hz) in geni_spi_set_clock_and_bw()
262 dev_err(mas->dev, "Err setting clk to %lu: %d\n", clk_hz, ret); in geni_spi_set_clock_and_bw()
267 * SPI core clock gets configured with the requested frequency in geni_spi_set_clock_and_bw()
273 mas->cur_speed_hz = clk_hz; in geni_spi_set_clock_and_bw()
277 writel(clk_sel, se->base + SE_GENI_CLK_SEL); in geni_spi_set_clock_and_bw()
278 writel(m_clk_cfg, se->base + GENI_SER_M_CLK_CFG); in geni_spi_set_clock_and_bw()
281 se->icc_paths[CPU_TO_GENI].avg_bw = Bps_to_icc(mas->cur_speed_hz); in geni_spi_set_clock_and_bw()
290 struct spi_master *spi) in setup_fifo_params() argument
292 struct spi_geni_master *mas = spi_master_get_devdata(spi); in setup_fifo_params()
293 struct geni_se *se = &mas->se; in setup_fifo_params()
297 if (mas->last_mode != spi_slv->mode) { in setup_fifo_params()
298 if (spi_slv->mode & SPI_LOOP) in setup_fifo_params()
301 if (spi_slv->mode & SPI_CPOL) in setup_fifo_params()
304 if (spi_slv->mode & SPI_CPHA) in setup_fifo_params()
307 if (spi_slv->mode & SPI_CS_HIGH) in setup_fifo_params()
308 demux_output_inv = BIT(spi_slv->chip_select); in setup_fifo_params()
310 demux_sel = spi_slv->chip_select; in setup_fifo_params()
311 mas->cur_bits_per_word = spi_slv->bits_per_word; in setup_fifo_params()
313 spi_setup_word_len(mas, spi_slv->mode, spi_slv->bits_per_word); in setup_fifo_params()
314 writel(loopback_cfg, se->base + SE_SPI_LOOPBACK); in setup_fifo_params()
315 writel(demux_sel, se->base + SE_SPI_DEMUX_SEL); in setup_fifo_params()
316 writel(cpha, se->base + SE_SPI_CPHA); in setup_fifo_params()
317 writel(cpol, se->base + SE_SPI_CPOL); in setup_fifo_params()
318 writel(demux_output_inv, se->base + SE_SPI_DEMUX_OUTPUT_INV); in setup_fifo_params()
320 mas->last_mode = spi_slv->mode; in setup_fifo_params()
323 return geni_spi_set_clock_and_bw(mas, spi_slv->max_speed_hz); in setup_fifo_params()
326 static int spi_geni_prepare_message(struct spi_master *spi, in spi_geni_prepare_message() argument
330 struct spi_geni_master *mas = spi_master_get_devdata(spi); in spi_geni_prepare_message()
333 return -EBUSY; in spi_geni_prepare_message()
335 ret = setup_fifo_params(spi_msg->spi, spi); in spi_geni_prepare_message()
337 dev_err(mas->dev, "Couldn't select mode %d\n", ret); in spi_geni_prepare_message()
343 struct geni_se *se = &mas->se; in spi_geni_init()
347 pm_runtime_get_sync(mas->dev); in spi_geni_init()
351 dev_err(mas->dev, "Invalid proto %d\n", proto); in spi_geni_init()
352 pm_runtime_put(mas->dev); in spi_geni_init()
353 return -ENXIO; in spi_geni_init()
355 mas->tx_fifo_depth = geni_se_get_tx_fifo_depth(se); in spi_geni_init()
358 mas->fifo_width_bits = geni_se_get_tx_fifo_width(se); in spi_geni_init()
362 * RX FIFO RFR level to fifo_depth-2. in spi_geni_init()
364 geni_se_init(se, mas->tx_fifo_depth - 3, mas->tx_fifo_depth - 2); in spi_geni_init()
366 mas->tx_wm = 1; in spi_geni_init()
372 mas->oversampling = 2; in spi_geni_init()
374 mas->oversampling = 1; in spi_geni_init()
379 spi_tx_cfg = readl(se->base + SE_SPI_TRANS_CFG); in spi_geni_init()
381 writel(spi_tx_cfg, se->base + SE_SPI_TRANS_CFG); in spi_geni_init()
383 pm_runtime_put(mas->dev); in spi_geni_init()
394 if (mas->fifo_width_bits % mas->cur_bits_per_word) in geni_byte_per_fifo_word()
395 return roundup_pow_of_two(DIV_ROUND_UP(mas->cur_bits_per_word, in geni_byte_per_fifo_word()
398 return mas->fifo_width_bits / BITS_PER_BYTE; in geni_byte_per_fifo_word()
403 struct geni_se *se = &mas->se; in geni_spi_handle_tx()
410 if (!mas->cur_xfer) { in geni_spi_handle_tx()
411 writel(0, se->base + SE_GENI_TX_WATERMARK_REG); in geni_spi_handle_tx()
415 max_bytes = (mas->tx_fifo_depth - mas->tx_wm) * bytes_per_fifo_word; in geni_spi_handle_tx()
416 if (mas->tx_rem_bytes < max_bytes) in geni_spi_handle_tx()
417 max_bytes = mas->tx_rem_bytes; in geni_spi_handle_tx()
419 tx_buf = mas->cur_xfer->tx_buf + mas->cur_xfer->len - mas->tx_rem_bytes; in geni_spi_handle_tx()
426 bytes_to_write = min(bytes_per_fifo_word, max_bytes - i); in geni_spi_handle_tx()
429 iowrite32_rep(se->base + SE_GENI_TX_FIFOn, &fifo_word, 1); in geni_spi_handle_tx()
431 mas->tx_rem_bytes -= max_bytes; in geni_spi_handle_tx()
432 if (!mas->tx_rem_bytes) { in geni_spi_handle_tx()
433 writel(0, se->base + SE_GENI_TX_WATERMARK_REG); in geni_spi_handle_tx()
441 struct geni_se *se = &mas->se; in geni_spi_handle_rx()
449 rx_fifo_status = readl(se->base + SE_GENI_RX_FIFO_STATUS); in geni_spi_handle_rx()
455 rx_bytes -= bytes_per_fifo_word - rx_last_byte_valid; in geni_spi_handle_rx()
459 if (!mas->cur_xfer) { in geni_spi_handle_rx()
461 readl(se->base + SE_GENI_RX_FIFOn); in geni_spi_handle_rx()
465 if (mas->rx_rem_bytes < rx_bytes) in geni_spi_handle_rx()
466 rx_bytes = mas->rx_rem_bytes; in geni_spi_handle_rx()
468 rx_buf = mas->cur_xfer->rx_buf + mas->cur_xfer->len - mas->rx_rem_bytes; in geni_spi_handle_rx()
475 bytes_to_read = min(bytes_per_fifo_word, rx_bytes - i); in geni_spi_handle_rx()
476 ioread32_rep(se->base + SE_GENI_RX_FIFOn, &fifo_word, 1); in geni_spi_handle_rx()
480 mas->rx_rem_bytes -= rx_bytes; in geni_spi_handle_rx()
485 u16 mode, struct spi_master *spi) in setup_fifo_xfer() argument
489 struct geni_se *se = &mas->se; in setup_fifo_xfer()
496 * worried about racing with out interrupt handler. The SPI core in setup_fifo_xfer()
504 spin_lock_irq(&mas->lock); in setup_fifo_xfer()
505 spin_unlock_irq(&mas->lock); in setup_fifo_xfer()
507 if (xfer->bits_per_word != mas->cur_bits_per_word) { in setup_fifo_xfer()
508 spi_setup_word_len(mas, mode, xfer->bits_per_word); in setup_fifo_xfer()
509 mas->cur_bits_per_word = xfer->bits_per_word; in setup_fifo_xfer()
513 ret = geni_spi_set_clock_and_bw(mas, xfer->speed_hz); in setup_fifo_xfer()
517 mas->tx_rem_bytes = 0; in setup_fifo_xfer()
518 mas->rx_rem_bytes = 0; in setup_fifo_xfer()
520 if (!(mas->cur_bits_per_word % MIN_WORD_LEN)) in setup_fifo_xfer()
521 len = xfer->len * BITS_PER_BYTE / mas->cur_bits_per_word; in setup_fifo_xfer()
523 len = xfer->len / (mas->cur_bits_per_word / BITS_PER_BYTE + 1); in setup_fifo_xfer()
526 mas->cur_xfer = xfer; in setup_fifo_xfer()
527 if (xfer->tx_buf) { in setup_fifo_xfer()
529 mas->tx_rem_bytes = xfer->len; in setup_fifo_xfer()
530 writel(len, se->base + SE_SPI_TX_TRANS_LEN); in setup_fifo_xfer()
533 if (xfer->rx_buf) { in setup_fifo_xfer()
535 writel(len, se->base + SE_SPI_RX_TRANS_LEN); in setup_fifo_xfer()
536 mas->rx_rem_bytes = xfer->len; in setup_fifo_xfer()
543 spin_lock_irq(&mas->lock); in setup_fifo_xfer()
547 * TX_WATERMARK_REG should be set after SPI configuration and in setup_fifo_xfer()
553 writel(mas->tx_wm, se->base + SE_GENI_TX_WATERMARK_REG); in setup_fifo_xfer()
555 spin_unlock_irq(&mas->lock); in setup_fifo_xfer()
558 static int spi_geni_transfer_one(struct spi_master *spi, in spi_geni_transfer_one() argument
562 struct spi_geni_master *mas = spi_master_get_devdata(spi); in spi_geni_transfer_one()
565 return -EBUSY; in spi_geni_transfer_one()
568 if (!xfer->len) in spi_geni_transfer_one()
571 setup_fifo_xfer(xfer, mas, slv->mode, spi); in spi_geni_transfer_one()
577 struct spi_master *spi = data; in geni_spi_isr() local
578 struct spi_geni_master *mas = spi_master_get_devdata(spi); in geni_spi_isr()
579 struct geni_se *se = &mas->se; in geni_spi_isr()
582 m_irq = readl(se->base + SE_GENI_M_IRQ_STATUS); in geni_spi_isr()
589 dev_warn(mas->dev, "Unexpected IRQ err status %#010x\n", m_irq); in geni_spi_isr()
591 spin_lock(&mas->lock); in geni_spi_isr()
600 if (mas->cur_xfer) { in geni_spi_isr()
601 spi_finalize_current_transfer(spi); in geni_spi_isr()
602 mas->cur_xfer = NULL; in geni_spi_isr()
616 if (mas->tx_rem_bytes) { in geni_spi_isr()
617 writel(0, se->base + SE_GENI_TX_WATERMARK_REG); in geni_spi_isr()
618 dev_err(mas->dev, "Premature done. tx_rem = %d bpw%d\n", in geni_spi_isr()
619 mas->tx_rem_bytes, mas->cur_bits_per_word); in geni_spi_isr()
621 if (mas->rx_rem_bytes) in geni_spi_isr()
622 dev_err(mas->dev, "Premature done. rx_rem = %d bpw%d\n", in geni_spi_isr()
623 mas->rx_rem_bytes, mas->cur_bits_per_word); in geni_spi_isr()
625 complete(&mas->cs_done); in geni_spi_isr()
630 complete(&mas->cancel_done); in geni_spi_isr()
632 complete(&mas->abort_done); in geni_spi_isr()
637 * - M_CMD_DONE_EN / M_RX_FIFO_LAST_EN: Edge triggered interrupts and in geni_spi_isr()
642 * - M_RX_FIFO_WATERMARK_EN / M_TX_FIFO_WATERMARK_EN: These appear in geni_spi_isr()
645 * since they'll re-assert if they're still happening. in geni_spi_isr()
647 writel(m_irq, se->base + SE_GENI_M_IRQ_CLEAR); in geni_spi_isr()
649 spin_unlock(&mas->lock); in geni_spi_isr()
657 struct spi_master *spi; in spi_geni_probe() local
660 struct clk *clk; in spi_geni_probe() local
661 struct device *dev = &pdev->dev; in spi_geni_probe()
671 clk = devm_clk_get(dev, "se"); in spi_geni_probe()
672 if (IS_ERR(clk)) in spi_geni_probe()
673 return PTR_ERR(clk); in spi_geni_probe()
675 spi = devm_spi_alloc_master(dev, sizeof(*mas)); in spi_geni_probe()
676 if (!spi) in spi_geni_probe()
677 return -ENOMEM; in spi_geni_probe()
679 platform_set_drvdata(pdev, spi); in spi_geni_probe()
680 mas = spi_master_get_devdata(spi); in spi_geni_probe()
681 mas->irq = irq; in spi_geni_probe()
682 mas->dev = dev; in spi_geni_probe()
683 mas->se.dev = dev; in spi_geni_probe()
684 mas->se.wrapper = dev_get_drvdata(dev->parent); in spi_geni_probe()
685 mas->se.base = base; in spi_geni_probe()
686 mas->se.clk = clk; in spi_geni_probe()
687 mas->se.opp_table = dev_pm_opp_set_clkname(&pdev->dev, "se"); in spi_geni_probe()
688 if (IS_ERR(mas->se.opp_table)) in spi_geni_probe()
689 return PTR_ERR(mas->se.opp_table); in spi_geni_probe()
691 ret = dev_pm_opp_of_add_table(&pdev->dev); in spi_geni_probe()
692 if (ret && ret != -ENODEV) { in spi_geni_probe()
693 dev_err(&pdev->dev, "invalid OPP table in device tree\n"); in spi_geni_probe()
697 spi->bus_num = -1; in spi_geni_probe()
698 spi->dev.of_node = dev->of_node; in spi_geni_probe()
699 spi->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP | SPI_CS_HIGH; in spi_geni_probe()
700 spi->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); in spi_geni_probe()
701 spi->num_chipselect = 4; in spi_geni_probe()
702 spi->max_speed_hz = 50000000; in spi_geni_probe()
703 spi->prepare_message = spi_geni_prepare_message; in spi_geni_probe()
704 spi->transfer_one = spi_geni_transfer_one; in spi_geni_probe()
705 spi->auto_runtime_pm = true; in spi_geni_probe()
706 spi->handle_err = handle_fifo_timeout; in spi_geni_probe()
707 spi->set_cs = spi_geni_set_cs; in spi_geni_probe()
709 init_completion(&mas->cs_done); in spi_geni_probe()
710 init_completion(&mas->cancel_done); in spi_geni_probe()
711 init_completion(&mas->abort_done); in spi_geni_probe()
712 spin_lock_init(&mas->lock); in spi_geni_probe()
713 pm_runtime_use_autosuspend(&pdev->dev); in spi_geni_probe()
714 pm_runtime_set_autosuspend_delay(&pdev->dev, 250); in spi_geni_probe()
717 ret = geni_icc_get(&mas->se, NULL); in spi_geni_probe()
721 mas->se.icc_paths[GENI_TO_CORE].avg_bw = Bps_to_icc(CORE_2X_50_MHZ); in spi_geni_probe()
722 mas->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW; in spi_geni_probe()
724 ret = geni_icc_set_bw(&mas->se); in spi_geni_probe()
732 ret = request_irq(mas->irq, geni_spi_isr, 0, dev_name(dev), spi); in spi_geni_probe()
736 ret = spi_register_master(spi); in spi_geni_probe()
742 free_irq(mas->irq, spi); in spi_geni_probe()
745 dev_pm_opp_of_remove_table(&pdev->dev); in spi_geni_probe()
747 dev_pm_opp_put_clkname(mas->se.opp_table); in spi_geni_probe()
753 struct spi_master *spi = platform_get_drvdata(pdev); in spi_geni_remove() local
754 struct spi_geni_master *mas = spi_master_get_devdata(spi); in spi_geni_remove()
757 spi_unregister_master(spi); in spi_geni_remove()
759 free_irq(mas->irq, spi); in spi_geni_remove()
760 pm_runtime_disable(&pdev->dev); in spi_geni_remove()
761 dev_pm_opp_of_remove_table(&pdev->dev); in spi_geni_remove()
762 dev_pm_opp_put_clkname(mas->se.opp_table); in spi_geni_remove()
768 struct spi_master *spi = dev_get_drvdata(dev); in spi_geni_runtime_suspend() local
769 struct spi_geni_master *mas = spi_master_get_devdata(spi); in spi_geni_runtime_suspend()
775 ret = geni_se_resources_off(&mas->se); in spi_geni_runtime_suspend()
779 return geni_icc_disable(&mas->se); in spi_geni_runtime_suspend()
784 struct spi_master *spi = dev_get_drvdata(dev); in spi_geni_runtime_resume() local
785 struct spi_geni_master *mas = spi_master_get_devdata(spi); in spi_geni_runtime_resume()
788 ret = geni_icc_enable(&mas->se); in spi_geni_runtime_resume()
792 ret = geni_se_resources_on(&mas->se); in spi_geni_runtime_resume()
796 return dev_pm_opp_set_rate(mas->dev, mas->cur_sclk_hz); in spi_geni_runtime_resume()
801 struct spi_master *spi = dev_get_drvdata(dev); in spi_geni_suspend() local
804 ret = spi_master_suspend(spi); in spi_geni_suspend()
810 spi_master_resume(spi); in spi_geni_suspend()
817 struct spi_master *spi = dev_get_drvdata(dev); in spi_geni_resume() local
824 ret = spi_master_resume(spi); in spi_geni_resume()
838 { .compatible = "qcom,geni-spi" },
854 MODULE_DESCRIPTION("SPI driver for GENI based QUP cores");