Lines Matching +full:tx +full:- +full:clk +full:- +full:100 +full:- +full:inverted
1 // SPDX-License-Identifier: GPL-2.0+
2 // Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
5 #include <linux/clk.h>
9 #include <linux/dma-mapping.h>
27 #include <linux/platform_data/dma-imx.h>
91 struct clk *clk_per;
92 struct clk *clk_ipg;
100 void (*tx)(struct spi_imx_data *); member
104 unsigned int txfifo; /* number of words pushed in tx FIFO */
123 return d->devtype_data->devtype == IMX27_CSPI; in is_imx27_cspi()
128 return d->devtype_data->devtype == IMX35_CSPI; in is_imx35_cspi()
133 return d->devtype_data->devtype == IMX51_ECSPI; in is_imx51_ecspi()
138 return d->devtype_data->devtype == IMX53_ECSPI; in is_imx53_ecspi()
144 unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); \
146 if (spi_imx->rx_buf) { \
147 *(type *)spi_imx->rx_buf = val; \
148 spi_imx->rx_buf += sizeof(type); \
151 spi_imx->remainder -= sizeof(type); \
159 if (spi_imx->tx_buf) { \
160 val = *(type *)spi_imx->tx_buf; \
161 spi_imx->tx_buf += sizeof(type); \
164 spi_imx->count -= sizeof(type); \
166 writel(val, spi_imx->base + MXC_CSPITXDATA); \
228 if (!use_dma || master->fallback) in spi_imx_can_dma()
231 if (!master->dma_rx) in spi_imx_can_dma()
234 if (spi_imx->slave_mode) in spi_imx_can_dma()
237 if (transfer->len < spi_imx->devtype_data->fifo_size) in spi_imx_can_dma()
240 spi_imx->dynamic_burst = 0; in spi_imx_can_dma()
249 * outside the range 0 - 3. We therefore need to limit the cs value to avoid
298 unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); in spi_imx_buf_rx_swap_u32()
303 if (spi_imx->rx_buf) { in spi_imx_buf_rx_swap_u32()
305 bytes_per_word = spi_imx_bytes_per_word(spi_imx->bits_per_word); in spi_imx_buf_rx_swap_u32()
311 *(u32 *)spi_imx->rx_buf = val; in spi_imx_buf_rx_swap_u32()
312 spi_imx->rx_buf += sizeof(u32); in spi_imx_buf_rx_swap_u32()
315 spi_imx->remainder -= sizeof(u32); in spi_imx_buf_rx_swap_u32()
323 unaligned = spi_imx->remainder % 4; in spi_imx_buf_rx_swap()
330 if (spi_imx_bytes_per_word(spi_imx->bits_per_word) == 2) { in spi_imx_buf_rx_swap()
335 val = readl(spi_imx->base + MXC_CSPIRXDATA); in spi_imx_buf_rx_swap()
337 while (unaligned--) { in spi_imx_buf_rx_swap()
338 if (spi_imx->rx_buf) { in spi_imx_buf_rx_swap()
339 *(u8 *)spi_imx->rx_buf = (val >> (8 * unaligned)) & 0xff; in spi_imx_buf_rx_swap()
340 spi_imx->rx_buf++; in spi_imx_buf_rx_swap()
342 spi_imx->remainder--; in spi_imx_buf_rx_swap()
353 if (spi_imx->tx_buf) { in spi_imx_buf_tx_swap_u32()
354 val = *(u32 *)spi_imx->tx_buf; in spi_imx_buf_tx_swap_u32()
355 spi_imx->tx_buf += sizeof(u32); in spi_imx_buf_tx_swap_u32()
358 spi_imx->count -= sizeof(u32); in spi_imx_buf_tx_swap_u32()
360 bytes_per_word = spi_imx_bytes_per_word(spi_imx->bits_per_word); in spi_imx_buf_tx_swap_u32()
367 writel(val, spi_imx->base + MXC_CSPITXDATA); in spi_imx_buf_tx_swap_u32()
375 unaligned = spi_imx->count % 4; in spi_imx_buf_tx_swap()
382 if (spi_imx_bytes_per_word(spi_imx->bits_per_word) == 2) { in spi_imx_buf_tx_swap()
387 while (unaligned--) { in spi_imx_buf_tx_swap()
388 if (spi_imx->tx_buf) { in spi_imx_buf_tx_swap()
389 val |= *(u8 *)spi_imx->tx_buf << (8 * unaligned); in spi_imx_buf_tx_swap()
390 spi_imx->tx_buf++; in spi_imx_buf_tx_swap()
392 spi_imx->count--; in spi_imx_buf_tx_swap()
395 writel(val, spi_imx->base + MXC_CSPITXDATA); in spi_imx_buf_tx_swap()
400 u32 val = be32_to_cpu(readl(spi_imx->base + MXC_CSPIRXDATA)); in mx53_ecspi_rx_slave()
402 if (spi_imx->rx_buf) { in mx53_ecspi_rx_slave()
403 int n_bytes = spi_imx->slave_burst % sizeof(val); in mx53_ecspi_rx_slave()
408 memcpy(spi_imx->rx_buf, in mx53_ecspi_rx_slave()
409 ((u8 *)&val) + sizeof(val) - n_bytes, n_bytes); in mx53_ecspi_rx_slave()
411 spi_imx->rx_buf += n_bytes; in mx53_ecspi_rx_slave()
412 spi_imx->slave_burst -= n_bytes; in mx53_ecspi_rx_slave()
415 spi_imx->remainder -= sizeof(u32); in mx53_ecspi_rx_slave()
421 int n_bytes = spi_imx->count % sizeof(val); in mx53_ecspi_tx_slave()
426 if (spi_imx->tx_buf) { in mx53_ecspi_tx_slave()
427 memcpy(((u8 *)&val) + sizeof(val) - n_bytes, in mx53_ecspi_tx_slave()
428 spi_imx->tx_buf, n_bytes); in mx53_ecspi_tx_slave()
430 spi_imx->tx_buf += n_bytes; in mx53_ecspi_tx_slave()
433 spi_imx->count -= n_bytes; in mx53_ecspi_tx_slave()
435 writel(val, spi_imx->base + MXC_CSPITXDATA); in mx53_ecspi_tx_slave()
443 * there are two 4-bit dividers, the pre-divider divides by in mx51_ecspi_clkdiv()
444 * $pre, the post-divider by 2^$post in mx51_ecspi_clkdiv()
447 unsigned int fin = spi_imx->spi_clk; in mx51_ecspi_clkdiv()
451 post = fls(fin) - fls(fspi); in mx51_ecspi_clkdiv()
457 post = max(4U, post) - 4; in mx51_ecspi_clkdiv()
459 dev_err(spi_imx->dev, "cannot set clock freq: %u (base freq: %u)\n", in mx51_ecspi_clkdiv()
464 pre = DIV_ROUND_UP(fin, fspi << post) - 1; in mx51_ecspi_clkdiv()
466 dev_dbg(spi_imx->dev, "%s: fin: %u, fspi: %u, post: %u, pre: %u\n", in mx51_ecspi_clkdiv()
489 writel(val, spi_imx->base + MX51_ECSPI_INT); in mx51_ecspi_intctrl()
496 reg = readl(spi_imx->base + MX51_ECSPI_CTRL); in mx51_ecspi_trigger()
498 writel(reg, spi_imx->base + MX51_ECSPI_CTRL); in mx51_ecspi_trigger()
503 writel(0, spi_imx->base + MX51_ECSPI_DMA); in mx51_disable_dma()
510 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL); in mx51_ecspi_disable()
512 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL); in mx51_ecspi_disable()
518 struct spi_device *spi = msg->spi; in mx51_ecspi_prepare_message()
523 u32 cfg = readl(spi_imx->base + MX51_ECSPI_CONFIG); in mx51_ecspi_prepare_message()
526 if (spi_imx->slave_mode) in mx51_ecspi_prepare_message()
534 if (spi->mode & SPI_READY) in mx51_ecspi_prepare_message()
535 ctrl |= MX51_ECSPI_CTRL_DRCTL(spi_imx->spi_drctl); in mx51_ecspi_prepare_message()
538 ctrl |= MX51_ECSPI_CTRL_CS(spi->chip_select); in mx51_ecspi_prepare_message()
544 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL); in mx51_ecspi_prepare_message()
546 testreg = readl(spi_imx->base + MX51_ECSPI_TESTREG); in mx51_ecspi_prepare_message()
547 if (spi->mode & SPI_LOOP) in mx51_ecspi_prepare_message()
551 writel(testreg, spi_imx->base + MX51_ECSPI_TESTREG); in mx51_ecspi_prepare_message()
558 if (spi_imx->slave_mode && is_imx53_ecspi(spi_imx)) in mx51_ecspi_prepare_message()
559 cfg &= ~MX51_ECSPI_CONFIG_SBBCTRL(spi->chip_select); in mx51_ecspi_prepare_message()
561 cfg |= MX51_ECSPI_CONFIG_SBBCTRL(spi->chip_select); in mx51_ecspi_prepare_message()
563 if (spi->mode & SPI_CPHA) in mx51_ecspi_prepare_message()
564 cfg |= MX51_ECSPI_CONFIG_SCLKPHA(spi->chip_select); in mx51_ecspi_prepare_message()
566 cfg &= ~MX51_ECSPI_CONFIG_SCLKPHA(spi->chip_select); in mx51_ecspi_prepare_message()
568 if (spi->mode & SPI_CPOL) { in mx51_ecspi_prepare_message()
569 cfg |= MX51_ECSPI_CONFIG_SCLKPOL(spi->chip_select); in mx51_ecspi_prepare_message()
570 cfg |= MX51_ECSPI_CONFIG_SCLKCTL(spi->chip_select); in mx51_ecspi_prepare_message()
572 cfg &= ~MX51_ECSPI_CONFIG_SCLKPOL(spi->chip_select); in mx51_ecspi_prepare_message()
573 cfg &= ~MX51_ECSPI_CONFIG_SCLKCTL(spi->chip_select); in mx51_ecspi_prepare_message()
576 if (spi->mode & SPI_CS_HIGH) in mx51_ecspi_prepare_message()
577 cfg |= MX51_ECSPI_CONFIG_SSBPOL(spi->chip_select); in mx51_ecspi_prepare_message()
579 cfg &= ~MX51_ECSPI_CONFIG_SSBPOL(spi->chip_select); in mx51_ecspi_prepare_message()
581 writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG); in mx51_ecspi_prepare_message()
589 * the polarity of SCLK should be inverted, the GPIO ChipSelect might in mx51_ecspi_prepare_message()
594 * Because spi_imx->spi_bus_clk is only set in bitbang prepare_message in mx51_ecspi_prepare_message()
600 list_for_each_entry(xfer, &msg->transfers, transfer_list) { in mx51_ecspi_prepare_message()
601 if (!xfer->speed_hz) in mx51_ecspi_prepare_message()
603 min_speed_hz = min(xfer->speed_hz, min_speed_hz); in mx51_ecspi_prepare_message()
607 if (likely(delay < 10)) /* SCLK is faster than 100 kHz */ in mx51_ecspi_prepare_message()
618 u32 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL); in mx51_ecspi_prepare_transfer()
619 u32 clk; in mx51_ecspi_prepare_transfer() local
623 if (spi_imx->slave_mode && is_imx53_ecspi(spi_imx)) in mx51_ecspi_prepare_transfer()
624 ctrl |= (spi_imx->slave_burst * 8 - 1) in mx51_ecspi_prepare_transfer()
627 ctrl |= (spi_imx->bits_per_word - 1) in mx51_ecspi_prepare_transfer()
633 ctrl |= mx51_ecspi_clkdiv(spi_imx, spi_imx->spi_bus_clk, &clk); in mx51_ecspi_prepare_transfer()
634 spi_imx->spi_bus_clk = clk; in mx51_ecspi_prepare_transfer()
636 if (spi_imx->usedma) in mx51_ecspi_prepare_transfer()
639 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL); in mx51_ecspi_prepare_transfer()
650 writel(MX51_ECSPI_DMA_RX_WML(spi_imx->wml - 1) | in mx51_setup_wml()
651 MX51_ECSPI_DMA_TX_WML(spi_imx->wml) | in mx51_setup_wml()
652 MX51_ECSPI_DMA_RXT_WML(spi_imx->wml) | in mx51_setup_wml()
654 MX51_ECSPI_DMA_RXTDEN, spi_imx->base + MX51_ECSPI_DMA); in mx51_setup_wml()
659 return readl(spi_imx->base + MX51_ECSPI_STAT) & MX51_ECSPI_STAT_RR; in mx51_ecspi_rx_available()
666 readl(spi_imx->base + MXC_CSPIRXDATA); in mx51_ecspi_reset()
709 writel(val, spi_imx->base + MXC_CSPIINT); in mx31_intctrl()
716 reg = readl(spi_imx->base + MXC_CSPICTRL); in mx31_trigger()
718 writel(reg, spi_imx->base + MXC_CSPICTRL); in mx31_trigger()
731 unsigned int clk; in mx31_prepare_transfer() local
733 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, spi_imx->spi_bus_clk, &clk) << in mx31_prepare_transfer()
735 spi_imx->spi_bus_clk = clk; in mx31_prepare_transfer()
738 reg |= (spi_imx->bits_per_word - 1) << MX35_CSPICTRL_BL_SHIFT; in mx31_prepare_transfer()
741 reg |= (spi_imx->bits_per_word - 1) << MX31_CSPICTRL_BC_SHIFT; in mx31_prepare_transfer()
744 if (spi->mode & SPI_CPHA) in mx31_prepare_transfer()
746 if (spi->mode & SPI_CPOL) in mx31_prepare_transfer()
748 if (spi->mode & SPI_CS_HIGH) in mx31_prepare_transfer()
750 if (!spi->cs_gpiod) in mx31_prepare_transfer()
751 reg |= (spi->chip_select) << in mx31_prepare_transfer()
755 if (spi_imx->usedma) in mx31_prepare_transfer()
758 writel(reg, spi_imx->base + MXC_CSPICTRL); in mx31_prepare_transfer()
760 reg = readl(spi_imx->base + MX31_CSPI_TESTREG); in mx31_prepare_transfer()
761 if (spi->mode & SPI_LOOP) in mx31_prepare_transfer()
765 writel(reg, spi_imx->base + MX31_CSPI_TESTREG); in mx31_prepare_transfer()
767 if (spi_imx->usedma) { in mx31_prepare_transfer()
773 spi_imx->base + MX31_CSPI_DMAREG); in mx31_prepare_transfer()
781 return readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR; in mx31_rx_available()
787 while (readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR) in mx31_reset()
788 readl(spi_imx->base + MXC_CSPIRXDATA); in mx31_reset()
813 writel(val, spi_imx->base + MXC_CSPIINT); in mx21_intctrl()
820 reg = readl(spi_imx->base + MXC_CSPICTRL); in mx21_trigger()
822 writel(reg, spi_imx->base + MXC_CSPICTRL); in mx21_trigger()
836 unsigned int clk; in mx21_prepare_transfer() local
838 reg |= spi_imx_clkdiv_1(spi_imx->spi_clk, spi_imx->spi_bus_clk, max, &clk) in mx21_prepare_transfer()
840 spi_imx->spi_bus_clk = clk; in mx21_prepare_transfer()
842 reg |= spi_imx->bits_per_word - 1; in mx21_prepare_transfer()
844 if (spi->mode & SPI_CPHA) in mx21_prepare_transfer()
846 if (spi->mode & SPI_CPOL) in mx21_prepare_transfer()
848 if (spi->mode & SPI_CS_HIGH) in mx21_prepare_transfer()
850 if (!spi->cs_gpiod) in mx21_prepare_transfer()
851 reg |= spi->chip_select << MX21_CSPICTRL_CS_SHIFT; in mx21_prepare_transfer()
853 writel(reg, spi_imx->base + MXC_CSPICTRL); in mx21_prepare_transfer()
860 return readl(spi_imx->base + MXC_CSPIINT) & MX21_INTREG_RR; in mx21_rx_available()
865 writel(1, spi_imx->base + MXC_RESET); in mx21_reset()
888 writel(val, spi_imx->base + MXC_CSPIINT); in mx1_intctrl()
895 reg = readl(spi_imx->base + MXC_CSPICTRL); in mx1_trigger()
897 writel(reg, spi_imx->base + MXC_CSPICTRL); in mx1_trigger()
910 unsigned int clk; in mx1_prepare_transfer() local
912 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, spi_imx->spi_bus_clk, &clk) << in mx1_prepare_transfer()
914 spi_imx->spi_bus_clk = clk; in mx1_prepare_transfer()
916 reg |= spi_imx->bits_per_word - 1; in mx1_prepare_transfer()
918 if (spi->mode & SPI_CPHA) in mx1_prepare_transfer()
920 if (spi->mode & SPI_CPOL) in mx1_prepare_transfer()
923 writel(reg, spi_imx->base + MXC_CSPICTRL); in mx1_prepare_transfer()
930 return readl(spi_imx->base + MXC_CSPIINT) & MX1_INTREG_RR; in mx1_rx_available()
935 writel(1, spi_imx->base + MXC_RESET); in mx1_reset()
1044 .name = "imx1-cspi",
1047 .name = "imx21-cspi",
1050 .name = "imx27-cspi",
1053 .name = "imx31-cspi",
1056 .name = "imx35-cspi",
1059 .name = "imx51-ecspi",
1062 .name = "imx53-ecspi",
1070 { .compatible = "fsl,imx1-cspi", .data = &imx1_cspi_devtype_data, },
1071 { .compatible = "fsl,imx21-cspi", .data = &imx21_cspi_devtype_data, },
1072 { .compatible = "fsl,imx27-cspi", .data = &imx27_cspi_devtype_data, },
1073 { .compatible = "fsl,imx31-cspi", .data = &imx31_cspi_devtype_data, },
1074 { .compatible = "fsl,imx35-cspi", .data = &imx35_cspi_devtype_data, },
1075 { .compatible = "fsl,imx51-ecspi", .data = &imx51_ecspi_devtype_data, },
1076 { .compatible = "fsl,imx53-ecspi", .data = &imx53_ecspi_devtype_data, },
1085 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL); in spi_imx_set_burst_len()
1087 ctrl |= ((n_bits - 1) << MX51_ECSPI_CTRL_BL_OFFSET); in spi_imx_set_burst_len()
1088 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL); in spi_imx_set_burst_len()
1095 if (spi_imx->dynamic_burst) in spi_imx_push()
1098 fifo_words = spi_imx_bytes_per_word(spi_imx->bits_per_word); in spi_imx_push()
1104 if (!spi_imx->remainder) { in spi_imx_push()
1105 if (spi_imx->dynamic_burst) { in spi_imx_push()
1108 burst_len = spi_imx->count % MX51_ECSPI_CTRL_MAX_BURST; in spi_imx_push()
1115 spi_imx->remainder = burst_len; in spi_imx_push()
1117 spi_imx->remainder = fifo_words; in spi_imx_push()
1121 while (spi_imx->txfifo < spi_imx->devtype_data->fifo_size) { in spi_imx_push()
1122 if (!spi_imx->count) in spi_imx_push()
1124 if (spi_imx->dynamic_burst && in spi_imx_push()
1125 spi_imx->txfifo >= DIV_ROUND_UP(spi_imx->remainder, in spi_imx_push()
1128 spi_imx->tx(spi_imx); in spi_imx_push()
1129 spi_imx->txfifo++; in spi_imx_push()
1132 if (!spi_imx->slave_mode) in spi_imx_push()
1133 spi_imx->devtype_data->trigger(spi_imx); in spi_imx_push()
1140 while (spi_imx->txfifo && in spi_imx_isr()
1141 spi_imx->devtype_data->rx_available(spi_imx)) { in spi_imx_isr()
1142 spi_imx->rx(spi_imx); in spi_imx_isr()
1143 spi_imx->txfifo--; in spi_imx_isr()
1146 if (spi_imx->count) { in spi_imx_isr()
1151 if (spi_imx->txfifo) { in spi_imx_isr()
1155 spi_imx->devtype_data->intctrl( in spi_imx_isr()
1160 spi_imx->devtype_data->intctrl(spi_imx, 0); in spi_imx_isr()
1161 complete(&spi_imx->xfer_done); in spi_imx_isr()
1170 struct dma_slave_config rx = {}, tx = {}; in spi_imx_dma_configure() local
1173 switch (spi_imx_bytes_per_word(spi_imx->bits_per_word)) { in spi_imx_dma_configure()
1184 return -EINVAL; in spi_imx_dma_configure()
1187 tx.direction = DMA_MEM_TO_DEV; in spi_imx_dma_configure()
1188 tx.dst_addr = spi_imx->base_phys + MXC_CSPITXDATA; in spi_imx_dma_configure()
1189 tx.dst_addr_width = buswidth; in spi_imx_dma_configure()
1190 tx.dst_maxburst = spi_imx->wml; in spi_imx_dma_configure()
1191 ret = dmaengine_slave_config(master->dma_tx, &tx); in spi_imx_dma_configure()
1193 dev_err(spi_imx->dev, "TX dma configuration failed with %d\n", ret); in spi_imx_dma_configure()
1198 rx.src_addr = spi_imx->base_phys + MXC_CSPIRXDATA; in spi_imx_dma_configure()
1200 rx.src_maxburst = spi_imx->wml; in spi_imx_dma_configure()
1201 ret = dmaengine_slave_config(master->dma_rx, &rx); in spi_imx_dma_configure()
1203 dev_err(spi_imx->dev, "RX dma configuration failed with %d\n", ret); in spi_imx_dma_configure()
1213 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); in spi_imx_setupxfer()
1218 if (!t->speed_hz) { in spi_imx_setupxfer()
1219 if (!spi->max_speed_hz) { in spi_imx_setupxfer()
1220 dev_err(&spi->dev, "no speed_hz provided!\n"); in spi_imx_setupxfer()
1221 return -EINVAL; in spi_imx_setupxfer()
1223 dev_dbg(&spi->dev, "using spi->max_speed_hz!\n"); in spi_imx_setupxfer()
1224 spi_imx->spi_bus_clk = spi->max_speed_hz; in spi_imx_setupxfer()
1226 spi_imx->spi_bus_clk = t->speed_hz; in spi_imx_setupxfer()
1228 spi_imx->bits_per_word = t->bits_per_word; in spi_imx_setupxfer()
1231 * Initialize the functions for transfer. To transfer non byte-aligned in spi_imx_setupxfer()
1232 * words, we have to use multiple word-size bursts, we can't use in spi_imx_setupxfer()
1235 if (spi_imx->devtype_data->dynamic_burst && !spi_imx->slave_mode && in spi_imx_setupxfer()
1236 (spi_imx->bits_per_word == 8 || in spi_imx_setupxfer()
1237 spi_imx->bits_per_word == 16 || in spi_imx_setupxfer()
1238 spi_imx->bits_per_word == 32)) { in spi_imx_setupxfer()
1240 spi_imx->rx = spi_imx_buf_rx_swap; in spi_imx_setupxfer()
1241 spi_imx->tx = spi_imx_buf_tx_swap; in spi_imx_setupxfer()
1242 spi_imx->dynamic_burst = 1; in spi_imx_setupxfer()
1245 if (spi_imx->bits_per_word <= 8) { in spi_imx_setupxfer()
1246 spi_imx->rx = spi_imx_buf_rx_u8; in spi_imx_setupxfer()
1247 spi_imx->tx = spi_imx_buf_tx_u8; in spi_imx_setupxfer()
1248 } else if (spi_imx->bits_per_word <= 16) { in spi_imx_setupxfer()
1249 spi_imx->rx = spi_imx_buf_rx_u16; in spi_imx_setupxfer()
1250 spi_imx->tx = spi_imx_buf_tx_u16; in spi_imx_setupxfer()
1252 spi_imx->rx = spi_imx_buf_rx_u32; in spi_imx_setupxfer()
1253 spi_imx->tx = spi_imx_buf_tx_u32; in spi_imx_setupxfer()
1255 spi_imx->dynamic_burst = 0; in spi_imx_setupxfer()
1258 if (spi_imx_can_dma(spi_imx->bitbang.master, spi, t)) in spi_imx_setupxfer()
1259 spi_imx->usedma = true; in spi_imx_setupxfer()
1261 spi_imx->usedma = false; in spi_imx_setupxfer()
1263 if (is_imx53_ecspi(spi_imx) && spi_imx->slave_mode) { in spi_imx_setupxfer()
1264 spi_imx->rx = mx53_ecspi_rx_slave; in spi_imx_setupxfer()
1265 spi_imx->tx = mx53_ecspi_tx_slave; in spi_imx_setupxfer()
1266 spi_imx->slave_burst = t->len; in spi_imx_setupxfer()
1269 spi_imx->devtype_data->prepare_transfer(spi_imx, spi); in spi_imx_setupxfer()
1276 struct spi_master *master = spi_imx->bitbang.master; in spi_imx_sdma_exit()
1278 if (master->dma_rx) { in spi_imx_sdma_exit()
1279 dma_release_channel(master->dma_rx); in spi_imx_sdma_exit()
1280 master->dma_rx = NULL; in spi_imx_sdma_exit()
1283 if (master->dma_tx) { in spi_imx_sdma_exit()
1284 dma_release_channel(master->dma_tx); in spi_imx_sdma_exit()
1285 master->dma_tx = NULL; in spi_imx_sdma_exit()
1298 spi_imx->wml = spi_imx->devtype_data->fifo_size / 2; in spi_imx_sdma_init()
1300 /* Prepare for TX DMA: */ in spi_imx_sdma_init()
1301 master->dma_tx = dma_request_chan(dev, "tx"); in spi_imx_sdma_init()
1302 if (IS_ERR(master->dma_tx)) { in spi_imx_sdma_init()
1303 ret = PTR_ERR(master->dma_tx); in spi_imx_sdma_init()
1304 dev_dbg(dev, "can't get the TX DMA channel, error %d!\n", ret); in spi_imx_sdma_init()
1305 master->dma_tx = NULL; in spi_imx_sdma_init()
1310 master->dma_rx = dma_request_chan(dev, "rx"); in spi_imx_sdma_init()
1311 if (IS_ERR(master->dma_rx)) { in spi_imx_sdma_init()
1312 ret = PTR_ERR(master->dma_rx); in spi_imx_sdma_init()
1314 master->dma_rx = NULL; in spi_imx_sdma_init()
1318 init_completion(&spi_imx->dma_rx_completion); in spi_imx_sdma_init()
1319 init_completion(&spi_imx->dma_tx_completion); in spi_imx_sdma_init()
1320 master->can_dma = spi_imx_can_dma; in spi_imx_sdma_init()
1321 master->max_dma_len = MAX_SDMA_BD_BYTES; in spi_imx_sdma_init()
1322 spi_imx->bitbang.master->flags = SPI_MASTER_MUST_RX | in spi_imx_sdma_init()
1335 complete(&spi_imx->dma_rx_completion); in spi_imx_dma_rx_callback()
1342 complete(&spi_imx->dma_tx_completion); in spi_imx_dma_tx_callback()
1350 timeout = (8 + 4) * size / spi_imx->spi_bus_clk; in spi_imx_calculate_timeout()
1365 struct spi_master *master = spi_imx->bitbang.master; in spi_imx_dma_transfer()
1366 struct sg_table *tx = &transfer->tx_sg, *rx = &transfer->rx_sg; in spi_imx_dma_transfer() local
1367 struct scatterlist *last_sg = sg_last(rx->sgl, rx->nents); in spi_imx_dma_transfer()
1372 bytes_per_word = spi_imx_bytes_per_word(transfer->bits_per_word); in spi_imx_dma_transfer()
1373 for (i = spi_imx->devtype_data->fifo_size / 2; i > 0; i--) { in spi_imx_dma_transfer()
1381 spi_imx->wml = i; in spi_imx_dma_transfer()
1387 if (!spi_imx->devtype_data->setup_wml) { in spi_imx_dma_transfer()
1388 dev_err(spi_imx->dev, "No setup_wml()?\n"); in spi_imx_dma_transfer()
1389 ret = -EINVAL; in spi_imx_dma_transfer()
1392 spi_imx->devtype_data->setup_wml(spi_imx); in spi_imx_dma_transfer()
1395 * The TX DMA setup starts the transfer, so make sure RX is configured in spi_imx_dma_transfer()
1396 * before TX. in spi_imx_dma_transfer()
1398 desc_rx = dmaengine_prep_slave_sg(master->dma_rx, in spi_imx_dma_transfer()
1399 rx->sgl, rx->nents, DMA_DEV_TO_MEM, in spi_imx_dma_transfer()
1402 ret = -EINVAL; in spi_imx_dma_transfer()
1406 desc_rx->callback = spi_imx_dma_rx_callback; in spi_imx_dma_transfer()
1407 desc_rx->callback_param = (void *)spi_imx; in spi_imx_dma_transfer()
1409 reinit_completion(&spi_imx->dma_rx_completion); in spi_imx_dma_transfer()
1410 dma_async_issue_pending(master->dma_rx); in spi_imx_dma_transfer()
1412 desc_tx = dmaengine_prep_slave_sg(master->dma_tx, in spi_imx_dma_transfer()
1413 tx->sgl, tx->nents, DMA_MEM_TO_DEV, in spi_imx_dma_transfer()
1416 dmaengine_terminate_all(master->dma_tx); in spi_imx_dma_transfer()
1417 dmaengine_terminate_all(master->dma_rx); in spi_imx_dma_transfer()
1418 return -EINVAL; in spi_imx_dma_transfer()
1421 desc_tx->callback = spi_imx_dma_tx_callback; in spi_imx_dma_transfer()
1422 desc_tx->callback_param = (void *)spi_imx; in spi_imx_dma_transfer()
1424 reinit_completion(&spi_imx->dma_tx_completion); in spi_imx_dma_transfer()
1425 dma_async_issue_pending(master->dma_tx); in spi_imx_dma_transfer()
1427 transfer_timeout = spi_imx_calculate_timeout(spi_imx, transfer->len); in spi_imx_dma_transfer()
1430 timeout = wait_for_completion_timeout(&spi_imx->dma_tx_completion, in spi_imx_dma_transfer()
1433 dev_err(spi_imx->dev, "I/O Error in DMA TX\n"); in spi_imx_dma_transfer()
1434 dmaengine_terminate_all(master->dma_tx); in spi_imx_dma_transfer()
1435 dmaengine_terminate_all(master->dma_rx); in spi_imx_dma_transfer()
1436 return -ETIMEDOUT; in spi_imx_dma_transfer()
1439 timeout = wait_for_completion_timeout(&spi_imx->dma_rx_completion, in spi_imx_dma_transfer()
1442 dev_err(&master->dev, "I/O Error in DMA RX\n"); in spi_imx_dma_transfer()
1443 spi_imx->devtype_data->reset(spi_imx); in spi_imx_dma_transfer()
1444 dmaengine_terminate_all(master->dma_rx); in spi_imx_dma_transfer()
1445 return -ETIMEDOUT; in spi_imx_dma_transfer()
1448 return transfer->len; in spi_imx_dma_transfer()
1451 transfer->error |= SPI_TRANS_FAIL_NO_START; in spi_imx_dma_transfer()
1458 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); in spi_imx_pio_transfer()
1462 spi_imx->tx_buf = transfer->tx_buf; in spi_imx_pio_transfer()
1463 spi_imx->rx_buf = transfer->rx_buf; in spi_imx_pio_transfer()
1464 spi_imx->count = transfer->len; in spi_imx_pio_transfer()
1465 spi_imx->txfifo = 0; in spi_imx_pio_transfer()
1466 spi_imx->remainder = 0; in spi_imx_pio_transfer()
1468 reinit_completion(&spi_imx->xfer_done); in spi_imx_pio_transfer()
1472 spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE); in spi_imx_pio_transfer()
1474 transfer_timeout = spi_imx_calculate_timeout(spi_imx, transfer->len); in spi_imx_pio_transfer()
1476 timeout = wait_for_completion_timeout(&spi_imx->xfer_done, in spi_imx_pio_transfer()
1479 dev_err(&spi->dev, "I/O Error in PIO\n"); in spi_imx_pio_transfer()
1480 spi_imx->devtype_data->reset(spi_imx); in spi_imx_pio_transfer()
1481 return -ETIMEDOUT; in spi_imx_pio_transfer()
1484 return transfer->len; in spi_imx_pio_transfer()
1490 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); in spi_imx_pio_transfer_slave()
1491 int ret = transfer->len; in spi_imx_pio_transfer_slave()
1494 transfer->len > MX53_MAX_TRANSFER_BYTES) { in spi_imx_pio_transfer_slave()
1495 dev_err(&spi->dev, "Transaction too big, max size is %d bytes\n", in spi_imx_pio_transfer_slave()
1497 return -EMSGSIZE; in spi_imx_pio_transfer_slave()
1500 spi_imx->tx_buf = transfer->tx_buf; in spi_imx_pio_transfer_slave()
1501 spi_imx->rx_buf = transfer->rx_buf; in spi_imx_pio_transfer_slave()
1502 spi_imx->count = transfer->len; in spi_imx_pio_transfer_slave()
1503 spi_imx->txfifo = 0; in spi_imx_pio_transfer_slave()
1504 spi_imx->remainder = 0; in spi_imx_pio_transfer_slave()
1506 reinit_completion(&spi_imx->xfer_done); in spi_imx_pio_transfer_slave()
1507 spi_imx->slave_aborted = false; in spi_imx_pio_transfer_slave()
1511 spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE | MXC_INT_RDR); in spi_imx_pio_transfer_slave()
1513 if (wait_for_completion_interruptible(&spi_imx->xfer_done) || in spi_imx_pio_transfer_slave()
1514 spi_imx->slave_aborted) { in spi_imx_pio_transfer_slave()
1515 dev_dbg(&spi->dev, "interrupted\n"); in spi_imx_pio_transfer_slave()
1516 ret = -EINTR; in spi_imx_pio_transfer_slave()
1525 if (spi_imx->devtype_data->disable) in spi_imx_pio_transfer_slave()
1526 spi_imx->devtype_data->disable(spi_imx); in spi_imx_pio_transfer_slave()
1534 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); in spi_imx_transfer()
1536 transfer->effective_speed_hz = spi_imx->spi_bus_clk; in spi_imx_transfer()
1539 while (spi_imx->devtype_data->rx_available(spi_imx)) in spi_imx_transfer()
1540 readl(spi_imx->base + MXC_CSPIRXDATA); in spi_imx_transfer()
1542 if (spi_imx->slave_mode) in spi_imx_transfer()
1545 if (spi_imx->usedma) in spi_imx_transfer()
1553 dev_dbg(&spi->dev, "%s: mode %d, %u bpw, %d hz\n", __func__, in spi_imx_setup()
1554 spi->mode, spi->bits_per_word, spi->max_speed_hz); in spi_imx_setup()
1569 ret = pm_runtime_resume_and_get(spi_imx->dev); in spi_imx_prepare_message()
1571 dev_err(spi_imx->dev, "failed to enable clock\n"); in spi_imx_prepare_message()
1575 ret = spi_imx->devtype_data->prepare_message(spi_imx, msg); in spi_imx_prepare_message()
1577 pm_runtime_mark_last_busy(spi_imx->dev); in spi_imx_prepare_message()
1578 pm_runtime_put_autosuspend(spi_imx->dev); in spi_imx_prepare_message()
1589 pm_runtime_mark_last_busy(spi_imx->dev); in spi_imx_unprepare_message()
1590 pm_runtime_put_autosuspend(spi_imx->dev); in spi_imx_unprepare_message()
1598 spi_imx->slave_aborted = true; in spi_imx_slave_abort()
1599 complete(&spi_imx->xfer_done); in spi_imx_slave_abort()
1606 struct device_node *np = pdev->dev.of_node; in spi_imx_probe()
1608 of_match_device(spi_imx_dt_ids, &pdev->dev); in spi_imx_probe()
1613 const struct spi_imx_devtype_data *devtype_data = of_id ? of_id->data : in spi_imx_probe()
1614 (struct spi_imx_devtype_data *)pdev->id_entry->driver_data; in spi_imx_probe()
1618 slave_mode = devtype_data->has_slavemode && in spi_imx_probe()
1619 of_property_read_bool(np, "spi-slave"); in spi_imx_probe()
1621 master = spi_alloc_slave(&pdev->dev, in spi_imx_probe()
1624 master = spi_alloc_master(&pdev->dev, in spi_imx_probe()
1627 return -ENOMEM; in spi_imx_probe()
1629 ret = of_property_read_u32(np, "fsl,spi-rdy-drctl", &spi_drctl); in spi_imx_probe()
1637 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32); in spi_imx_probe()
1638 master->bus_num = np ? -1 : pdev->id; in spi_imx_probe()
1639 master->use_gpio_descriptors = true; in spi_imx_probe()
1642 spi_imx->bitbang.master = master; in spi_imx_probe()
1643 spi_imx->dev = &pdev->dev; in spi_imx_probe()
1644 spi_imx->slave_mode = slave_mode; in spi_imx_probe()
1646 spi_imx->devtype_data = devtype_data; in spi_imx_probe()
1654 if (!device_property_read_u32(&pdev->dev, "num-cs", &val)) in spi_imx_probe()
1655 master->num_chipselect = val; in spi_imx_probe()
1657 master->num_chipselect = 3; in spi_imx_probe()
1659 spi_imx->bitbang.setup_transfer = spi_imx_setupxfer; in spi_imx_probe()
1660 spi_imx->bitbang.txrx_bufs = spi_imx_transfer; in spi_imx_probe()
1661 spi_imx->bitbang.master->setup = spi_imx_setup; in spi_imx_probe()
1662 spi_imx->bitbang.master->cleanup = spi_imx_cleanup; in spi_imx_probe()
1663 spi_imx->bitbang.master->prepare_message = spi_imx_prepare_message; in spi_imx_probe()
1664 spi_imx->bitbang.master->unprepare_message = spi_imx_unprepare_message; in spi_imx_probe()
1665 spi_imx->bitbang.master->slave_abort = spi_imx_slave_abort; in spi_imx_probe()
1666 spi_imx->bitbang.master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH \ in spi_imx_probe()
1670 spi_imx->bitbang.master->mode_bits |= SPI_LOOP | SPI_READY; in spi_imx_probe()
1672 spi_imx->spi_drctl = spi_drctl; in spi_imx_probe()
1674 init_completion(&spi_imx->xfer_done); in spi_imx_probe()
1677 spi_imx->base = devm_ioremap_resource(&pdev->dev, res); in spi_imx_probe()
1678 if (IS_ERR(spi_imx->base)) { in spi_imx_probe()
1679 ret = PTR_ERR(spi_imx->base); in spi_imx_probe()
1682 spi_imx->base_phys = res->start; in spi_imx_probe()
1690 ret = devm_request_irq(&pdev->dev, irq, spi_imx_isr, 0, in spi_imx_probe()
1691 dev_name(&pdev->dev), spi_imx); in spi_imx_probe()
1693 dev_err(&pdev->dev, "can't get irq%d: %d\n", irq, ret); in spi_imx_probe()
1697 spi_imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); in spi_imx_probe()
1698 if (IS_ERR(spi_imx->clk_ipg)) { in spi_imx_probe()
1699 ret = PTR_ERR(spi_imx->clk_ipg); in spi_imx_probe()
1703 spi_imx->clk_per = devm_clk_get(&pdev->dev, "per"); in spi_imx_probe()
1704 if (IS_ERR(spi_imx->clk_per)) { in spi_imx_probe()
1705 ret = PTR_ERR(spi_imx->clk_per); in spi_imx_probe()
1709 ret = clk_prepare_enable(spi_imx->clk_per); in spi_imx_probe()
1713 ret = clk_prepare_enable(spi_imx->clk_ipg); in spi_imx_probe()
1717 pm_runtime_set_autosuspend_delay(spi_imx->dev, MXC_RPM_TIMEOUT); in spi_imx_probe()
1718 pm_runtime_use_autosuspend(spi_imx->dev); in spi_imx_probe()
1719 pm_runtime_get_noresume(spi_imx->dev); in spi_imx_probe()
1720 pm_runtime_set_active(spi_imx->dev); in spi_imx_probe()
1721 pm_runtime_enable(spi_imx->dev); in spi_imx_probe()
1723 spi_imx->spi_clk = clk_get_rate(spi_imx->clk_per); in spi_imx_probe()
1728 if (spi_imx->devtype_data->has_dmamode) { in spi_imx_probe()
1729 ret = spi_imx_sdma_init(&pdev->dev, spi_imx, master); in spi_imx_probe()
1730 if (ret == -EPROBE_DEFER) in spi_imx_probe()
1734 dev_dbg(&pdev->dev, "dma setup error %d, use pio\n", in spi_imx_probe()
1738 spi_imx->devtype_data->reset(spi_imx); in spi_imx_probe()
1740 spi_imx->devtype_data->intctrl(spi_imx, 0); in spi_imx_probe()
1742 master->dev.of_node = pdev->dev.of_node; in spi_imx_probe()
1743 ret = spi_bitbang_start(&spi_imx->bitbang); in spi_imx_probe()
1745 dev_err_probe(&pdev->dev, ret, "bitbang start failed\n"); in spi_imx_probe()
1749 pm_runtime_mark_last_busy(spi_imx->dev); in spi_imx_probe()
1750 pm_runtime_put_autosuspend(spi_imx->dev); in spi_imx_probe()
1755 if (spi_imx->devtype_data->has_dmamode) in spi_imx_probe()
1758 pm_runtime_dont_use_autosuspend(spi_imx->dev); in spi_imx_probe()
1759 pm_runtime_set_suspended(&pdev->dev); in spi_imx_probe()
1760 pm_runtime_disable(spi_imx->dev); in spi_imx_probe()
1762 clk_disable_unprepare(spi_imx->clk_ipg); in spi_imx_probe()
1764 clk_disable_unprepare(spi_imx->clk_per); in spi_imx_probe()
1777 spi_bitbang_stop(&spi_imx->bitbang); in spi_imx_remove()
1779 ret = pm_runtime_get_sync(spi_imx->dev); in spi_imx_remove()
1781 writel(0, spi_imx->base + MXC_CSPICTRL); in spi_imx_remove()
1783 dev_warn(spi_imx->dev, "failed to enable clock, skip hw disable\n"); in spi_imx_remove()
1785 pm_runtime_dont_use_autosuspend(spi_imx->dev); in spi_imx_remove()
1786 pm_runtime_put_sync(spi_imx->dev); in spi_imx_remove()
1787 pm_runtime_disable(spi_imx->dev); in spi_imx_remove()
1803 ret = clk_prepare_enable(spi_imx->clk_per); in spi_imx_runtime_resume()
1807 ret = clk_prepare_enable(spi_imx->clk_ipg); in spi_imx_runtime_resume()
1809 clk_disable_unprepare(spi_imx->clk_per); in spi_imx_runtime_resume()
1823 clk_disable_unprepare(spi_imx->clk_per); in spi_imx_runtime_suspend()
1824 clk_disable_unprepare(spi_imx->clk_ipg); in spi_imx_runtime_suspend()