Lines Matching +full:spi +full:- +full:src +full:- +full:clk
2 * Driver for Amlogic Meson SPI communication controller (SPICC)
7 * SPDX-License-Identifier: GPL-2.0+
11 #include <linux/clk.h>
12 #include <linux/clk-provider.h>
20 #include <linux/spi/spi.h>
30 * - all transfers are cutted in 16 words burst because the FIFO hangs on
31 * TX underflow, and there is no TX "Half-Empty" interrupt, so we go by
33 * - CS management is dumb, and goes UP between every burst, so is really a
69 #define SPICC_TH_EN BIT(1) /* TX FIFO Half-Full Interrupt */
72 #define SPICC_RH_EN BIT(4) /* RX FIFO Half-Full Interrupt */
89 #define SPICC_TH BIT(1) /* TX FIFO Half-Full Interrupt */
92 #define SPICC_RH BIT(4) /* RX FIFO Half-Full Interrupt */
104 #define SPICC_LBC_RO BIT(13) /* Loop Back Control Read-Only */
105 #define SPICC_LBC_W1 BIT(14) /* Loop Back Control Write-Only */
106 #define SPICC_SWAP_RO BIT(14) /* RX FIFO Data Swap Read-Only */
107 #define SPICC_SWAP_W1 BIT(15) /* RX FIFO Data Swap Write-Only */
108 #define SPICC_DLYCTL_RO_MASK GENMASK(20, 15) /* Delay Control Read-Only */
124 #define SPICC_FIFORST_RO_MASK GENMASK(22, 21) /* FIFO Softreset Read-Only */
125 #define SPICC_FIFORST_W1_MASK GENMASK(23, 22) /* FIFO Softreset Write-Only */
157 struct clk *core;
158 struct clk *pclk;
160 struct clk *clk; member
178 if (!spicc->data->has_oen) in meson_spicc_oen_enable()
181 conf = readl_relaxed(spicc->base + SPICC_ENH_CTL0) | in meson_spicc_oen_enable()
184 writel_relaxed(conf, spicc->base + SPICC_ENH_CTL0); in meson_spicc_oen_enable()
190 readl_relaxed(spicc->base + SPICC_STATREG)); in meson_spicc_txfull()
196 readl_relaxed(spicc->base + SPICC_STATREG)); in meson_spicc_rxready()
201 unsigned int bytes = spicc->bytes_per_word; in meson_spicc_pull_data()
206 while (bytes--) { in meson_spicc_pull_data()
207 byte = *spicc->tx_buf++; in meson_spicc_pull_data()
212 spicc->tx_remain--; in meson_spicc_pull_data()
219 unsigned int bytes = spicc->bytes_per_word; in meson_spicc_push_data()
223 while (bytes--) { in meson_spicc_push_data()
225 *spicc->rx_buf++ = byte; in meson_spicc_push_data()
229 spicc->rx_remain--; in meson_spicc_push_data()
235 while (spicc->rx_remain && in meson_spicc_rx()
238 readl_relaxed(spicc->base + SPICC_RXDATA)); in meson_spicc_rx()
244 while (spicc->tx_remain && in meson_spicc_tx()
247 spicc->base + SPICC_TXDATA); in meson_spicc_tx()
254 spicc->xfer_remain / in meson_spicc_setup_burst()
255 spicc->bytes_per_word, in meson_spicc_setup_burst()
256 spicc->data->fifo_size); in meson_spicc_setup_burst()
258 spicc->tx_remain = burst_len; in meson_spicc_setup_burst()
259 spicc->rx_remain = burst_len; in meson_spicc_setup_burst()
260 spicc->xfer_remain -= burst_len * spicc->bytes_per_word; in meson_spicc_setup_burst()
265 burst_len - 1), in meson_spicc_setup_burst()
266 spicc->base + SPICC_CONREG); in meson_spicc_setup_burst()
276 writel_bits_relaxed(SPICC_TC, SPICC_TC, spicc->base + SPICC_STATREG); in meson_spicc_irq()
281 if (!spicc->xfer_remain) { in meson_spicc_irq()
283 writel(0, spicc->base + SPICC_INTREG); in meson_spicc_irq()
285 spi_finalize_current_transfer(spicc->master); in meson_spicc_irq()
294 writel_bits_relaxed(SPICC_XCH, SPICC_XCH, spicc->base + SPICC_CONREG); in meson_spicc_irq()
305 if (spicc->data->has_enhance_clk_div) { in meson_spicc_auto_io_delay()
307 readl_relaxed(spicc->base + SPICC_ENH_CTL0)); in meson_spicc_auto_io_delay()
312 readl_relaxed(spicc->base + SPICC_CONREG)); in meson_spicc_auto_io_delay()
319 hz = clk_get_rate(spicc->clk); in meson_spicc_auto_io_delay()
334 conf = readl_relaxed(spicc->base + SPICC_TESTREG); in meson_spicc_auto_io_delay()
339 writel_relaxed(conf, spicc->base + SPICC_TESTREG); in meson_spicc_auto_io_delay()
348 conf = conf_orig = readl_relaxed(spicc->base + SPICC_CONREG); in meson_spicc_setup_xfer()
353 (spicc->bytes_per_word << 3) - 1); in meson_spicc_setup_xfer()
357 writel_relaxed(conf, spicc->base + SPICC_CONREG); in meson_spicc_setup_xfer()
359 clk_set_rate(spicc->clk, xfer->speed_hz); in meson_spicc_setup_xfer()
363 writel_relaxed(0, spicc->base + SPICC_DMAREG); in meson_spicc_setup_xfer()
368 if (spicc->data->has_oen) in meson_spicc_reset_fifo()
371 spicc->base + SPICC_ENH_CTL0); in meson_spicc_reset_fifo()
374 spicc->base + SPICC_TESTREG); in meson_spicc_reset_fifo()
377 readl_relaxed(spicc->base + SPICC_RXDATA); in meson_spicc_reset_fifo()
379 if (spicc->data->has_oen) in meson_spicc_reset_fifo()
381 spicc->base + SPICC_ENH_CTL0); in meson_spicc_reset_fifo()
385 struct spi_device *spi, in meson_spicc_transfer_one() argument
391 spicc->xfer = xfer; in meson_spicc_transfer_one()
394 spicc->tx_buf = (u8 *)xfer->tx_buf; in meson_spicc_transfer_one()
395 spicc->rx_buf = (u8 *)xfer->rx_buf; in meson_spicc_transfer_one()
396 spicc->xfer_remain = xfer->len; in meson_spicc_transfer_one()
398 /* Pre-calculate word size */ in meson_spicc_transfer_one()
399 spicc->bytes_per_word = in meson_spicc_transfer_one()
400 DIV_ROUND_UP(spicc->xfer->bits_per_word, 8); in meson_spicc_transfer_one()
402 if (xfer->len % spicc->bytes_per_word) in meson_spicc_transfer_one()
403 return -EINVAL; in meson_spicc_transfer_one()
414 writel_bits_relaxed(SPICC_XCH, SPICC_XCH, spicc->base + SPICC_CONREG); in meson_spicc_transfer_one()
417 writel_relaxed(SPICC_TC_EN, spicc->base + SPICC_INTREG); in meson_spicc_transfer_one()
426 struct spi_device *spi = message->spi; in meson_spicc_prepare_message() local
427 u32 conf = readl_relaxed(spicc->base + SPICC_CONREG) & SPICC_DATARATE_MASK; in meson_spicc_prepare_message()
430 spicc->message = message; in meson_spicc_prepare_message()
439 if (spi->mode & SPI_CPOL) in meson_spicc_prepare_message()
444 if (spi->mode & SPI_CPHA) in meson_spicc_prepare_message()
451 if (spi->mode & SPI_CS_HIGH) in meson_spicc_prepare_message()
456 if (spi->mode & SPI_READY) in meson_spicc_prepare_message()
462 conf |= FIELD_PREP(SPICC_CS_MASK, spi->chip_select); in meson_spicc_prepare_message()
465 conf |= FIELD_PREP(SPICC_BITLENGTH_MASK, 8 - 1); in meson_spicc_prepare_message()
467 writel_relaxed(conf, spicc->base + SPICC_CONREG); in meson_spicc_prepare_message()
470 writel_relaxed(0, spicc->base + SPICC_PERIODREG); in meson_spicc_prepare_message()
472 writel_bits_relaxed(SPICC_LBC_W1, 0, spicc->base + SPICC_TESTREG); in meson_spicc_prepare_message()
480 u32 conf = readl_relaxed(spicc->base + SPICC_CONREG) & SPICC_DATARATE_MASK; in meson_spicc_unprepare_transfer()
483 writel(0, spicc->base + SPICC_INTREG); in meson_spicc_unprepare_transfer()
485 device_reset_optional(&spicc->pdev->dev); in meson_spicc_unprepare_transfer()
488 writel_relaxed(conf, spicc->base + SPICC_CONREG); in meson_spicc_unprepare_transfer()
493 static int meson_spicc_setup(struct spi_device *spi) in meson_spicc_setup() argument
495 if (!spi->controller_state) in meson_spicc_setup()
496 spi->controller_state = spi_master_get_devdata(spi->master); in meson_spicc_setup()
501 static void meson_spicc_cleanup(struct spi_device *spi) in meson_spicc_cleanup() argument
503 spi->controller_state = NULL; in meson_spicc_cleanup()
508 * x-----------------x x------------x x------\
509 * |---| pow2 fixed div |---| pow2 div |----| |
510 * | x-----------------x x------------x | |
511 * src ---| | mux |-- out
512 * | x-----------------x x------------x | |
513 * |---| enh fixed div |---| enh div |0---| |
514 * x-----------------x x------------x x------/
516 * Clk path for GX series:
517 * src -> pow2 fixed div -> pow2 div -> out
519 * Clk path for AXG series:
520 * src -> pow2 fixed div -> pow2 div -> mux -> out
521 * src -> enh fixed div -> enh div -> mux -> out
523 * Clk path for G12A series:
524 * pclk -> pow2 fixed div -> pow2 div -> mux -> out
525 * pclk -> enh fixed div -> enh div -> mux -> out
540 if (!spicc->master->cur_msg) in meson_spicc_pow2_recalc_rate()
552 if (!spicc->master->cur_msg) in meson_spicc_pow2_determine_rate()
553 return -EINVAL; in meson_spicc_pow2_determine_rate()
564 if (!spicc->master->cur_msg) in meson_spicc_pow2_set_rate()
565 return -EINVAL; in meson_spicc_pow2_set_rate()
578 struct device *dev = &spicc->pdev->dev; in meson_spicc_pow2_clk_init()
581 struct clk *clk; in meson_spicc_pow2_clk_init() local
594 return -ENOMEM; in meson_spicc_pow2_clk_init()
600 if (spicc->data->has_pclk) in meson_spicc_pow2_clk_init()
601 parent_data[0].hw = __clk_get_hw(spicc->pclk); in meson_spicc_pow2_clk_init()
603 parent_data[0].hw = __clk_get_hw(spicc->core); in meson_spicc_pow2_clk_init()
606 pow2_fixed_div->mult = 1, in meson_spicc_pow2_clk_init()
607 pow2_fixed_div->div = 4, in meson_spicc_pow2_clk_init()
608 pow2_fixed_div->hw.init = &init; in meson_spicc_pow2_clk_init()
610 clk = devm_clk_register(dev, &pow2_fixed_div->hw); in meson_spicc_pow2_clk_init()
611 if (WARN_ON(IS_ERR(clk))) in meson_spicc_pow2_clk_init()
612 return PTR_ERR(clk); in meson_spicc_pow2_clk_init()
622 parent_data[0].hw = &pow2_fixed_div->hw; in meson_spicc_pow2_clk_init()
625 spicc->pow2_div.shift = 16, in meson_spicc_pow2_clk_init()
626 spicc->pow2_div.width = 3, in meson_spicc_pow2_clk_init()
627 spicc->pow2_div.flags = CLK_DIVIDER_POWER_OF_TWO, in meson_spicc_pow2_clk_init()
628 spicc->pow2_div.reg = spicc->base + SPICC_CONREG; in meson_spicc_pow2_clk_init()
629 spicc->pow2_div.hw.init = &init; in meson_spicc_pow2_clk_init()
631 spicc->clk = devm_clk_register(dev, &spicc->pow2_div.hw); in meson_spicc_pow2_clk_init()
632 if (WARN_ON(IS_ERR(spicc->clk))) in meson_spicc_pow2_clk_init()
633 return PTR_ERR(spicc->clk); in meson_spicc_pow2_clk_init()
640 struct device *dev = &spicc->pdev->dev; in meson_spicc_enh_clk_init()
645 struct clk *clk; in meson_spicc_enh_clk_init() local
658 return -ENOMEM; in meson_spicc_enh_clk_init()
664 if (spicc->data->has_pclk) in meson_spicc_enh_clk_init()
665 parent_data[0].hw = __clk_get_hw(spicc->pclk); in meson_spicc_enh_clk_init()
667 parent_data[0].hw = __clk_get_hw(spicc->core); in meson_spicc_enh_clk_init()
670 enh_fixed_div->mult = 1, in meson_spicc_enh_clk_init()
671 enh_fixed_div->div = 2, in meson_spicc_enh_clk_init()
672 enh_fixed_div->hw.init = &init; in meson_spicc_enh_clk_init()
674 clk = devm_clk_register(dev, &enh_fixed_div->hw); in meson_spicc_enh_clk_init()
675 if (WARN_ON(IS_ERR(clk))) in meson_spicc_enh_clk_init()
676 return PTR_ERR(clk); in meson_spicc_enh_clk_init()
680 return -ENOMEM; in meson_spicc_enh_clk_init()
686 parent_data[0].hw = &enh_fixed_div->hw; in meson_spicc_enh_clk_init()
689 enh_div->shift = 16, in meson_spicc_enh_clk_init()
690 enh_div->width = 8, in meson_spicc_enh_clk_init()
691 enh_div->reg = spicc->base + SPICC_ENH_CTL0; in meson_spicc_enh_clk_init()
692 enh_div->hw.init = &init; in meson_spicc_enh_clk_init()
694 clk = devm_clk_register(dev, &enh_div->hw); in meson_spicc_enh_clk_init()
695 if (WARN_ON(IS_ERR(clk))) in meson_spicc_enh_clk_init()
696 return PTR_ERR(clk); in meson_spicc_enh_clk_init()
700 return -ENOMEM; in meson_spicc_enh_clk_init()
705 parent_data[0].hw = &spicc->pow2_div.hw; in meson_spicc_enh_clk_init()
706 parent_data[1].hw = &enh_div->hw; in meson_spicc_enh_clk_init()
710 mux->mask = 0x1, in meson_spicc_enh_clk_init()
711 mux->shift = 24, in meson_spicc_enh_clk_init()
712 mux->reg = spicc->base + SPICC_ENH_CTL0; in meson_spicc_enh_clk_init()
713 mux->hw.init = &init; in meson_spicc_enh_clk_init()
715 spicc->clk = devm_clk_register(dev, &mux->hw); in meson_spicc_enh_clk_init()
716 if (WARN_ON(IS_ERR(spicc->clk))) in meson_spicc_enh_clk_init()
717 return PTR_ERR(spicc->clk); in meson_spicc_enh_clk_init()
728 master = spi_alloc_master(&pdev->dev, sizeof(*spicc)); in meson_spicc_probe()
730 dev_err(&pdev->dev, "master allocation failed\n"); in meson_spicc_probe()
731 return -ENOMEM; in meson_spicc_probe()
734 spicc->master = master; in meson_spicc_probe()
736 spicc->data = of_device_get_match_data(&pdev->dev); in meson_spicc_probe()
737 if (!spicc->data) { in meson_spicc_probe()
738 dev_err(&pdev->dev, "failed to get match data\n"); in meson_spicc_probe()
739 ret = -EINVAL; in meson_spicc_probe()
743 spicc->pdev = pdev; in meson_spicc_probe()
746 spicc->base = devm_platform_ioremap_resource(pdev, 0); in meson_spicc_probe()
747 if (IS_ERR(spicc->base)) { in meson_spicc_probe()
748 dev_err(&pdev->dev, "io resource mapping failed\n"); in meson_spicc_probe()
749 ret = PTR_ERR(spicc->base); in meson_spicc_probe()
755 spicc->base + SPICC_CONREG); in meson_spicc_probe()
758 writel_relaxed(0, spicc->base + SPICC_INTREG); in meson_spicc_probe()
766 ret = devm_request_irq(&pdev->dev, irq, meson_spicc_irq, in meson_spicc_probe()
769 dev_err(&pdev->dev, "irq request failed\n"); in meson_spicc_probe()
773 spicc->core = devm_clk_get(&pdev->dev, "core"); in meson_spicc_probe()
774 if (IS_ERR(spicc->core)) { in meson_spicc_probe()
775 dev_err(&pdev->dev, "core clock request failed\n"); in meson_spicc_probe()
776 ret = PTR_ERR(spicc->core); in meson_spicc_probe()
780 if (spicc->data->has_pclk) { in meson_spicc_probe()
781 spicc->pclk = devm_clk_get(&pdev->dev, "pclk"); in meson_spicc_probe()
782 if (IS_ERR(spicc->pclk)) { in meson_spicc_probe()
783 dev_err(&pdev->dev, "pclk clock request failed\n"); in meson_spicc_probe()
784 ret = PTR_ERR(spicc->pclk); in meson_spicc_probe()
789 ret = clk_prepare_enable(spicc->core); in meson_spicc_probe()
791 dev_err(&pdev->dev, "core clock enable failed\n"); in meson_spicc_probe()
795 ret = clk_prepare_enable(spicc->pclk); in meson_spicc_probe()
797 dev_err(&pdev->dev, "pclk clock enable failed\n"); in meson_spicc_probe()
801 device_reset_optional(&pdev->dev); in meson_spicc_probe()
803 master->num_chipselect = 4; in meson_spicc_probe()
804 master->dev.of_node = pdev->dev.of_node; in meson_spicc_probe()
805 master->mode_bits = SPI_CPHA | SPI_CPOL | SPI_CS_HIGH; in meson_spicc_probe()
806 master->bits_per_word_mask = SPI_BPW_MASK(32) | in meson_spicc_probe()
810 master->flags = (SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX); in meson_spicc_probe()
811 master->min_speed_hz = spicc->data->min_speed_hz; in meson_spicc_probe()
812 master->max_speed_hz = spicc->data->max_speed_hz; in meson_spicc_probe()
813 master->setup = meson_spicc_setup; in meson_spicc_probe()
814 master->cleanup = meson_spicc_cleanup; in meson_spicc_probe()
815 master->prepare_message = meson_spicc_prepare_message; in meson_spicc_probe()
816 master->unprepare_transfer_hardware = meson_spicc_unprepare_transfer; in meson_spicc_probe()
817 master->transfer_one = meson_spicc_transfer_one; in meson_spicc_probe()
818 master->use_gpio_descriptors = true; in meson_spicc_probe()
824 dev_err(&pdev->dev, "pow2 clock registration failed\n"); in meson_spicc_probe()
828 if (spicc->data->has_enhance_clk_div) { in meson_spicc_probe()
831 dev_err(&pdev->dev, "clock registration failed\n"); in meson_spicc_probe()
836 ret = devm_spi_register_master(&pdev->dev, master); in meson_spicc_probe()
838 dev_err(&pdev->dev, "spi master registration failed\n"); in meson_spicc_probe()
845 clk_disable_unprepare(spicc->pclk); in meson_spicc_probe()
848 clk_disable_unprepare(spicc->core); in meson_spicc_probe()
860 /* Disable SPI */ in meson_spicc_remove()
861 writel(0, spicc->base + SPICC_CONREG); in meson_spicc_remove()
863 clk_disable_unprepare(spicc->core); in meson_spicc_remove()
864 clk_disable_unprepare(spicc->pclk); in meson_spicc_remove()
866 spi_master_put(spicc->master); in meson_spicc_remove()
896 .compatible = "amlogic,meson-gx-spicc",
900 .compatible = "amlogic,meson-axg-spicc",
904 .compatible = "amlogic,meson-g12a-spicc",
915 .name = "meson-spicc",
922 MODULE_DESCRIPTION("Meson SPI Communication Controller driver");