3  * MPC52xx PSC in SPI mode driver.
27 #define MCLK 20000000 /* PSC port MClk in hz */
35 	struct mpc52xx_psc __iomem *psc;  member
75 	struct mpc52xx_psc __iomem *psc = mps->psc;  in mpc52xx_psc_spi_activate_cs()  local
79 	sicr = in_be32(&psc->sicr);  in mpc52xx_psc_spi_activate_cs()
95 	out_be32(&psc->sicr, sicr);  in mpc52xx_psc_spi_activate_cs()
98 	 * Because psc->ccr is defined as 16bit register instead of 32bit  in mpc52xx_psc_spi_activate_cs()
101 	ccr = in_be16((u16 __iomem *)&psc->ccr);  in mpc52xx_psc_spi_activate_cs()
107 	out_be16((u16 __iomem *)&psc->ccr, ccr);  in mpc52xx_psc_spi_activate_cs()
130 	struct mpc52xx_psc __iomem *psc = mps->psc;  in mpc52xx_psc_spi_transfer_rxtx()  local
145 	out_8(&psc->command, MPC52xx_PSC_TX_ENABLE | MPC52xx_PSC_RX_ENABLE);  in mpc52xx_psc_spi_transfer_rxtx()
160 				out_8(&psc->ircr2, 0x01);  in mpc52xx_psc_spi_transfer_rxtx()
163 				out_8(&psc->mpc52xx_psc_buffer_8, tx_buf[sb]);  in mpc52xx_psc_spi_transfer_rxtx()
165 				out_8(&psc->mpc52xx_psc_buffer_8, 0);  in mpc52xx_psc_spi_transfer_rxtx()
173 		out_8(&psc->command, MPC52xx_PSC_SEL_MODE_REG_1);  in mpc52xx_psc_spi_transfer_rxtx()
175 			out_8(&psc->mode, 0);  in mpc52xx_psc_spi_transfer_rxtx()
177 			out_8(&psc->mode, MPC52xx_PSC_MODE_FFULL);  in mpc52xx_psc_spi_transfer_rxtx()
180 		out_be16(&psc->mpc52xx_psc_imr, MPC52xx_PSC_IMR_RXRDY);  in mpc52xx_psc_spi_transfer_rxtx()
188 				rx_buf[rb] = in_8(&psc->mpc52xx_psc_buffer_8);  in mpc52xx_psc_spi_transfer_rxtx()
191 				in_8(&psc->mpc52xx_psc_buffer_8);  in mpc52xx_psc_spi_transfer_rxtx()
195 	out_8(&psc->command, MPC52xx_PSC_TX_DISABLE | MPC52xx_PSC_RX_DISABLE);  in mpc52xx_psc_spi_transfer_rxtx()
309 	struct mpc52xx_psc __iomem *psc = mps->psc;  in mpc52xx_psc_spi_port_config()  local
320 	/* Reset the PSC into a known state */  in mpc52xx_psc_spi_port_config()
321 	out_8(&psc->command, MPC52xx_PSC_RST_RX);  in mpc52xx_psc_spi_port_config()
322 	out_8(&psc->command, MPC52xx_PSC_RST_TX);  in mpc52xx_psc_spi_port_config()
323 	out_8(&psc->command, MPC52xx_PSC_TX_DISABLE | MPC52xx_PSC_RX_DISABLE);  in mpc52xx_psc_spi_port_config()
326 	out_be16(&psc->mpc52xx_psc_imr, 0);  in mpc52xx_psc_spi_port_config()
327 	out_8(&psc->command, MPC52xx_PSC_SEL_MODE_REG_1);  in mpc52xx_psc_spi_port_config()
329 	out_8(&psc->mode, MPC52xx_PSC_MODE_FFULL);  in mpc52xx_psc_spi_port_config()
333 	out_be32(&psc->sicr, 0x0180C800);  in mpc52xx_psc_spi_port_config()
334 	out_be16((u16 __iomem *)&psc->ccr, 0x070F); /* default SPI Clk 1MHz */  in mpc52xx_psc_spi_port_config()
337 	out_8(&psc->ctur, 0x00);  in mpc52xx_psc_spi_port_config()
338 	out_8(&psc->ctlr, 0x84);  in mpc52xx_psc_spi_port_config()
348 	struct mpc52xx_psc __iomem *psc = mps->psc;  in mpc52xx_psc_spi_isr()  local
351 	if (in_be16(&psc->mpc52xx_psc_isr) & MPC52xx_PSC_IMR_RXRDY) {  in mpc52xx_psc_spi_isr()
352 		out_be16(&psc->mpc52xx_psc_imr, 0);  in mpc52xx_psc_spi_isr()
397 	mps->psc = ioremap(regaddr, size);  in mpc52xx_psc_spi_do_probe()
398 	if (!mps->psc) {  in mpc52xx_psc_spi_do_probe()
403 	/* On the 5200, fifo regs are immediately ajacent to the psc regs */  in mpc52xx_psc_spi_do_probe()
404 	mps->fifo = ((void __iomem *)mps->psc) + sizeof(struct mpc52xx_psc);  in mpc52xx_psc_spi_do_probe()
406 	ret = request_irq(mps->irq, mpc52xx_psc_spi_isr, 0, "mpc52xx-psc-spi",  in mpc52xx_psc_spi_do_probe()
413 		dev_err(dev, "can't configure PSC! Is it capable of SPI?\n");  in mpc52xx_psc_spi_do_probe()
431 	if (mps->psc)  in mpc52xx_psc_spi_do_probe()
432 		iounmap(mps->psc);  in mpc52xx_psc_spi_do_probe()
446 		dev_err(&op->dev, "Invalid PSC address\n");  in mpc52xx_psc_spi_of_probe()
451 	/* get PSC id (1..6, used by port_config) */  in mpc52xx_psc_spi_of_probe()
475 	if (mps->psc)  in mpc52xx_psc_spi_of_remove()
476 		iounmap(mps->psc);  in mpc52xx_psc_spi_of_remove()
483 	{ .compatible = "fsl,mpc5200-psc-spi", },
484 	{ .compatible = "mpc5200-psc-spi", }, /* old */
494 		.name = "mpc52xx-psc-spi",
501 MODULE_DESCRIPTION("MPC52xx PSC SPI Driver");