Lines Matching +full:spi +full:- +full:src +full:- +full:clk
1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/clk.h>
16 #include <linux/spi/spi-mem.h>
106 /* FIU UMA Write Data Bytes 0-3 Register */
112 /* FIU UMA Write Data Bytes 4-7 Register */
118 /* FIU UMA Write Data Bytes 8-11 Register */
124 /* FIU UMA Write Data Bytes 12-15 Register */
130 /* FIU UMA Read Data Bytes 0-3 Register */
136 /* FIU UMA Read Data Bytes 4-7 Register */
142 /* FIU UMA Read Data Bytes 8-11 Register */
148 /* FIU UMA Read Data Bytes 12-15 Register */
234 struct clk *clk; member
248 regmap_update_bits(fiu->regmap, NPCM_FIU_DRD_CFG, in npcm_fiu_set_drd()
250 ilog2(op->addr.buswidth) << in npcm_fiu_set_drd()
252 fiu->drd_op.addr.buswidth = op->addr.buswidth; in npcm_fiu_set_drd()
253 regmap_update_bits(fiu->regmap, NPCM_FIU_DRD_CFG, in npcm_fiu_set_drd()
255 ((op->dummy.nbytes * ilog2(op->addr.buswidth)) / BITS_PER_BYTE) in npcm_fiu_set_drd()
257 fiu->drd_op.dummy.nbytes = op->dummy.nbytes; in npcm_fiu_set_drd()
258 regmap_update_bits(fiu->regmap, NPCM_FIU_DRD_CFG, in npcm_fiu_set_drd()
259 NPCM_FIU_DRD_CFG_RDCMD, op->cmd.opcode); in npcm_fiu_set_drd()
260 fiu->drd_op.cmd.opcode = op->cmd.opcode; in npcm_fiu_set_drd()
261 regmap_update_bits(fiu->regmap, NPCM_FIU_DRD_CFG, in npcm_fiu_set_drd()
263 (op->addr.nbytes - 3) << NPCM_FIU_DRD_ADDSIZ_SHIFT); in npcm_fiu_set_drd()
264 fiu->drd_op.addr.nbytes = op->addr.nbytes; in npcm_fiu_set_drd()
271 spi_controller_get_devdata(desc->mem->spi->master); in npcm_fiu_direct_read()
272 struct npcm_fiu_chip *chip = &fiu->chip[desc->mem->spi->chip_select]; in npcm_fiu_direct_read()
273 void __iomem *src = (void __iomem *)(chip->flash_region_mapped_ptr + in npcm_fiu_direct_read() local
278 if (fiu->spix_mode) { in npcm_fiu_direct_read()
280 *(buf_rx + i) = ioread8(src + i); in npcm_fiu_direct_read()
282 if (desc->info.op_tmpl.addr.buswidth != fiu->drd_op.addr.buswidth || in npcm_fiu_direct_read()
283 desc->info.op_tmpl.dummy.nbytes != fiu->drd_op.dummy.nbytes || in npcm_fiu_direct_read()
284 desc->info.op_tmpl.cmd.opcode != fiu->drd_op.cmd.opcode || in npcm_fiu_direct_read()
285 desc->info.op_tmpl.addr.nbytes != fiu->drd_op.addr.nbytes) in npcm_fiu_direct_read()
286 npcm_fiu_set_drd(fiu, &desc->info.op_tmpl); in npcm_fiu_direct_read()
288 memcpy_fromio(buf_rx, src, len); in npcm_fiu_direct_read()
298 spi_controller_get_devdata(desc->mem->spi->master); in npcm_fiu_direct_write()
299 struct npcm_fiu_chip *chip = &fiu->chip[desc->mem->spi->chip_select]; in npcm_fiu_direct_write()
300 void __iomem *dst = (void __iomem *)(chip->flash_region_mapped_ptr + in npcm_fiu_direct_write()
305 if (fiu->spix_mode) in npcm_fiu_direct_write()
319 spi_controller_get_devdata(mem->spi->master); in npcm_fiu_uma_read()
326 regmap_update_bits(fiu->regmap, NPCM_FIU_UMA_CTS, in npcm_fiu_uma_read()
328 (mem->spi->chip_select << in npcm_fiu_uma_read()
330 regmap_update_bits(fiu->regmap, NPCM_FIU_UMA_CMD, in npcm_fiu_uma_read()
331 NPCM_FIU_UMA_CMD_CMD, op->cmd.opcode); in npcm_fiu_uma_read()
334 uma_cfg |= ilog2(op->cmd.buswidth); in npcm_fiu_uma_read()
335 uma_cfg |= ilog2(op->addr.buswidth) in npcm_fiu_uma_read()
337 if (op->dummy.nbytes) in npcm_fiu_uma_read()
338 uma_cfg |= ilog2(op->dummy.buswidth) in npcm_fiu_uma_read()
340 uma_cfg |= ilog2(op->data.buswidth) in npcm_fiu_uma_read()
342 uma_cfg |= op->dummy.nbytes << NPCM_FIU_UMA_CFG_DBSIZ_SHIFT; in npcm_fiu_uma_read()
343 uma_cfg |= op->addr.nbytes << NPCM_FIU_UMA_CFG_ADDSIZ_SHIFT; in npcm_fiu_uma_read()
344 regmap_write(fiu->regmap, NPCM_FIU_UMA_ADDR, addr); in npcm_fiu_uma_read()
346 regmap_write(fiu->regmap, NPCM_FIU_UMA_ADDR, 0x0); in npcm_fiu_uma_read()
350 regmap_write(fiu->regmap, NPCM_FIU_UMA_CFG, uma_cfg); in npcm_fiu_uma_read()
351 regmap_write_bits(fiu->regmap, NPCM_FIU_UMA_CTS, in npcm_fiu_uma_read()
354 ret = regmap_read_poll_timeout(fiu->regmap, NPCM_FIU_UMA_CTS, val, in npcm_fiu_uma_read()
362 regmap_read(fiu->regmap, NPCM_FIU_UMA_DR0 + (i * 4), in npcm_fiu_uma_read()
375 spi_controller_get_devdata(mem->spi->master); in npcm_fiu_uma_write()
381 regmap_update_bits(fiu->regmap, NPCM_FIU_UMA_CTS, in npcm_fiu_uma_write()
383 (mem->spi->chip_select << in npcm_fiu_uma_write()
386 regmap_update_bits(fiu->regmap, NPCM_FIU_UMA_CMD, in npcm_fiu_uma_write()
392 regmap_write(fiu->regmap, NPCM_FIU_UMA_DW0 + (i * 4), in npcm_fiu_uma_write()
397 uma_cfg |= ilog2(op->cmd.buswidth); in npcm_fiu_uma_write()
398 uma_cfg |= ilog2(op->addr.buswidth) << in npcm_fiu_uma_write()
400 uma_cfg |= ilog2(op->data.buswidth) << in npcm_fiu_uma_write()
402 uma_cfg |= op->addr.nbytes << NPCM_FIU_UMA_CFG_ADDSIZ_SHIFT; in npcm_fiu_uma_write()
403 regmap_write(fiu->regmap, NPCM_FIU_UMA_ADDR, op->addr.val); in npcm_fiu_uma_write()
405 regmap_write(fiu->regmap, NPCM_FIU_UMA_ADDR, 0x0); in npcm_fiu_uma_write()
409 regmap_write(fiu->regmap, NPCM_FIU_UMA_CFG, uma_cfg); in npcm_fiu_uma_write()
411 regmap_write_bits(fiu->regmap, NPCM_FIU_UMA_CTS, in npcm_fiu_uma_write()
415 return regmap_read_poll_timeout(fiu->regmap, NPCM_FIU_UMA_CTS, val, in npcm_fiu_uma_write()
424 spi_controller_get_devdata(mem->spi->master); in npcm_fiu_manualwrite()
425 u8 *data = (u8 *)op->data.buf.out; in npcm_fiu_manualwrite()
431 num_data_chunks = op->data.nbytes / CHUNK_SIZE; in npcm_fiu_manualwrite()
432 remain_data = op->data.nbytes % CHUNK_SIZE; in npcm_fiu_manualwrite()
434 regmap_update_bits(fiu->regmap, NPCM_FIU_UMA_CTS, in npcm_fiu_manualwrite()
436 (mem->spi->chip_select << in npcm_fiu_manualwrite()
438 regmap_update_bits(fiu->regmap, NPCM_FIU_UMA_CTS, in npcm_fiu_manualwrite()
441 ret = npcm_fiu_uma_write(mem, op, op->cmd.opcode, true, NULL, 0); in npcm_fiu_manualwrite()
448 &data[1], CHUNK_SIZE - 1); in npcm_fiu_manualwrite()
458 &data[1], remain_data - 1); in npcm_fiu_manualwrite()
463 regmap_update_bits(fiu->regmap, NPCM_FIU_UMA_CTS, in npcm_fiu_manualwrite()
471 u8 *data = op->data.buf.in; in npcm_fiu_read()
478 currlen = op->data.nbytes; in npcm_fiu_read()
481 addr = ((u32)op->addr.val + i); in npcm_fiu_read()
494 currlen -= 16; in npcm_fiu_read()
502 regmap_write(fiu->regmap, NPCM_FIU_DWR_CFG, in npcm_fiux_set_direct_wr()
504 regmap_update_bits(fiu->regmap, NPCM_FIU_DWR_CFG, in npcm_fiux_set_direct_wr()
507 regmap_update_bits(fiu->regmap, NPCM_FIU_DWR_CFG, in npcm_fiux_set_direct_wr()
516 regmap_write(fiu->regmap, NPCM_FIU_DRD_CFG, in npcm_fiux_set_direct_rd()
518 regmap_update_bits(fiu->regmap, NPCM_FIU_DRD_CFG, in npcm_fiux_set_direct_rd()
521 regmap_update_bits(fiu->regmap, NPCM_FIU_DRD_CFG, in npcm_fiux_set_direct_rd()
529 spi_controller_get_devdata(mem->spi->master); in npcm_fiu_exec_op()
530 struct npcm_fiu_chip *chip = &fiu->chip[mem->spi->chip_select]; in npcm_fiu_exec_op()
534 dev_dbg(fiu->dev, "cmd:%#x mode:%d.%d.%d.%d addr:%#llx len:%#x\n", in npcm_fiu_exec_op()
535 op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth, in npcm_fiu_exec_op()
536 op->dummy.buswidth, op->data.buswidth, op->addr.val, in npcm_fiu_exec_op()
537 op->data.nbytes); in npcm_fiu_exec_op()
539 if (fiu->spix_mode || op->addr.nbytes > 4) in npcm_fiu_exec_op()
540 return -ENOTSUPP; in npcm_fiu_exec_op()
542 if (fiu->clkrate != chip->clkrate) { in npcm_fiu_exec_op()
543 ret = clk_set_rate(fiu->clk, chip->clkrate); in npcm_fiu_exec_op()
545 dev_warn(fiu->dev, "Failed setting %lu frequency, stay at %lu frequency\n", in npcm_fiu_exec_op()
546 chip->clkrate, fiu->clkrate); in npcm_fiu_exec_op()
548 fiu->clkrate = chip->clkrate; in npcm_fiu_exec_op()
551 if (op->data.dir == SPI_MEM_DATA_IN) { in npcm_fiu_exec_op()
552 if (!op->addr.nbytes) { in npcm_fiu_exec_op()
553 buf = op->data.buf.in; in npcm_fiu_exec_op()
554 ret = npcm_fiu_uma_read(mem, op, op->addr.val, false, in npcm_fiu_exec_op()
555 buf, op->data.nbytes); in npcm_fiu_exec_op()
560 if (!op->addr.nbytes && !op->data.nbytes) in npcm_fiu_exec_op()
561 ret = npcm_fiu_uma_write(mem, op, op->cmd.opcode, false, in npcm_fiu_exec_op()
563 if (op->addr.nbytes && !op->data.nbytes) { in npcm_fiu_exec_op()
566 u32 addr = op->addr.val; in npcm_fiu_exec_op()
568 for (i = op->addr.nbytes - 1; i >= 0; i--) { in npcm_fiu_exec_op()
572 ret = npcm_fiu_uma_write(mem, op, op->cmd.opcode, false, in npcm_fiu_exec_op()
573 buf_addr, op->addr.nbytes); in npcm_fiu_exec_op()
575 if (!op->addr.nbytes && op->data.nbytes) in npcm_fiu_exec_op()
576 ret = npcm_fiu_uma_write(mem, op, op->cmd.opcode, false, in npcm_fiu_exec_op()
577 (u8 *)op->data.buf.out, in npcm_fiu_exec_op()
578 op->data.nbytes); in npcm_fiu_exec_op()
579 if (op->addr.nbytes && op->data.nbytes) in npcm_fiu_exec_op()
589 spi_controller_get_devdata(desc->mem->spi->master); in npcm_fiu_dirmap_create()
590 struct npcm_fiu_chip *chip = &fiu->chip[desc->mem->spi->chip_select]; in npcm_fiu_dirmap_create()
593 if (!fiu->res_mem) { in npcm_fiu_dirmap_create()
594 dev_warn(fiu->dev, "Reserved memory not defined, direct read disabled\n"); in npcm_fiu_dirmap_create()
595 desc->nodirmap = true; in npcm_fiu_dirmap_create()
599 if (!fiu->spix_mode && in npcm_fiu_dirmap_create()
600 desc->info.op_tmpl.data.dir == SPI_MEM_DATA_OUT) { in npcm_fiu_dirmap_create()
601 desc->nodirmap = true; in npcm_fiu_dirmap_create()
605 if (!chip->flash_region_mapped_ptr) { in npcm_fiu_dirmap_create()
606 chip->flash_region_mapped_ptr = in npcm_fiu_dirmap_create()
607 devm_ioremap(fiu->dev, (fiu->res_mem->start + in npcm_fiu_dirmap_create()
608 (fiu->info->max_map_size * in npcm_fiu_dirmap_create()
609 desc->mem->spi->chip_select)), in npcm_fiu_dirmap_create()
610 (u32)desc->info.length); in npcm_fiu_dirmap_create()
611 if (!chip->flash_region_mapped_ptr) { in npcm_fiu_dirmap_create()
612 dev_warn(fiu->dev, "Error mapping memory region, direct read disabled\n"); in npcm_fiu_dirmap_create()
613 desc->nodirmap = true; in npcm_fiu_dirmap_create()
618 if (of_device_is_compatible(fiu->dev->of_node, "nuvoton,npcm750-fiu")) { in npcm_fiu_dirmap_create()
620 syscon_regmap_lookup_by_compatible("nuvoton,npcm750-gcr"); in npcm_fiu_dirmap_create()
622 dev_warn(fiu->dev, "Didn't find nuvoton,npcm750-gcr, direct read disabled\n"); in npcm_fiu_dirmap_create()
623 desc->nodirmap = true; in npcm_fiu_dirmap_create()
631 if (desc->info.op_tmpl.data.dir == SPI_MEM_DATA_IN) { in npcm_fiu_dirmap_create()
632 if (!fiu->spix_mode) in npcm_fiu_dirmap_create()
633 npcm_fiu_set_drd(fiu, &desc->info.op_tmpl); in npcm_fiu_dirmap_create()
644 static int npcm_fiu_setup(struct spi_device *spi) in npcm_fiu_setup() argument
646 struct spi_controller *ctrl = spi->master; in npcm_fiu_setup()
650 chip = &fiu->chip[spi->chip_select]; in npcm_fiu_setup()
651 chip->fiu = fiu; in npcm_fiu_setup()
652 chip->chipselect = spi->chip_select; in npcm_fiu_setup()
653 chip->clkrate = spi->max_speed_hz; in npcm_fiu_setup()
655 fiu->clkrate = clk_get_rate(fiu->clk); in npcm_fiu_setup()
668 { .compatible = "nuvoton,npcm750-fiu", .data = &npxm7xx_fiu_data },
676 struct device *dev = &pdev->dev; in npcm_fiu_probe()
685 return -ENOMEM; in npcm_fiu_probe()
690 if (!match || !match->data) { in npcm_fiu_probe()
692 return -ENODEV; in npcm_fiu_probe()
695 fiu_data_match = match->data; in npcm_fiu_probe()
696 id = of_alias_get_id(dev->of_node, "fiu"); in npcm_fiu_probe()
697 if (id < 0 || id >= fiu_data_match->fiu_max) { in npcm_fiu_probe()
699 return -EINVAL; in npcm_fiu_probe()
702 fiu->info = &fiu_data_match->npcm_fiu_data_info[id]; in npcm_fiu_probe()
705 fiu->dev = dev; in npcm_fiu_probe()
712 fiu->regmap = devm_regmap_init_mmio(dev, regbase, in npcm_fiu_probe()
714 if (IS_ERR(fiu->regmap)) { in npcm_fiu_probe()
716 return PTR_ERR(fiu->regmap); in npcm_fiu_probe()
719 fiu->res_mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, in npcm_fiu_probe()
721 fiu->clk = devm_clk_get(dev, NULL); in npcm_fiu_probe()
722 if (IS_ERR(fiu->clk)) in npcm_fiu_probe()
723 return PTR_ERR(fiu->clk); in npcm_fiu_probe()
725 fiu->spix_mode = of_property_read_bool(dev->of_node, in npcm_fiu_probe()
726 "nuvoton,spix-mode"); in npcm_fiu_probe()
729 clk_prepare_enable(fiu->clk); in npcm_fiu_probe()
731 ctrl->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD in npcm_fiu_probe()
733 ctrl->setup = npcm_fiu_setup; in npcm_fiu_probe()
734 ctrl->bus_num = -1; in npcm_fiu_probe()
735 ctrl->mem_ops = &npcm_fiu_mem_ops; in npcm_fiu_probe()
736 ctrl->num_chipselect = fiu->info->max_cs; in npcm_fiu_probe()
737 ctrl->dev.of_node = dev->of_node; in npcm_fiu_probe()
741 clk_disable_unprepare(fiu->clk); in npcm_fiu_probe()
750 clk_disable_unprepare(fiu->clk); in npcm_fiu_remove()
758 .name = "NPCM-FIU",
767 MODULE_DESCRIPTION("Nuvoton FLASH Interface Unit SPI Controller Driver");