Lines Matching +full:cs +full:- +full:to +full:- +full:clk
1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright 2006-2009 Simtec Electronics
13 #include <linux/clk.h>
22 #include <linux/spi/s3c24xx-fiq.h>
27 #include "spi-s3c24xx-regs.h"
30 * struct s3c24xx_spi_devstate - per device data
33 * @spcon: Value to write to the SPCON register.
34 * @sppre: Value to write to the SPPRE register.
51 /* bitbang has to be first */
66 int cs, int pol);
72 struct clk *clk; member
84 return spi_master_get_devdata(sdev->master); in to_hw()
87 static void s3c24xx_spi_gpiocs(struct s3c2410_spi_info *spi, int cs, int pol) in s3c24xx_spi_gpiocs() argument
89 gpio_set_value(spi->pin_cs, pol); in s3c24xx_spi_gpiocs()
94 struct s3c24xx_spi_devstate *cs = spi->controller_state; in s3c24xx_spi_chipsel() local
96 unsigned int cspol = spi->mode & SPI_CS_HIGH ? 1 : 0; in s3c24xx_spi_chipsel()
102 hw->set_cs(hw->pdata, spi->chip_select, cspol^1); in s3c24xx_spi_chipsel()
103 writeb(cs->spcon, hw->regs + S3C2410_SPCON); in s3c24xx_spi_chipsel()
107 writeb(cs->spcon | S3C2410_SPCON_ENSCK, in s3c24xx_spi_chipsel()
108 hw->regs + S3C2410_SPCON); in s3c24xx_spi_chipsel()
109 hw->set_cs(hw->pdata, spi->chip_select, cspol); in s3c24xx_spi_chipsel()
118 struct s3c24xx_spi_devstate *cs = spi->controller_state; in s3c24xx_spi_update_state() local
121 unsigned long clk; in s3c24xx_spi_update_state() local
123 hz = t ? t->speed_hz : spi->max_speed_hz; in s3c24xx_spi_update_state()
126 hz = spi->max_speed_hz; in s3c24xx_spi_update_state()
128 if (spi->mode != cs->mode) { in s3c24xx_spi_update_state()
131 if (spi->mode & SPI_CPHA) in s3c24xx_spi_update_state()
134 if (spi->mode & SPI_CPOL) in s3c24xx_spi_update_state()
137 cs->mode = spi->mode; in s3c24xx_spi_update_state()
138 cs->spcon = spcon; in s3c24xx_spi_update_state()
141 if (cs->hz != hz) { in s3c24xx_spi_update_state()
142 clk = clk_get_rate(hw->clk); in s3c24xx_spi_update_state()
143 div = DIV_ROUND_UP(clk, hz * 2) - 1; in s3c24xx_spi_update_state()
148 dev_dbg(&spi->dev, "pre-scaler=%d (wanted %d, got %ld)\n", in s3c24xx_spi_update_state()
149 div, hz, clk / (2 * (div + 1))); in s3c24xx_spi_update_state()
151 cs->hz = hz; in s3c24xx_spi_update_state()
152 cs->sppre = div; in s3c24xx_spi_update_state()
161 struct s3c24xx_spi_devstate *cs = spi->controller_state; in s3c24xx_spi_setupxfer() local
167 writeb(cs->sppre, hw->regs + S3C2410_SPPRE); in s3c24xx_spi_setupxfer()
174 struct s3c24xx_spi_devstate *cs = spi->controller_state; in s3c24xx_spi_setup() local
179 if (!cs) { in s3c24xx_spi_setup()
180 cs = devm_kzalloc(&spi->dev, in s3c24xx_spi_setup()
183 if (!cs) in s3c24xx_spi_setup()
184 return -ENOMEM; in s3c24xx_spi_setup()
186 cs->spcon = SPCON_DEFAULT; in s3c24xx_spi_setup()
187 cs->hz = -1; in s3c24xx_spi_setup()
188 spi->controller_state = cs; in s3c24xx_spi_setup()
196 mutex_lock(&hw->bitbang.lock); in s3c24xx_spi_setup()
197 if (!hw->bitbang.busy) { in s3c24xx_spi_setup()
198 hw->bitbang.chipselect(spi, BITBANG_CS_INACTIVE); in s3c24xx_spi_setup()
199 /* need to ndelay for 0.5 clocktick ? */ in s3c24xx_spi_setup()
201 mutex_unlock(&hw->bitbang.lock); in s3c24xx_spi_setup()
208 return hw->tx ? hw->tx[count] : 0; in hw_txbyte()
212 /* Support for FIQ based pseudo-DMA to improve the transfer speed.
215 * used by the FIQ core to move data between main memory and the peripheral
221 * struct spi_fiq_code - FIQ code and header
223 * @ack_offset: The offset from @data to the word to place the IRQ ACK bit at.
224 * @data: The code itself to install as a FIQ handler.
233 * s3c24xx_spi_tryfiq - attempt to claim and setup FIQ for transfer
240 * so the caller does not need to do anything more than start the transfer
241 * as normal, since the IRQ will have been re-routed to the FIQ handler.
251 if (!hw->fiq_claimed) { in s3c24xx_spi_tryfiq()
255 ret = claim_fiq(&hw->fiq_handler); in s3c24xx_spi_tryfiq()
260 if (hw->tx && !hw->rx) in s3c24xx_spi_tryfiq()
262 else if (hw->rx && !hw->tx) in s3c24xx_spi_tryfiq()
267 regs.uregs[fiq_rspi] = (long)hw->regs; in s3c24xx_spi_tryfiq()
268 regs.uregs[fiq_rrx] = (long)hw->rx; in s3c24xx_spi_tryfiq()
269 regs.uregs[fiq_rtx] = (long)hw->tx + 1; in s3c24xx_spi_tryfiq()
270 regs.uregs[fiq_rcount] = hw->len - 1; in s3c24xx_spi_tryfiq()
274 if (hw->fiq_mode != mode) { in s3c24xx_spi_tryfiq()
275 hw->fiq_mode = mode; in s3c24xx_spi_tryfiq()
293 ack_ptr = (u32 *)&code->data[code->ack_offset]; in s3c24xx_spi_tryfiq()
294 set_fiq_handler(&code->data, code->length); in s3c24xx_spi_tryfiq()
297 s3c24xx_set_fiq(hw->irq, ack_ptr, true); in s3c24xx_spi_tryfiq()
299 hw->fiq_mode = mode; in s3c24xx_spi_tryfiq()
300 hw->fiq_inuse = 1; in s3c24xx_spi_tryfiq()
304 * s3c24xx_spi_fiqop - FIQ core code callback
308 * Called by the FIQ code when another module wants to use the FIQ, so
318 if (hw->fiq_inuse) in s3c24xx_spi_fiqop()
319 ret = -EBUSY; in s3c24xx_spi_fiqop()
321 /* note, we do not need to unroute the FIQ, as the FIQ in s3c24xx_spi_fiqop()
322 * vector code de-routes it to signal the end of transfer */ in s3c24xx_spi_fiqop()
324 hw->fiq_mode = FIQ_MODE_NONE; in s3c24xx_spi_fiqop()
325 hw->fiq_claimed = 0; in s3c24xx_spi_fiqop()
327 hw->fiq_claimed = 1; in s3c24xx_spi_fiqop()
334 * s3c24xx_spi_initfiq - setup the information for the FIQ core
337 * Setup the fiq_handler block to pass to the FIQ core.
341 hw->fiq_handler.dev_id = hw; in s3c24xx_spi_initfiq()
342 hw->fiq_handler.name = dev_name(hw->dev); in s3c24xx_spi_initfiq()
343 hw->fiq_handler.fiq_op = s3c24xx_spi_fiqop; in s3c24xx_spi_initfiq()
347 * s3c24xx_spi_usefiq - return if we should be using FIQ.
351 * allowed to use the FIQ.
355 return hw->pdata->use_fiq; in s3c24xx_spi_usefiq()
359 * s3c24xx_spi_usingfiq - return if channel is using FIQ
367 return spi->fiq_inuse; in s3c24xx_spi_usingfiq()
382 hw->tx = t->tx_buf; in s3c24xx_spi_txrx()
383 hw->rx = t->rx_buf; in s3c24xx_spi_txrx()
384 hw->len = t->len; in s3c24xx_spi_txrx()
385 hw->count = 0; in s3c24xx_spi_txrx()
387 init_completion(&hw->done); in s3c24xx_spi_txrx()
389 hw->fiq_inuse = 0; in s3c24xx_spi_txrx()
390 if (s3c24xx_spi_usefiq(hw) && t->len >= 3) in s3c24xx_spi_txrx()
394 writeb(hw_txbyte(hw, 0), hw->regs + S3C2410_SPTDAT); in s3c24xx_spi_txrx()
396 wait_for_completion(&hw->done); in s3c24xx_spi_txrx()
397 return hw->count; in s3c24xx_spi_txrx()
403 unsigned int spsta = readb(hw->regs + S3C2410_SPSTA); in s3c24xx_spi_irq()
404 unsigned int count = hw->count; in s3c24xx_spi_irq()
407 dev_dbg(hw->dev, "data-collision\n"); in s3c24xx_spi_irq()
408 complete(&hw->done); in s3c24xx_spi_irq()
413 dev_dbg(hw->dev, "spi not ready for tx?\n"); in s3c24xx_spi_irq()
414 complete(&hw->done); in s3c24xx_spi_irq()
419 hw->count++; in s3c24xx_spi_irq()
421 if (hw->rx) in s3c24xx_spi_irq()
422 hw->rx[count] = readb(hw->regs + S3C2410_SPRDAT); in s3c24xx_spi_irq()
426 if (count < hw->len) in s3c24xx_spi_irq()
427 writeb(hw_txbyte(hw, count), hw->regs + S3C2410_SPTDAT); in s3c24xx_spi_irq()
429 complete(&hw->done); in s3c24xx_spi_irq()
431 hw->count = hw->len; in s3c24xx_spi_irq()
432 hw->fiq_inuse = 0; in s3c24xx_spi_irq()
434 if (hw->rx) in s3c24xx_spi_irq()
435 hw->rx[hw->len-1] = readb(hw->regs + S3C2410_SPRDAT); in s3c24xx_spi_irq()
437 complete(&hw->done); in s3c24xx_spi_irq()
448 clk_enable(hw->clk); in s3c24xx_spi_initialsetup()
452 writeb(0xff, hw->regs + S3C2410_SPPRE); in s3c24xx_spi_initialsetup()
453 writeb(SPPIN_DEFAULT, hw->regs + S3C2410_SPPIN); in s3c24xx_spi_initialsetup()
454 writeb(SPCON_DEFAULT, hw->regs + S3C2410_SPCON); in s3c24xx_spi_initialsetup()
456 if (hw->pdata) { in s3c24xx_spi_initialsetup()
457 if (hw->set_cs == s3c24xx_spi_gpiocs) in s3c24xx_spi_initialsetup()
458 gpio_direction_output(hw->pdata->pin_cs, 1); in s3c24xx_spi_initialsetup()
460 if (hw->pdata->gpio_setup) in s3c24xx_spi_initialsetup()
461 hw->pdata->gpio_setup(hw->pdata, 1); in s3c24xx_spi_initialsetup()
472 master = spi_alloc_master(&pdev->dev, sizeof(struct s3c24xx_spi)); in s3c24xx_spi_probe()
474 dev_err(&pdev->dev, "No memory for spi_master\n"); in s3c24xx_spi_probe()
475 return -ENOMEM; in s3c24xx_spi_probe()
480 hw->master = master; in s3c24xx_spi_probe()
481 hw->pdata = pdata = dev_get_platdata(&pdev->dev); in s3c24xx_spi_probe()
482 hw->dev = &pdev->dev; in s3c24xx_spi_probe()
485 dev_err(&pdev->dev, "No platform data supplied\n"); in s3c24xx_spi_probe()
486 err = -ENOENT; in s3c24xx_spi_probe()
491 init_completion(&hw->done); in s3c24xx_spi_probe()
499 /* the spi->mode bits understood by this driver: */ in s3c24xx_spi_probe()
500 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; in s3c24xx_spi_probe()
502 master->num_chipselect = hw->pdata->num_cs; in s3c24xx_spi_probe()
503 master->bus_num = pdata->bus_num; in s3c24xx_spi_probe()
504 master->bits_per_word_mask = SPI_BPW_MASK(8); in s3c24xx_spi_probe()
508 hw->bitbang.master = hw->master; in s3c24xx_spi_probe()
509 hw->bitbang.setup_transfer = s3c24xx_spi_setupxfer; in s3c24xx_spi_probe()
510 hw->bitbang.chipselect = s3c24xx_spi_chipsel; in s3c24xx_spi_probe()
511 hw->bitbang.txrx_bufs = s3c24xx_spi_txrx; in s3c24xx_spi_probe()
513 hw->master->setup = s3c24xx_spi_setup; in s3c24xx_spi_probe()
515 dev_dbg(hw->dev, "bitbang at %p\n", &hw->bitbang); in s3c24xx_spi_probe()
518 hw->regs = devm_platform_ioremap_resource(pdev, 0); in s3c24xx_spi_probe()
519 if (IS_ERR(hw->regs)) { in s3c24xx_spi_probe()
520 err = PTR_ERR(hw->regs); in s3c24xx_spi_probe()
524 hw->irq = platform_get_irq(pdev, 0); in s3c24xx_spi_probe()
525 if (hw->irq < 0) { in s3c24xx_spi_probe()
526 err = -ENOENT; in s3c24xx_spi_probe()
530 err = devm_request_irq(&pdev->dev, hw->irq, s3c24xx_spi_irq, 0, in s3c24xx_spi_probe()
531 pdev->name, hw); in s3c24xx_spi_probe()
533 dev_err(&pdev->dev, "Cannot claim IRQ\n"); in s3c24xx_spi_probe()
537 hw->clk = devm_clk_get(&pdev->dev, "spi"); in s3c24xx_spi_probe()
538 if (IS_ERR(hw->clk)) { in s3c24xx_spi_probe()
539 dev_err(&pdev->dev, "No clock for device\n"); in s3c24xx_spi_probe()
540 err = PTR_ERR(hw->clk); in s3c24xx_spi_probe()
546 if (!pdata->set_cs) { in s3c24xx_spi_probe()
547 if (pdata->pin_cs < 0) { in s3c24xx_spi_probe()
548 dev_err(&pdev->dev, "No chipselect pin\n"); in s3c24xx_spi_probe()
549 err = -EINVAL; in s3c24xx_spi_probe()
553 err = devm_gpio_request(&pdev->dev, pdata->pin_cs, in s3c24xx_spi_probe()
554 dev_name(&pdev->dev)); in s3c24xx_spi_probe()
556 dev_err(&pdev->dev, "Failed to get gpio for cs\n"); in s3c24xx_spi_probe()
560 hw->set_cs = s3c24xx_spi_gpiocs; in s3c24xx_spi_probe()
561 gpio_direction_output(pdata->pin_cs, 1); in s3c24xx_spi_probe()
563 hw->set_cs = pdata->set_cs; in s3c24xx_spi_probe()
569 err = spi_bitbang_start(&hw->bitbang); in s3c24xx_spi_probe()
571 dev_err(&pdev->dev, "Failed to register SPI master\n"); in s3c24xx_spi_probe()
578 clk_disable(hw->clk); in s3c24xx_spi_probe()
581 spi_master_put(hw->master); in s3c24xx_spi_probe()
589 spi_bitbang_stop(&hw->bitbang); in s3c24xx_spi_remove()
590 clk_disable(hw->clk); in s3c24xx_spi_remove()
591 spi_master_put(hw->master); in s3c24xx_spi_remove()
603 ret = spi_master_suspend(hw->master); in s3c24xx_spi_suspend()
607 if (hw->pdata && hw->pdata->gpio_setup) in s3c24xx_spi_suspend()
608 hw->pdata->gpio_setup(hw->pdata, 0); in s3c24xx_spi_suspend()
610 clk_disable(hw->clk); in s3c24xx_spi_suspend()
619 return spi_master_resume(hw->master); in s3c24xx_spi_resume()
632 MODULE_ALIAS("platform:s3c2410-spi");
637 .name = "s3c2410-spi",