Lines Matching +full:spi +full:- +full:feedback +full:- +full:delay
1 // SPDX-License-Identifier: GPL-2.0+
9 #include <linux/delay.h>
11 #include <linux/dma-mapping.h>
15 #include <linux/spi/spi.h>
20 #include <linux/platform_data/spi-s3c64xx.h>
27 /* Registers and bit-fields */
106 #define FIFO_LVL_MASK(i) ((i)->port_conf->fifo_lvl_mask[i->port_id])
108 (1 << (i)->port_conf->tx_st_done)) ? 1 : 0)
110 #define RX_FIFO_LVL(v, i) (((v) >> (i)->port_conf->rx_lvl_offset) & \
119 #define is_polling(x) (x->port_conf->quirks & S3C64XX_SPI_QUIRK_POLL)
131 * struct s3c64xx_spi_info - SPI Controller hardware info
132 * @fifo_lvl_mask: Bit-mask for {TX|RX}_FIFO_LVL bits in SPI_STATUS register.
141 * The Samsung s3c64xx SPI controller are used on various Samsung SoC's but
142 * differ in some aspects such as the size of the fifo and spi bus clock
157 * struct s3c64xx_spi_driver_data - Runtime info holder for SPI driver.
158 * @clk: Pointer to the spi clock.
159 * @src_clk: Pointer to the clock used to generate SPI signals.
162 * @master: Pointer to the SPI Protocol master.
166 * @sfr_start: BUS address of SPI controller regs.
174 * @port_conf: Local SPI port configuartion data
199 void __iomem *regs = sdd->regs; in s3c64xx_flush_fifo()
218 } while (TX_FIFO_LVL(val, sdd) && loops--); in s3c64xx_flush_fifo()
221 dev_warn(&sdd->pdev->dev, "Timed out flushing TX FIFO\n"); in s3c64xx_flush_fifo()
231 } while (loops--); in s3c64xx_flush_fifo()
234 dev_warn(&sdd->pdev->dev, "Timed out flushing RX FIFO\n"); in s3c64xx_flush_fifo()
251 if (dma->direction == DMA_DEV_TO_MEM) in s3c64xx_spi_dmacb()
258 spin_lock_irqsave(&sdd->lock, flags); in s3c64xx_spi_dmacb()
260 if (dma->direction == DMA_DEV_TO_MEM) { in s3c64xx_spi_dmacb()
261 sdd->state &= ~RXBUSY; in s3c64xx_spi_dmacb()
262 if (!(sdd->state & TXBUSY)) in s3c64xx_spi_dmacb()
263 complete(&sdd->xfer_completion); in s3c64xx_spi_dmacb()
265 sdd->state &= ~TXBUSY; in s3c64xx_spi_dmacb()
266 if (!(sdd->state & RXBUSY)) in s3c64xx_spi_dmacb()
267 complete(&sdd->xfer_completion); in s3c64xx_spi_dmacb()
270 spin_unlock_irqrestore(&sdd->lock, flags); in s3c64xx_spi_dmacb()
283 if (dma->direction == DMA_DEV_TO_MEM) { in prepare_dma()
286 config.direction = dma->direction; in prepare_dma()
287 config.src_addr = sdd->sfr_start + S3C64XX_SPI_RX_DATA; in prepare_dma()
288 config.src_addr_width = sdd->cur_bpw / 8; in prepare_dma()
290 dmaengine_slave_config(dma->ch, &config); in prepare_dma()
294 config.direction = dma->direction; in prepare_dma()
295 config.dst_addr = sdd->sfr_start + S3C64XX_SPI_TX_DATA; in prepare_dma()
296 config.dst_addr_width = sdd->cur_bpw / 8; in prepare_dma()
298 dmaengine_slave_config(dma->ch, &config); in prepare_dma()
301 desc = dmaengine_prep_slave_sg(dma->ch, sgt->sgl, sgt->nents, in prepare_dma()
302 dma->direction, DMA_PREP_INTERRUPT); in prepare_dma()
304 dev_err(&sdd->pdev->dev, "unable to prepare %s scatterlist", in prepare_dma()
305 dma->direction == DMA_DEV_TO_MEM ? "rx" : "tx"); in prepare_dma()
306 return -ENOMEM; in prepare_dma()
309 desc->callback = s3c64xx_spi_dmacb; in prepare_dma()
310 desc->callback_param = dma; in prepare_dma()
312 dma->cookie = dmaengine_submit(desc); in prepare_dma()
313 ret = dma_submit_error(dma->cookie); in prepare_dma()
315 dev_err(&sdd->pdev->dev, "DMA submission failed"); in prepare_dma()
316 return -EIO; in prepare_dma()
319 dma_async_issue_pending(dma->ch); in prepare_dma()
323 static void s3c64xx_spi_set_cs(struct spi_device *spi, bool enable) in s3c64xx_spi_set_cs() argument
326 spi_master_get_devdata(spi->master); in s3c64xx_spi_set_cs()
328 if (sdd->cntrlr_info->no_cs) in s3c64xx_spi_set_cs()
332 if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO)) { in s3c64xx_spi_set_cs()
333 writel(0, sdd->regs + S3C64XX_SPI_CS_REG); in s3c64xx_spi_set_cs()
335 u32 ssel = readl(sdd->regs + S3C64XX_SPI_CS_REG); in s3c64xx_spi_set_cs()
339 writel(ssel, sdd->regs + S3C64XX_SPI_CS_REG); in s3c64xx_spi_set_cs()
342 if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO)) in s3c64xx_spi_set_cs()
344 sdd->regs + S3C64XX_SPI_CS_REG); in s3c64xx_spi_set_cs()
348 static int s3c64xx_spi_prepare_transfer(struct spi_master *spi) in s3c64xx_spi_prepare_transfer() argument
350 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi); in s3c64xx_spi_prepare_transfer()
355 spi->dma_rx = sdd->rx_dma.ch; in s3c64xx_spi_prepare_transfer()
356 spi->dma_tx = sdd->tx_dma.ch; in s3c64xx_spi_prepare_transfer()
362 struct spi_device *spi, in s3c64xx_spi_can_dma() argument
367 return xfer->len > (FIFO_LVL_MASK(sdd) >> 1) + 1; in s3c64xx_spi_can_dma()
373 void __iomem *regs = sdd->regs; in s3c64xx_enable_datapath()
391 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff) in s3c64xx_enable_datapath()
396 if (xfer->tx_buf != NULL) { in s3c64xx_enable_datapath()
397 sdd->state |= TXBUSY; in s3c64xx_enable_datapath()
401 ret = prepare_dma(&sdd->tx_dma, &xfer->tx_sg); in s3c64xx_enable_datapath()
403 switch (sdd->cur_bpw) { in s3c64xx_enable_datapath()
406 xfer->tx_buf, xfer->len / 4); in s3c64xx_enable_datapath()
410 xfer->tx_buf, xfer->len / 2); in s3c64xx_enable_datapath()
414 xfer->tx_buf, xfer->len); in s3c64xx_enable_datapath()
420 if (xfer->rx_buf != NULL) { in s3c64xx_enable_datapath()
421 sdd->state |= RXBUSY; in s3c64xx_enable_datapath()
423 if (sdd->port_conf->high_speed && sdd->cur_speed >= 30000000UL in s3c64xx_enable_datapath()
424 && !(sdd->cur_mode & SPI_CPHA)) in s3c64xx_enable_datapath()
430 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff) in s3c64xx_enable_datapath()
433 ret = prepare_dma(&sdd->rx_dma, &xfer->rx_sg); in s3c64xx_enable_datapath()
449 void __iomem *regs = sdd->regs; in s3c64xx_spi_wait_for_timeout()
461 } while (RX_FIFO_LVL(status, sdd) < max_fifo && --val); in s3c64xx_spi_wait_for_timeout()
470 void __iomem *regs = sdd->regs; in s3c64xx_wait_for_dma()
476 ms = xfer->len * 8 * 1000 / sdd->cur_speed; in s3c64xx_wait_for_dma()
481 val = wait_for_completion_timeout(&sdd->xfer_completion, val); in s3c64xx_wait_for_dma()
485 * proceed further else return -EIO. in s3c64xx_wait_for_dma()
492 if (val && !xfer->rx_buf) { in s3c64xx_wait_for_dma()
497 && --val) { in s3c64xx_wait_for_dma()
506 return -EIO; in s3c64xx_wait_for_dma()
514 void __iomem *regs = sdd->regs; in s3c64xx_wait_for_pio()
523 ms = xfer->len * 8 * 1000 / sdd->cur_speed; in s3c64xx_wait_for_pio()
529 } while (RX_FIFO_LVL(status, sdd) < xfer->len && --val); in s3c64xx_wait_for_pio()
532 return -EIO; in s3c64xx_wait_for_pio()
535 if (!xfer->rx_buf) { in s3c64xx_wait_for_pio()
536 sdd->state &= ~TXBUSY; in s3c64xx_wait_for_pio()
548 loops = xfer->len / ((FIFO_LVL_MASK(sdd) >> 1) + 1); in s3c64xx_wait_for_pio()
549 buf = xfer->rx_buf; in s3c64xx_wait_for_pio()
555 switch (sdd->cur_bpw) { in s3c64xx_wait_for_pio()
571 } while (loops--); in s3c64xx_wait_for_pio()
572 sdd->state &= ~RXBUSY; in s3c64xx_wait_for_pio()
579 void __iomem *regs = sdd->regs; in s3c64xx_spi_config()
584 if (!sdd->port_conf->clk_from_cmu) { in s3c64xx_spi_config()
596 if (sdd->cur_mode & SPI_CPOL) in s3c64xx_spi_config()
599 if (sdd->cur_mode & SPI_CPHA) in s3c64xx_spi_config()
609 switch (sdd->cur_bpw) { in s3c64xx_spi_config()
626 if (sdd->port_conf->clk_from_cmu) { in s3c64xx_spi_config()
628 ret = clk_set_rate(sdd->src_clk, sdd->cur_speed * 2); in s3c64xx_spi_config()
631 sdd->cur_speed = clk_get_rate(sdd->src_clk) / 2; in s3c64xx_spi_config()
636 val |= ((clk_get_rate(sdd->src_clk) / sdd->cur_speed / 2 - 1) in s3c64xx_spi_config()
655 struct spi_device *spi = msg->spi; in s3c64xx_spi_prepare_message() local
656 struct s3c64xx_spi_csinfo *cs = spi->controller_data; in s3c64xx_spi_prepare_message()
658 /* Configure feedback delay */ in s3c64xx_spi_prepare_message()
659 writel(cs->fb_delay & 0x3, sdd->regs + S3C64XX_SPI_FB_CLK); in s3c64xx_spi_prepare_message()
664 static size_t s3c64xx_spi_max_transfer_size(struct spi_device *spi) in s3c64xx_spi_max_transfer_size() argument
666 struct spi_controller *ctlr = spi->controller; in s3c64xx_spi_max_transfer_size()
668 return ctlr->can_dma ? S3C64XX_SPI_PACKET_CNT_MASK : SIZE_MAX; in s3c64xx_spi_max_transfer_size()
672 struct spi_device *spi, in s3c64xx_spi_transfer_one() argument
686 reinit_completion(&sdd->xfer_completion); in s3c64xx_spi_transfer_one()
689 bpw = xfer->bits_per_word; in s3c64xx_spi_transfer_one()
690 speed = xfer->speed_hz; in s3c64xx_spi_transfer_one()
692 if (bpw != sdd->cur_bpw || speed != sdd->cur_speed) { in s3c64xx_spi_transfer_one()
693 sdd->cur_bpw = bpw; in s3c64xx_spi_transfer_one()
694 sdd->cur_speed = speed; in s3c64xx_spi_transfer_one()
695 sdd->cur_mode = spi->mode; in s3c64xx_spi_transfer_one()
701 if (!is_polling(sdd) && (xfer->len > fifo_len) && in s3c64xx_spi_transfer_one()
702 sdd->rx_dma.ch && sdd->tx_dma.ch) { in s3c64xx_spi_transfer_one()
705 } else if (is_polling(sdd) && xfer->len > fifo_len) { in s3c64xx_spi_transfer_one()
706 tx_buf = xfer->tx_buf; in s3c64xx_spi_transfer_one()
707 rx_buf = xfer->rx_buf; in s3c64xx_spi_transfer_one()
708 origin_len = xfer->len; in s3c64xx_spi_transfer_one()
710 target_len = xfer->len; in s3c64xx_spi_transfer_one()
711 if (xfer->len > fifo_len) in s3c64xx_spi_transfer_one()
712 xfer->len = fifo_len; in s3c64xx_spi_transfer_one()
716 spin_lock_irqsave(&sdd->lock, flags); in s3c64xx_spi_transfer_one()
719 sdd->state &= ~RXBUSY; in s3c64xx_spi_transfer_one()
720 sdd->state &= ~TXBUSY; in s3c64xx_spi_transfer_one()
723 s3c64xx_spi_set_cs(spi, true); in s3c64xx_spi_transfer_one()
727 spin_unlock_irqrestore(&sdd->lock, flags); in s3c64xx_spi_transfer_one()
730 dev_err(&spi->dev, "failed to enable data path for transfer: %d\n", status); in s3c64xx_spi_transfer_one()
740 dev_err(&spi->dev, in s3c64xx_spi_transfer_one()
741 "I/O Error: rx-%d tx-%d rx-%c tx-%c len-%d dma-%d res-(%d)\n", in s3c64xx_spi_transfer_one()
742 xfer->rx_buf ? 1 : 0, xfer->tx_buf ? 1 : 0, in s3c64xx_spi_transfer_one()
743 (sdd->state & RXBUSY) ? 'f' : 'p', in s3c64xx_spi_transfer_one()
744 (sdd->state & TXBUSY) ? 'f' : 'p', in s3c64xx_spi_transfer_one()
745 xfer->len, use_dma ? 1 : 0, status); in s3c64xx_spi_transfer_one()
750 if (xfer->tx_buf && (sdd->state & TXBUSY)) { in s3c64xx_spi_transfer_one()
751 dmaengine_pause(sdd->tx_dma.ch); in s3c64xx_spi_transfer_one()
752 dmaengine_tx_status(sdd->tx_dma.ch, sdd->tx_dma.cookie, &s); in s3c64xx_spi_transfer_one()
753 dmaengine_terminate_all(sdd->tx_dma.ch); in s3c64xx_spi_transfer_one()
754 dev_err(&spi->dev, "TX residue: %d\n", s.residue); in s3c64xx_spi_transfer_one()
757 if (xfer->rx_buf && (sdd->state & RXBUSY)) { in s3c64xx_spi_transfer_one()
758 dmaengine_pause(sdd->rx_dma.ch); in s3c64xx_spi_transfer_one()
759 dmaengine_tx_status(sdd->rx_dma.ch, sdd->rx_dma.cookie, &s); in s3c64xx_spi_transfer_one()
760 dmaengine_terminate_all(sdd->rx_dma.ch); in s3c64xx_spi_transfer_one()
761 dev_err(&spi->dev, "RX residue: %d\n", s.residue); in s3c64xx_spi_transfer_one()
768 target_len -= xfer->len; in s3c64xx_spi_transfer_one()
770 if (xfer->tx_buf) in s3c64xx_spi_transfer_one()
771 xfer->tx_buf += xfer->len; in s3c64xx_spi_transfer_one()
773 if (xfer->rx_buf) in s3c64xx_spi_transfer_one()
774 xfer->rx_buf += xfer->len; in s3c64xx_spi_transfer_one()
777 xfer->len = fifo_len; in s3c64xx_spi_transfer_one()
779 xfer->len = target_len; in s3c64xx_spi_transfer_one()
785 xfer->tx_buf = tx_buf; in s3c64xx_spi_transfer_one()
786 xfer->rx_buf = rx_buf; in s3c64xx_spi_transfer_one()
787 xfer->len = origin_len; in s3c64xx_spi_transfer_one()
794 struct spi_device *spi) in s3c64xx_get_slave_ctrldata() argument
800 slave_np = spi->dev.of_node; in s3c64xx_get_slave_ctrldata()
802 dev_err(&spi->dev, "device node not found\n"); in s3c64xx_get_slave_ctrldata()
803 return ERR_PTR(-EINVAL); in s3c64xx_get_slave_ctrldata()
806 data_np = of_get_child_by_name(slave_np, "controller-data"); in s3c64xx_get_slave_ctrldata()
808 dev_err(&spi->dev, "child node 'controller-data' not found\n"); in s3c64xx_get_slave_ctrldata()
809 return ERR_PTR(-EINVAL); in s3c64xx_get_slave_ctrldata()
815 return ERR_PTR(-ENOMEM); in s3c64xx_get_slave_ctrldata()
818 of_property_read_u32(data_np, "samsung,spi-feedback-delay", &fb_delay); in s3c64xx_get_slave_ctrldata()
819 cs->fb_delay = fb_delay; in s3c64xx_get_slave_ctrldata()
826 * and save the configuration in a local data-structure.
830 static int s3c64xx_spi_setup(struct spi_device *spi) in s3c64xx_spi_setup() argument
832 struct s3c64xx_spi_csinfo *cs = spi->controller_data; in s3c64xx_spi_setup()
836 sdd = spi_master_get_devdata(spi->master); in s3c64xx_spi_setup()
837 if (spi->dev.of_node) { in s3c64xx_spi_setup()
838 cs = s3c64xx_get_slave_ctrldata(spi); in s3c64xx_spi_setup()
839 spi->controller_data = cs; in s3c64xx_spi_setup()
841 /* On non-DT platforms the SPI core will set spi->cs_gpio in s3c64xx_spi_setup()
842 * to -ENOENT. The GPIO pin used to drive the chip select in s3c64xx_spi_setup()
843 * is defined by using platform data so spi->cs_gpio value in s3c64xx_spi_setup()
846 spi->cs_gpio = cs->line; in s3c64xx_spi_setup()
850 dev_err(&spi->dev, "No CS for SPI(%d)\n", spi->chip_select); in s3c64xx_spi_setup()
851 return -ENODEV; in s3c64xx_spi_setup()
854 if (!spi_get_ctldata(spi)) { in s3c64xx_spi_setup()
855 if (gpio_is_valid(spi->cs_gpio)) { in s3c64xx_spi_setup()
856 err = gpio_request_one(spi->cs_gpio, GPIOF_OUT_INIT_HIGH, in s3c64xx_spi_setup()
857 dev_name(&spi->dev)); in s3c64xx_spi_setup()
859 dev_err(&spi->dev, in s3c64xx_spi_setup()
861 spi->cs_gpio, err); in s3c64xx_spi_setup()
866 spi_set_ctldata(spi, cs); in s3c64xx_spi_setup()
869 pm_runtime_get_sync(&sdd->pdev->dev); in s3c64xx_spi_setup()
872 if (!sdd->port_conf->clk_from_cmu) { in s3c64xx_spi_setup()
876 speed = clk_get_rate(sdd->src_clk) / 2 / (0 + 1); in s3c64xx_spi_setup()
878 if (spi->max_speed_hz > speed) in s3c64xx_spi_setup()
879 spi->max_speed_hz = speed; in s3c64xx_spi_setup()
881 psr = clk_get_rate(sdd->src_clk) / 2 / spi->max_speed_hz - 1; in s3c64xx_spi_setup()
884 psr--; in s3c64xx_spi_setup()
886 speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1); in s3c64xx_spi_setup()
887 if (spi->max_speed_hz < speed) { in s3c64xx_spi_setup()
891 err = -EINVAL; in s3c64xx_spi_setup()
896 speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1); in s3c64xx_spi_setup()
897 if (spi->max_speed_hz >= speed) { in s3c64xx_spi_setup()
898 spi->max_speed_hz = speed; in s3c64xx_spi_setup()
900 dev_err(&spi->dev, "Can't set %dHz transfer speed\n", in s3c64xx_spi_setup()
901 spi->max_speed_hz); in s3c64xx_spi_setup()
902 err = -EINVAL; in s3c64xx_spi_setup()
907 pm_runtime_mark_last_busy(&sdd->pdev->dev); in s3c64xx_spi_setup()
908 pm_runtime_put_autosuspend(&sdd->pdev->dev); in s3c64xx_spi_setup()
909 s3c64xx_spi_set_cs(spi, false); in s3c64xx_spi_setup()
914 pm_runtime_mark_last_busy(&sdd->pdev->dev); in s3c64xx_spi_setup()
915 pm_runtime_put_autosuspend(&sdd->pdev->dev); in s3c64xx_spi_setup()
916 /* setup() returns with device de-selected */ in s3c64xx_spi_setup()
917 s3c64xx_spi_set_cs(spi, false); in s3c64xx_spi_setup()
919 if (gpio_is_valid(spi->cs_gpio)) in s3c64xx_spi_setup()
920 gpio_free(spi->cs_gpio); in s3c64xx_spi_setup()
921 spi_set_ctldata(spi, NULL); in s3c64xx_spi_setup()
924 if (spi->dev.of_node) in s3c64xx_spi_setup()
930 static void s3c64xx_spi_cleanup(struct spi_device *spi) in s3c64xx_spi_cleanup() argument
932 struct s3c64xx_spi_csinfo *cs = spi_get_ctldata(spi); in s3c64xx_spi_cleanup()
934 if (gpio_is_valid(spi->cs_gpio)) { in s3c64xx_spi_cleanup()
935 gpio_free(spi->cs_gpio); in s3c64xx_spi_cleanup()
936 if (spi->dev.of_node) in s3c64xx_spi_cleanup()
939 /* On non-DT platforms, the SPI core sets in s3c64xx_spi_cleanup()
940 * spi->cs_gpio to -ENOENT and .setup() in s3c64xx_spi_cleanup()
944 spi->cs_gpio = -ENOENT; in s3c64xx_spi_cleanup()
948 spi_set_ctldata(spi, NULL); in s3c64xx_spi_cleanup()
954 struct spi_master *spi = sdd->master; in s3c64xx_spi_irq() local
957 val = readl(sdd->regs + S3C64XX_SPI_STATUS); in s3c64xx_spi_irq()
961 dev_err(&spi->dev, "RX overrun\n"); in s3c64xx_spi_irq()
965 dev_err(&spi->dev, "RX underrun\n"); in s3c64xx_spi_irq()
969 dev_err(&spi->dev, "TX overrun\n"); in s3c64xx_spi_irq()
973 dev_err(&spi->dev, "TX underrun\n"); in s3c64xx_spi_irq()
977 writel(clr, sdd->regs + S3C64XX_SPI_PENDING_CLR); in s3c64xx_spi_irq()
978 writel(0, sdd->regs + S3C64XX_SPI_PENDING_CLR); in s3c64xx_spi_irq()
985 struct s3c64xx_spi_info *sci = sdd->cntrlr_info; in s3c64xx_spi_hwinit()
986 void __iomem *regs = sdd->regs; in s3c64xx_spi_hwinit()
989 sdd->cur_speed = 0; in s3c64xx_spi_hwinit()
991 if (sci->no_cs) in s3c64xx_spi_hwinit()
992 writel(0, sdd->regs + S3C64XX_SPI_CS_REG); in s3c64xx_spi_hwinit()
993 else if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO)) in s3c64xx_spi_hwinit()
994 writel(S3C64XX_SPI_CS_SIG_INACT, sdd->regs + S3C64XX_SPI_CS_REG); in s3c64xx_spi_hwinit()
996 /* Disable Interrupts - we use Polling if not DMA mode */ in s3c64xx_spi_hwinit()
999 if (!sdd->port_conf->clk_from_cmu) in s3c64xx_spi_hwinit()
1000 writel(sci->src_clk_nr << S3C64XX_SPI_CLKSEL_SRCSHFT, in s3c64xx_spi_hwinit()
1032 return ERR_PTR(-ENOMEM); in s3c64xx_spi_parse_dt()
1034 if (of_property_read_u32(dev->of_node, "samsung,spi-src-clk", &temp)) { in s3c64xx_spi_parse_dt()
1035 dev_warn(dev, "spi bus clock parent not specified, using clock at index 0 as parent\n"); in s3c64xx_spi_parse_dt()
1036 sci->src_clk_nr = 0; in s3c64xx_spi_parse_dt()
1038 sci->src_clk_nr = temp; in s3c64xx_spi_parse_dt()
1041 if (of_property_read_u32(dev->of_node, "num-cs", &temp)) { in s3c64xx_spi_parse_dt()
1043 sci->num_cs = 1; in s3c64xx_spi_parse_dt()
1045 sci->num_cs = temp; in s3c64xx_spi_parse_dt()
1048 sci->no_cs = of_property_read_bool(dev->of_node, "no-cs-readback"); in s3c64xx_spi_parse_dt()
1065 if (pdev->dev.of_node) { in s3c64xx_spi_get_port_config()
1067 match = of_match_node(s3c64xx_spi_dt_match, pdev->dev.of_node); in s3c64xx_spi_get_port_config()
1068 return (struct s3c64xx_spi_port_config *)match->data; in s3c64xx_spi_get_port_config()
1072 platform_get_device_id(pdev)->driver_data; in s3c64xx_spi_get_port_config()
1079 struct s3c64xx_spi_info *sci = dev_get_platdata(&pdev->dev); in s3c64xx_spi_probe()
1084 if (!sci && pdev->dev.of_node) { in s3c64xx_spi_probe()
1085 sci = s3c64xx_spi_parse_dt(&pdev->dev); in s3c64xx_spi_probe()
1091 dev_err(&pdev->dev, "platform_data missing!\n"); in s3c64xx_spi_probe()
1092 return -ENODEV; in s3c64xx_spi_probe()
1097 dev_err(&pdev->dev, "Unable to get SPI MEM resource\n"); in s3c64xx_spi_probe()
1098 return -ENXIO; in s3c64xx_spi_probe()
1103 dev_warn(&pdev->dev, "Failed to get IRQ: %d\n", irq); in s3c64xx_spi_probe()
1107 master = spi_alloc_master(&pdev->dev, in s3c64xx_spi_probe()
1110 dev_err(&pdev->dev, "Unable to allocate SPI Master\n"); in s3c64xx_spi_probe()
1111 return -ENOMEM; in s3c64xx_spi_probe()
1117 sdd->port_conf = s3c64xx_spi_get_port_config(pdev); in s3c64xx_spi_probe()
1118 sdd->master = master; in s3c64xx_spi_probe()
1119 sdd->cntrlr_info = sci; in s3c64xx_spi_probe()
1120 sdd->pdev = pdev; in s3c64xx_spi_probe()
1121 sdd->sfr_start = mem_res->start; in s3c64xx_spi_probe()
1122 if (pdev->dev.of_node) { in s3c64xx_spi_probe()
1123 ret = of_alias_get_id(pdev->dev.of_node, "spi"); in s3c64xx_spi_probe()
1125 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", in s3c64xx_spi_probe()
1129 sdd->port_id = ret; in s3c64xx_spi_probe()
1131 sdd->port_id = pdev->id; in s3c64xx_spi_probe()
1134 sdd->cur_bpw = 8; in s3c64xx_spi_probe()
1136 sdd->tx_dma.direction = DMA_MEM_TO_DEV; in s3c64xx_spi_probe()
1137 sdd->rx_dma.direction = DMA_DEV_TO_MEM; in s3c64xx_spi_probe()
1139 master->dev.of_node = pdev->dev.of_node; in s3c64xx_spi_probe()
1140 master->bus_num = sdd->port_id; in s3c64xx_spi_probe()
1141 master->setup = s3c64xx_spi_setup; in s3c64xx_spi_probe()
1142 master->cleanup = s3c64xx_spi_cleanup; in s3c64xx_spi_probe()
1143 master->prepare_transfer_hardware = s3c64xx_spi_prepare_transfer; in s3c64xx_spi_probe()
1144 master->prepare_message = s3c64xx_spi_prepare_message; in s3c64xx_spi_probe()
1145 master->transfer_one = s3c64xx_spi_transfer_one; in s3c64xx_spi_probe()
1146 master->max_transfer_size = s3c64xx_spi_max_transfer_size; in s3c64xx_spi_probe()
1147 master->num_chipselect = sci->num_cs; in s3c64xx_spi_probe()
1148 master->dma_alignment = 8; in s3c64xx_spi_probe()
1149 master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) | in s3c64xx_spi_probe()
1151 /* the spi->mode bits understood by this driver: */ in s3c64xx_spi_probe()
1152 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; in s3c64xx_spi_probe()
1153 master->auto_runtime_pm = true; in s3c64xx_spi_probe()
1155 master->can_dma = s3c64xx_spi_can_dma; in s3c64xx_spi_probe()
1157 sdd->regs = devm_ioremap_resource(&pdev->dev, mem_res); in s3c64xx_spi_probe()
1158 if (IS_ERR(sdd->regs)) { in s3c64xx_spi_probe()
1159 ret = PTR_ERR(sdd->regs); in s3c64xx_spi_probe()
1163 if (sci->cfg_gpio && sci->cfg_gpio()) { in s3c64xx_spi_probe()
1164 dev_err(&pdev->dev, "Unable to config gpio\n"); in s3c64xx_spi_probe()
1165 ret = -EBUSY; in s3c64xx_spi_probe()
1170 sdd->clk = devm_clk_get(&pdev->dev, "spi"); in s3c64xx_spi_probe()
1171 if (IS_ERR(sdd->clk)) { in s3c64xx_spi_probe()
1172 dev_err(&pdev->dev, "Unable to acquire clock 'spi'\n"); in s3c64xx_spi_probe()
1173 ret = PTR_ERR(sdd->clk); in s3c64xx_spi_probe()
1177 ret = clk_prepare_enable(sdd->clk); in s3c64xx_spi_probe()
1179 dev_err(&pdev->dev, "Couldn't enable clock 'spi'\n"); in s3c64xx_spi_probe()
1183 sprintf(clk_name, "spi_busclk%d", sci->src_clk_nr); in s3c64xx_spi_probe()
1184 sdd->src_clk = devm_clk_get(&pdev->dev, clk_name); in s3c64xx_spi_probe()
1185 if (IS_ERR(sdd->src_clk)) { in s3c64xx_spi_probe()
1186 dev_err(&pdev->dev, in s3c64xx_spi_probe()
1188 ret = PTR_ERR(sdd->src_clk); in s3c64xx_spi_probe()
1192 ret = clk_prepare_enable(sdd->src_clk); in s3c64xx_spi_probe()
1194 dev_err(&pdev->dev, "Couldn't enable clock '%s'\n", clk_name); in s3c64xx_spi_probe()
1198 if (sdd->port_conf->clk_ioclk) { in s3c64xx_spi_probe()
1199 sdd->ioclk = devm_clk_get(&pdev->dev, "spi_ioclk"); in s3c64xx_spi_probe()
1200 if (IS_ERR(sdd->ioclk)) { in s3c64xx_spi_probe()
1201 dev_err(&pdev->dev, "Unable to acquire 'ioclk'\n"); in s3c64xx_spi_probe()
1202 ret = PTR_ERR(sdd->ioclk); in s3c64xx_spi_probe()
1206 ret = clk_prepare_enable(sdd->ioclk); in s3c64xx_spi_probe()
1208 dev_err(&pdev->dev, "Couldn't enable clock 'ioclk'\n"); in s3c64xx_spi_probe()
1215 sdd->rx_dma.ch = dma_request_chan(&pdev->dev, "rx"); in s3c64xx_spi_probe()
1216 if (IS_ERR(sdd->rx_dma.ch)) { in s3c64xx_spi_probe()
1217 dev_err(&pdev->dev, "Failed to get RX DMA channel\n"); in s3c64xx_spi_probe()
1218 ret = PTR_ERR(sdd->rx_dma.ch); in s3c64xx_spi_probe()
1221 sdd->tx_dma.ch = dma_request_chan(&pdev->dev, "tx"); in s3c64xx_spi_probe()
1222 if (IS_ERR(sdd->tx_dma.ch)) { in s3c64xx_spi_probe()
1223 dev_err(&pdev->dev, "Failed to get TX DMA channel\n"); in s3c64xx_spi_probe()
1224 ret = PTR_ERR(sdd->tx_dma.ch); in s3c64xx_spi_probe()
1229 pm_runtime_set_autosuspend_delay(&pdev->dev, AUTOSUSPEND_TIMEOUT); in s3c64xx_spi_probe()
1230 pm_runtime_use_autosuspend(&pdev->dev); in s3c64xx_spi_probe()
1231 pm_runtime_set_active(&pdev->dev); in s3c64xx_spi_probe()
1232 pm_runtime_enable(&pdev->dev); in s3c64xx_spi_probe()
1233 pm_runtime_get_sync(&pdev->dev); in s3c64xx_spi_probe()
1238 spin_lock_init(&sdd->lock); in s3c64xx_spi_probe()
1239 init_completion(&sdd->xfer_completion); in s3c64xx_spi_probe()
1241 ret = devm_request_irq(&pdev->dev, irq, s3c64xx_spi_irq, 0, in s3c64xx_spi_probe()
1242 "spi-s3c64xx", sdd); in s3c64xx_spi_probe()
1244 dev_err(&pdev->dev, "Failed to request IRQ %d: %d\n", in s3c64xx_spi_probe()
1251 sdd->regs + S3C64XX_SPI_INT_EN); in s3c64xx_spi_probe()
1253 ret = devm_spi_register_master(&pdev->dev, master); in s3c64xx_spi_probe()
1255 dev_err(&pdev->dev, "cannot register SPI master: %d\n", ret); in s3c64xx_spi_probe()
1259 dev_dbg(&pdev->dev, "Samsung SoC SPI Driver loaded for Bus SPI-%d with %d Slaves attached\n", in s3c64xx_spi_probe()
1260 sdd->port_id, master->num_chipselect); in s3c64xx_spi_probe()
1261 dev_dbg(&pdev->dev, "\tIOmem=[%pR]\tFIFO %dbytes\n", in s3c64xx_spi_probe()
1264 pm_runtime_mark_last_busy(&pdev->dev); in s3c64xx_spi_probe()
1265 pm_runtime_put_autosuspend(&pdev->dev); in s3c64xx_spi_probe()
1270 pm_runtime_put_noidle(&pdev->dev); in s3c64xx_spi_probe()
1271 pm_runtime_disable(&pdev->dev); in s3c64xx_spi_probe()
1272 pm_runtime_set_suspended(&pdev->dev); in s3c64xx_spi_probe()
1275 dma_release_channel(sdd->tx_dma.ch); in s3c64xx_spi_probe()
1278 dma_release_channel(sdd->rx_dma.ch); in s3c64xx_spi_probe()
1280 clk_disable_unprepare(sdd->ioclk); in s3c64xx_spi_probe()
1282 clk_disable_unprepare(sdd->src_clk); in s3c64xx_spi_probe()
1284 clk_disable_unprepare(sdd->clk); in s3c64xx_spi_probe()
1296 pm_runtime_get_sync(&pdev->dev); in s3c64xx_spi_remove()
1298 writel(0, sdd->regs + S3C64XX_SPI_INT_EN); in s3c64xx_spi_remove()
1301 dma_release_channel(sdd->rx_dma.ch); in s3c64xx_spi_remove()
1302 dma_release_channel(sdd->tx_dma.ch); in s3c64xx_spi_remove()
1305 clk_disable_unprepare(sdd->ioclk); in s3c64xx_spi_remove()
1307 clk_disable_unprepare(sdd->src_clk); in s3c64xx_spi_remove()
1309 clk_disable_unprepare(sdd->clk); in s3c64xx_spi_remove()
1311 pm_runtime_put_noidle(&pdev->dev); in s3c64xx_spi_remove()
1312 pm_runtime_disable(&pdev->dev); in s3c64xx_spi_remove()
1313 pm_runtime_set_suspended(&pdev->dev); in s3c64xx_spi_remove()
1332 sdd->cur_speed = 0; /* Output Clock is stopped */ in s3c64xx_spi_suspend()
1341 struct s3c64xx_spi_info *sci = sdd->cntrlr_info; in s3c64xx_spi_resume()
1344 if (sci->cfg_gpio) in s3c64xx_spi_resume()
1345 sci->cfg_gpio(); in s3c64xx_spi_resume()
1361 clk_disable_unprepare(sdd->clk); in s3c64xx_spi_runtime_suspend()
1362 clk_disable_unprepare(sdd->src_clk); in s3c64xx_spi_runtime_suspend()
1363 clk_disable_unprepare(sdd->ioclk); in s3c64xx_spi_runtime_suspend()
1374 if (sdd->port_conf->clk_ioclk) { in s3c64xx_spi_runtime_resume()
1375 ret = clk_prepare_enable(sdd->ioclk); in s3c64xx_spi_runtime_resume()
1380 ret = clk_prepare_enable(sdd->src_clk); in s3c64xx_spi_runtime_resume()
1384 ret = clk_prepare_enable(sdd->clk); in s3c64xx_spi_runtime_resume()
1392 sdd->regs + S3C64XX_SPI_INT_EN); in s3c64xx_spi_runtime_resume()
1397 clk_disable_unprepare(sdd->src_clk); in s3c64xx_spi_runtime_resume()
1399 clk_disable_unprepare(sdd->ioclk); in s3c64xx_spi_runtime_resume()
1461 .name = "s3c2443-spi",
1464 .name = "s3c6410-spi",
1471 { .compatible = "samsung,s3c2443-spi",
1474 { .compatible = "samsung,s3c6410-spi",
1477 { .compatible = "samsung,s5pv210-spi",
1480 { .compatible = "samsung,exynos4210-spi",
1483 { .compatible = "samsung,exynos7-spi",
1486 { .compatible = "samsung,exynos5433-spi",
1495 .name = "s3c64xx-spi",
1503 MODULE_ALIAS("platform:s3c64xx-spi");
1508 MODULE_DESCRIPTION("S3C64XX SPI Controller Driver");