Lines Matching +full:spi +full:- +full:base
1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * SPI bus driver for CSR SiRFprimaII
20 #include <linux/spi/spi.h>
21 #include <linux/spi/spi_bitbang.h>
23 #include <linux/dma-direction.h>
24 #include <linux/dma-mapping.h>
28 /* SPI CTRL register defines */
136 #define SIRFSOC_SPI_FIFO_FULL_MASK(s) (1 << ((s)->fifo_full_offset))
137 #define SIRFSOC_SPI_FIFO_EMPTY_MASK(s) (1 << ((s)->fifo_full_offset + 1))
138 #define SIRFSOC_SPI_FIFO_THD_MASK(s) ((s)->fifo_size - 1)
141 ((val) & (s)->fifo_level_chk_mask)
150 * only if the rx/tx buffer and transfer size are 4-bytes aligned, we use dma
155 #define IS_DMA_VALID(x) (x && ALIGNED(x->tx_buf) && ALIGNED(x->rx_buf) && \
156 ALIGNED(x->len) && (x->len < 2 * PAGE_SIZE))
162 /*SPI and USP-SPI common*/
180 /*SPI self*/
184 /*USP-SPI self*/
255 void __iomem *base; member
256 u32 ctrl_freq; /* SPI controller clock speed */
290 /* fifo_level_chk_mask is (fifo_size/4 - 1) */
306 writel(readl(sspi->base + sspi->regs->usp_mode1) & in sirfsoc_usp_hwinit()
307 ~SIRFSOC_USP_EN, sspi->base + sspi->regs->usp_mode1); in sirfsoc_usp_hwinit()
308 writel(readl(sspi->base + sspi->regs->usp_mode1) | in sirfsoc_usp_hwinit()
309 SIRFSOC_USP_EN, sspi->base + sspi->regs->usp_mode1); in sirfsoc_usp_hwinit()
315 u8 *rx = sspi->rx; in spi_sirfsoc_rx_word_u8()
317 data = readl(sspi->base + sspi->regs->rxfifo_data); in spi_sirfsoc_rx_word_u8()
321 sspi->rx = rx; in spi_sirfsoc_rx_word_u8()
324 sspi->left_rx_word--; in spi_sirfsoc_rx_word_u8()
330 const u8 *tx = sspi->tx; in spi_sirfsoc_tx_word_u8()
334 sspi->tx = tx; in spi_sirfsoc_tx_word_u8()
336 writel(data, sspi->base + sspi->regs->txfifo_data); in spi_sirfsoc_tx_word_u8()
337 sspi->left_tx_word--; in spi_sirfsoc_tx_word_u8()
343 u16 *rx = sspi->rx; in spi_sirfsoc_rx_word_u16()
345 data = readl(sspi->base + sspi->regs->rxfifo_data); in spi_sirfsoc_rx_word_u16()
349 sspi->rx = rx; in spi_sirfsoc_rx_word_u16()
352 sspi->left_rx_word--; in spi_sirfsoc_rx_word_u16()
358 const u16 *tx = sspi->tx; in spi_sirfsoc_tx_word_u16()
362 sspi->tx = tx; in spi_sirfsoc_tx_word_u16()
365 writel(data, sspi->base + sspi->regs->txfifo_data); in spi_sirfsoc_tx_word_u16()
366 sspi->left_tx_word--; in spi_sirfsoc_tx_word_u16()
372 u32 *rx = sspi->rx; in spi_sirfsoc_rx_word_u32()
374 data = readl(sspi->base + sspi->regs->rxfifo_data); in spi_sirfsoc_rx_word_u32()
378 sspi->rx = rx; in spi_sirfsoc_rx_word_u32()
381 sspi->left_rx_word--; in spi_sirfsoc_rx_word_u32()
388 const u32 *tx = sspi->tx; in spi_sirfsoc_tx_word_u32()
392 sspi->tx = tx; in spi_sirfsoc_tx_word_u32()
395 writel(data, sspi->base + sspi->regs->txfifo_data); in spi_sirfsoc_tx_word_u32()
396 sspi->left_tx_word--; in spi_sirfsoc_tx_word_u32()
404 spi_stat = readl(sspi->base + sspi->regs->int_st); in spi_sirfsoc_irq()
405 if (sspi->tx_by_cmd && sspi->type == SIRF_REAL_SPI in spi_sirfsoc_irq()
407 complete(&sspi->tx_done); in spi_sirfsoc_irq()
408 writel(0x0, sspi->base + sspi->regs->int_en); in spi_sirfsoc_irq()
409 writel(readl(sspi->base + sspi->regs->int_st), in spi_sirfsoc_irq()
410 sspi->base + sspi->regs->int_st); in spi_sirfsoc_irq()
416 complete(&sspi->tx_done); in spi_sirfsoc_irq()
417 complete(&sspi->rx_done); in spi_sirfsoc_irq()
418 switch (sspi->type) { in spi_sirfsoc_irq()
421 writel(0x0, sspi->base + sspi->regs->int_en); in spi_sirfsoc_irq()
424 writel(~0UL, sspi->base + sspi->regs->usp_int_en_clr); in spi_sirfsoc_irq()
427 writel(readl(sspi->base + sspi->regs->int_st), in spi_sirfsoc_irq()
428 sspi->base + sspi->regs->int_st); in spi_sirfsoc_irq()
432 complete(&sspi->tx_done); in spi_sirfsoc_irq()
433 while (!(readl(sspi->base + sspi->regs->int_st) & in spi_sirfsoc_irq()
436 complete(&sspi->rx_done); in spi_sirfsoc_irq()
437 switch (sspi->type) { in spi_sirfsoc_irq()
440 writel(0x0, sspi->base + sspi->regs->int_en); in spi_sirfsoc_irq()
443 writel(~0UL, sspi->base + sspi->regs->usp_int_en_clr); in spi_sirfsoc_irq()
446 writel(readl(sspi->base + sspi->regs->int_st), in spi_sirfsoc_irq()
447 sspi->base + sspi->regs->int_st); in spi_sirfsoc_irq()
459 static void spi_sirfsoc_cmd_transfer(struct spi_device *spi, in spi_sirfsoc_cmd_transfer() argument
463 int timeout = t->len * 10; in spi_sirfsoc_cmd_transfer()
466 sspi = spi_master_get_devdata(spi->master); in spi_sirfsoc_cmd_transfer()
467 writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + sspi->regs->txfifo_op); in spi_sirfsoc_cmd_transfer()
468 writel(SIRFSOC_SPI_FIFO_START, sspi->base + sspi->regs->txfifo_op); in spi_sirfsoc_cmd_transfer()
469 memcpy(&cmd, sspi->tx, t->len); in spi_sirfsoc_cmd_transfer()
470 if (sspi->word_width == 1 && !(spi->mode & SPI_LSB_FIRST)) in spi_sirfsoc_cmd_transfer()
472 ((SIRFSOC_MAX_CMD_BYTES - t->len) * 8); in spi_sirfsoc_cmd_transfer()
473 if (sspi->word_width == 2 && t->len == 4 && in spi_sirfsoc_cmd_transfer()
474 (!(spi->mode & SPI_LSB_FIRST))) in spi_sirfsoc_cmd_transfer()
476 writel(cmd, sspi->base + sspi->regs->spi_cmd); in spi_sirfsoc_cmd_transfer()
478 sspi->base + sspi->regs->int_en); in spi_sirfsoc_cmd_transfer()
480 sspi->base + sspi->regs->tx_rx_en); in spi_sirfsoc_cmd_transfer()
481 if (wait_for_completion_timeout(&sspi->tx_done, timeout) == 0) { in spi_sirfsoc_cmd_transfer()
482 dev_err(&spi->dev, "cmd transfer timeout\n"); in spi_sirfsoc_cmd_transfer()
485 sspi->left_rx_word -= t->len; in spi_sirfsoc_cmd_transfer()
488 static void spi_sirfsoc_dma_transfer(struct spi_device *spi, in spi_sirfsoc_dma_transfer() argument
493 int timeout = t->len * 10; in spi_sirfsoc_dma_transfer()
495 sspi = spi_master_get_devdata(spi->master); in spi_sirfsoc_dma_transfer()
496 writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + sspi->regs->rxfifo_op); in spi_sirfsoc_dma_transfer()
497 writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + sspi->regs->txfifo_op); in spi_sirfsoc_dma_transfer()
498 switch (sspi->type) { in spi_sirfsoc_dma_transfer()
501 sspi->base + sspi->regs->rxfifo_op); in spi_sirfsoc_dma_transfer()
503 sspi->base + sspi->regs->txfifo_op); in spi_sirfsoc_dma_transfer()
504 writel(0, sspi->base + sspi->regs->int_en); in spi_sirfsoc_dma_transfer()
507 writel(0x0, sspi->base + sspi->regs->rxfifo_op); in spi_sirfsoc_dma_transfer()
508 writel(0x0, sspi->base + sspi->regs->txfifo_op); in spi_sirfsoc_dma_transfer()
509 writel(0, sspi->base + sspi->regs->int_en); in spi_sirfsoc_dma_transfer()
512 writel(0x0, sspi->base + sspi->regs->rxfifo_op); in spi_sirfsoc_dma_transfer()
513 writel(0x0, sspi->base + sspi->regs->txfifo_op); in spi_sirfsoc_dma_transfer()
514 writel(~0UL, sspi->base + sspi->regs->usp_int_en_clr); in spi_sirfsoc_dma_transfer()
517 writel(readl(sspi->base + sspi->regs->int_st), in spi_sirfsoc_dma_transfer()
518 sspi->base + sspi->regs->int_st); in spi_sirfsoc_dma_transfer()
519 if (sspi->left_tx_word < sspi->dat_max_frm_len) { in spi_sirfsoc_dma_transfer()
520 switch (sspi->type) { in spi_sirfsoc_dma_transfer()
522 writel(readl(sspi->base + sspi->regs->spi_ctrl) | in spi_sirfsoc_dma_transfer()
525 sspi->base + sspi->regs->spi_ctrl); in spi_sirfsoc_dma_transfer()
526 writel(sspi->left_tx_word - 1, in spi_sirfsoc_dma_transfer()
527 sspi->base + sspi->regs->tx_dma_io_len); in spi_sirfsoc_dma_transfer()
528 writel(sspi->left_tx_word - 1, in spi_sirfsoc_dma_transfer()
529 sspi->base + sspi->regs->rx_dma_io_len); in spi_sirfsoc_dma_transfer()
533 /*USP simulate SPI, tx/rx_dma_io_len indicates bytes*/ in spi_sirfsoc_dma_transfer()
534 writel(sspi->left_tx_word * sspi->word_width, in spi_sirfsoc_dma_transfer()
535 sspi->base + sspi->regs->tx_dma_io_len); in spi_sirfsoc_dma_transfer()
536 writel(sspi->left_tx_word * sspi->word_width, in spi_sirfsoc_dma_transfer()
537 sspi->base + sspi->regs->rx_dma_io_len); in spi_sirfsoc_dma_transfer()
541 if (sspi->type == SIRF_REAL_SPI) in spi_sirfsoc_dma_transfer()
542 writel(readl(sspi->base + sspi->regs->spi_ctrl), in spi_sirfsoc_dma_transfer()
543 sspi->base + sspi->regs->spi_ctrl); in spi_sirfsoc_dma_transfer()
544 writel(0, sspi->base + sspi->regs->tx_dma_io_len); in spi_sirfsoc_dma_transfer()
545 writel(0, sspi->base + sspi->regs->rx_dma_io_len); in spi_sirfsoc_dma_transfer()
547 sspi->dst_start = dma_map_single(&spi->dev, sspi->rx, t->len, in spi_sirfsoc_dma_transfer()
548 (t->tx_buf != t->rx_buf) ? in spi_sirfsoc_dma_transfer()
550 rx_desc = dmaengine_prep_slave_single(sspi->rx_chan, in spi_sirfsoc_dma_transfer()
551 sspi->dst_start, t->len, DMA_DEV_TO_MEM, in spi_sirfsoc_dma_transfer()
553 rx_desc->callback = spi_sirfsoc_dma_fini_callback; in spi_sirfsoc_dma_transfer()
554 rx_desc->callback_param = &sspi->rx_done; in spi_sirfsoc_dma_transfer()
556 sspi->src_start = dma_map_single(&spi->dev, (void *)sspi->tx, t->len, in spi_sirfsoc_dma_transfer()
557 (t->tx_buf != t->rx_buf) ? in spi_sirfsoc_dma_transfer()
559 tx_desc = dmaengine_prep_slave_single(sspi->tx_chan, in spi_sirfsoc_dma_transfer()
560 sspi->src_start, t->len, DMA_MEM_TO_DEV, in spi_sirfsoc_dma_transfer()
562 tx_desc->callback = spi_sirfsoc_dma_fini_callback; in spi_sirfsoc_dma_transfer()
563 tx_desc->callback_param = &sspi->tx_done; in spi_sirfsoc_dma_transfer()
567 dma_async_issue_pending(sspi->tx_chan); in spi_sirfsoc_dma_transfer()
568 dma_async_issue_pending(sspi->rx_chan); in spi_sirfsoc_dma_transfer()
570 sspi->base + sspi->regs->tx_rx_en); in spi_sirfsoc_dma_transfer()
571 if (sspi->type == SIRF_USP_SPI_P2 || in spi_sirfsoc_dma_transfer()
572 sspi->type == SIRF_USP_SPI_A7) { in spi_sirfsoc_dma_transfer()
574 sspi->base + sspi->regs->rxfifo_op); in spi_sirfsoc_dma_transfer()
576 sspi->base + sspi->regs->txfifo_op); in spi_sirfsoc_dma_transfer()
578 if (wait_for_completion_timeout(&sspi->rx_done, timeout) == 0) { in spi_sirfsoc_dma_transfer()
579 dev_err(&spi->dev, "transfer timeout\n"); in spi_sirfsoc_dma_transfer()
580 dmaengine_terminate_all(sspi->rx_chan); in spi_sirfsoc_dma_transfer()
582 sspi->left_rx_word = 0; in spi_sirfsoc_dma_transfer()
584 * we only wait tx-done event if transferring by DMA. for PIO, in spi_sirfsoc_dma_transfer()
588 if (wait_for_completion_timeout(&sspi->tx_done, timeout) == 0) { in spi_sirfsoc_dma_transfer()
589 dev_err(&spi->dev, "transfer timeout\n"); in spi_sirfsoc_dma_transfer()
590 if (sspi->type == SIRF_USP_SPI_P2 || in spi_sirfsoc_dma_transfer()
591 sspi->type == SIRF_USP_SPI_A7) in spi_sirfsoc_dma_transfer()
592 writel(0, sspi->base + sspi->regs->tx_rx_en); in spi_sirfsoc_dma_transfer()
593 dmaengine_terminate_all(sspi->tx_chan); in spi_sirfsoc_dma_transfer()
595 dma_unmap_single(&spi->dev, sspi->src_start, t->len, DMA_TO_DEVICE); in spi_sirfsoc_dma_transfer()
596 dma_unmap_single(&spi->dev, sspi->dst_start, t->len, DMA_FROM_DEVICE); in spi_sirfsoc_dma_transfer()
598 writel(0, sspi->base + sspi->regs->rxfifo_op); in spi_sirfsoc_dma_transfer()
599 writel(0, sspi->base + sspi->regs->txfifo_op); in spi_sirfsoc_dma_transfer()
600 if (sspi->left_tx_word >= sspi->dat_max_frm_len) in spi_sirfsoc_dma_transfer()
601 writel(0, sspi->base + sspi->regs->tx_rx_en); in spi_sirfsoc_dma_transfer()
602 if (sspi->type == SIRF_USP_SPI_P2 || in spi_sirfsoc_dma_transfer()
603 sspi->type == SIRF_USP_SPI_A7) in spi_sirfsoc_dma_transfer()
604 writel(0, sspi->base + sspi->regs->tx_rx_en); in spi_sirfsoc_dma_transfer()
607 static void spi_sirfsoc_pio_transfer(struct spi_device *spi, in spi_sirfsoc_pio_transfer() argument
611 int timeout = t->len * 10; in spi_sirfsoc_pio_transfer()
614 sspi = spi_master_get_devdata(spi->master); in spi_sirfsoc_pio_transfer()
617 sspi->base + sspi->regs->rxfifo_op); in spi_sirfsoc_pio_transfer()
619 sspi->base + sspi->regs->txfifo_op); in spi_sirfsoc_pio_transfer()
620 switch (sspi->type) { in spi_sirfsoc_pio_transfer()
622 writel(0x0, sspi->base + sspi->regs->rxfifo_op); in spi_sirfsoc_pio_transfer()
623 writel(0x0, sspi->base + sspi->regs->txfifo_op); in spi_sirfsoc_pio_transfer()
624 writel(0, sspi->base + sspi->regs->int_en); in spi_sirfsoc_pio_transfer()
625 writel(readl(sspi->base + sspi->regs->int_st), in spi_sirfsoc_pio_transfer()
626 sspi->base + sspi->regs->int_st); in spi_sirfsoc_pio_transfer()
627 writel(min((sspi->left_tx_word * sspi->word_width), in spi_sirfsoc_pio_transfer()
628 sspi->fifo_size), in spi_sirfsoc_pio_transfer()
629 sspi->base + sspi->regs->tx_dma_io_len); in spi_sirfsoc_pio_transfer()
630 writel(min((sspi->left_rx_word * sspi->word_width), in spi_sirfsoc_pio_transfer()
631 sspi->fifo_size), in spi_sirfsoc_pio_transfer()
632 sspi->base + sspi->regs->rx_dma_io_len); in spi_sirfsoc_pio_transfer()
635 writel(0x0, sspi->base + sspi->regs->rxfifo_op); in spi_sirfsoc_pio_transfer()
636 writel(0x0, sspi->base + sspi->regs->txfifo_op); in spi_sirfsoc_pio_transfer()
637 writel(~0UL, sspi->base + sspi->regs->usp_int_en_clr); in spi_sirfsoc_pio_transfer()
638 writel(readl(sspi->base + sspi->regs->int_st), in spi_sirfsoc_pio_transfer()
639 sspi->base + sspi->regs->int_st); in spi_sirfsoc_pio_transfer()
640 writel(min((sspi->left_tx_word * sspi->word_width), in spi_sirfsoc_pio_transfer()
641 sspi->fifo_size), in spi_sirfsoc_pio_transfer()
642 sspi->base + sspi->regs->tx_dma_io_len); in spi_sirfsoc_pio_transfer()
643 writel(min((sspi->left_rx_word * sspi->word_width), in spi_sirfsoc_pio_transfer()
644 sspi->fifo_size), in spi_sirfsoc_pio_transfer()
645 sspi->base + sspi->regs->rx_dma_io_len); in spi_sirfsoc_pio_transfer()
649 sspi->base + sspi->regs->rxfifo_op); in spi_sirfsoc_pio_transfer()
651 sspi->base + sspi->regs->txfifo_op); in spi_sirfsoc_pio_transfer()
652 writel(0, sspi->base + sspi->regs->int_en); in spi_sirfsoc_pio_transfer()
653 writel(readl(sspi->base + sspi->regs->int_st), in spi_sirfsoc_pio_transfer()
654 sspi->base + sspi->regs->int_st); in spi_sirfsoc_pio_transfer()
655 writel(readl(sspi->base + sspi->regs->spi_ctrl) | in spi_sirfsoc_pio_transfer()
658 sspi->base + sspi->regs->spi_ctrl); in spi_sirfsoc_pio_transfer()
659 data_units = sspi->fifo_size / sspi->word_width; in spi_sirfsoc_pio_transfer()
660 writel(min(sspi->left_tx_word, data_units) - 1, in spi_sirfsoc_pio_transfer()
661 sspi->base + sspi->regs->tx_dma_io_len); in spi_sirfsoc_pio_transfer()
662 writel(min(sspi->left_rx_word, data_units) - 1, in spi_sirfsoc_pio_transfer()
663 sspi->base + sspi->regs->rx_dma_io_len); in spi_sirfsoc_pio_transfer()
666 while (!((readl(sspi->base + sspi->regs->txfifo_st) in spi_sirfsoc_pio_transfer()
668 sspi->left_tx_word) in spi_sirfsoc_pio_transfer()
669 sspi->tx_word(sspi); in spi_sirfsoc_pio_transfer()
674 sspi->base + sspi->regs->int_en); in spi_sirfsoc_pio_transfer()
676 sspi->base + sspi->regs->tx_rx_en); in spi_sirfsoc_pio_transfer()
677 if (sspi->type == SIRF_USP_SPI_P2 || in spi_sirfsoc_pio_transfer()
678 sspi->type == SIRF_USP_SPI_A7) { in spi_sirfsoc_pio_transfer()
680 sspi->base + sspi->regs->rxfifo_op); in spi_sirfsoc_pio_transfer()
682 sspi->base + sspi->regs->txfifo_op); in spi_sirfsoc_pio_transfer()
684 if (!wait_for_completion_timeout(&sspi->tx_done, timeout) || in spi_sirfsoc_pio_transfer()
685 !wait_for_completion_timeout(&sspi->rx_done, timeout)) { in spi_sirfsoc_pio_transfer()
686 dev_err(&spi->dev, "transfer timeout\n"); in spi_sirfsoc_pio_transfer()
687 if (sspi->type == SIRF_USP_SPI_P2 || in spi_sirfsoc_pio_transfer()
688 sspi->type == SIRF_USP_SPI_A7) in spi_sirfsoc_pio_transfer()
689 writel(0, sspi->base + sspi->regs->tx_rx_en); in spi_sirfsoc_pio_transfer()
692 while (!((readl(sspi->base + sspi->regs->rxfifo_st) in spi_sirfsoc_pio_transfer()
694 sspi->left_rx_word) in spi_sirfsoc_pio_transfer()
695 sspi->rx_word(sspi); in spi_sirfsoc_pio_transfer()
696 if (sspi->type == SIRF_USP_SPI_P2 || in spi_sirfsoc_pio_transfer()
697 sspi->type == SIRF_USP_SPI_A7) in spi_sirfsoc_pio_transfer()
698 writel(0, sspi->base + sspi->regs->tx_rx_en); in spi_sirfsoc_pio_transfer()
699 writel(0, sspi->base + sspi->regs->rxfifo_op); in spi_sirfsoc_pio_transfer()
700 writel(0, sspi->base + sspi->regs->txfifo_op); in spi_sirfsoc_pio_transfer()
701 } while (sspi->left_tx_word != 0 || sspi->left_rx_word != 0); in spi_sirfsoc_pio_transfer()
704 static int spi_sirfsoc_transfer(struct spi_device *spi, struct spi_transfer *t) in spi_sirfsoc_transfer() argument
708 sspi = spi_master_get_devdata(spi->master); in spi_sirfsoc_transfer()
709 sspi->tx = t->tx_buf; in spi_sirfsoc_transfer()
710 sspi->rx = t->rx_buf; in spi_sirfsoc_transfer()
711 sspi->left_tx_word = sspi->left_rx_word = t->len / sspi->word_width; in spi_sirfsoc_transfer()
712 reinit_completion(&sspi->rx_done); in spi_sirfsoc_transfer()
713 reinit_completion(&sspi->tx_done); in spi_sirfsoc_transfer()
719 if (sspi->type == SIRF_REAL_SPI && sspi->tx_by_cmd) in spi_sirfsoc_transfer()
720 spi_sirfsoc_cmd_transfer(spi, t); in spi_sirfsoc_transfer()
722 spi_sirfsoc_dma_transfer(spi, t); in spi_sirfsoc_transfer()
724 spi_sirfsoc_pio_transfer(spi, t); in spi_sirfsoc_transfer()
726 return t->len - sspi->left_rx_word * sspi->word_width; in spi_sirfsoc_transfer()
729 static void spi_sirfsoc_chipselect(struct spi_device *spi, int value) in spi_sirfsoc_chipselect() argument
731 struct sirfsoc_spi *sspi = spi_master_get_devdata(spi->master); in spi_sirfsoc_chipselect()
733 if (sspi->hw_cs) { in spi_sirfsoc_chipselect()
736 switch (sspi->type) { in spi_sirfsoc_chipselect()
738 regval = readl(sspi->base + sspi->regs->spi_ctrl); in spi_sirfsoc_chipselect()
741 if (spi->mode & SPI_CS_HIGH) in spi_sirfsoc_chipselect()
747 if (spi->mode & SPI_CS_HIGH) in spi_sirfsoc_chipselect()
753 writel(regval, sspi->base + sspi->regs->spi_ctrl); in spi_sirfsoc_chipselect()
757 regval = readl(sspi->base + in spi_sirfsoc_chipselect()
758 sspi->regs->usp_pin_io_data); in spi_sirfsoc_chipselect()
761 if (spi->mode & SPI_CS_HIGH) in spi_sirfsoc_chipselect()
767 if (spi->mode & SPI_CS_HIGH) in spi_sirfsoc_chipselect()
774 sspi->base + sspi->regs->usp_pin_io_data); in spi_sirfsoc_chipselect()
780 gpio_direction_output(spi->cs_gpio, in spi_sirfsoc_chipselect()
781 spi->mode & SPI_CS_HIGH ? 1 : 0); in spi_sirfsoc_chipselect()
784 gpio_direction_output(spi->cs_gpio, in spi_sirfsoc_chipselect()
785 spi->mode & SPI_CS_HIGH ? 0 : 1); in spi_sirfsoc_chipselect()
791 static int spi_sirfsoc_config_mode(struct spi_device *spi) in spi_sirfsoc_config_mode() argument
796 sspi = spi_master_get_devdata(spi->master); in spi_sirfsoc_config_mode()
797 regval = readl(sspi->base + sspi->regs->spi_ctrl); in spi_sirfsoc_config_mode()
798 usp_mode1 = readl(sspi->base + sspi->regs->usp_mode1); in spi_sirfsoc_config_mode()
799 if (!(spi->mode & SPI_CS_HIGH)) { in spi_sirfsoc_config_mode()
806 if (!(spi->mode & SPI_LSB_FIRST)) { in spi_sirfsoc_config_mode()
813 if (spi->mode & SPI_CPOL) { in spi_sirfsoc_config_mode()
824 if (((spi->mode & SPI_CPOL) && (spi->mode & SPI_CPHA)) || in spi_sirfsoc_config_mode()
825 (!(spi->mode & SPI_CPOL) && !(spi->mode & SPI_CPHA))) { in spi_sirfsoc_config_mode()
834 writel((SIRFSOC_SPI_FIFO_LEVEL_CHK_MASK(sspi, sspi->fifo_size - 2) << in spi_sirfsoc_config_mode()
836 (SIRFSOC_SPI_FIFO_LEVEL_CHK_MASK(sspi, sspi->fifo_size / 2) << in spi_sirfsoc_config_mode()
840 sspi->base + sspi->regs->txfifo_level_chk); in spi_sirfsoc_config_mode()
843 (SIRFSOC_SPI_FIFO_LEVEL_CHK_MASK(sspi, sspi->fifo_size / 2) << in spi_sirfsoc_config_mode()
845 (SIRFSOC_SPI_FIFO_LEVEL_CHK_MASK(sspi, sspi->fifo_size - 2) << in spi_sirfsoc_config_mode()
847 sspi->base + sspi->regs->rxfifo_level_chk); in spi_sirfsoc_config_mode()
852 switch (sspi->type) { in spi_sirfsoc_config_mode()
855 writel(regval, sspi->base + sspi->regs->spi_ctrl); in spi_sirfsoc_config_mode()
862 writel(usp_mode1, sspi->base + sspi->regs->usp_mode1); in spi_sirfsoc_config_mode()
870 spi_sirfsoc_setup_transfer(struct spi_device *spi, struct spi_transfer *t) in spi_sirfsoc_setup_transfer() argument
877 sspi = spi_master_get_devdata(spi->master); in spi_sirfsoc_setup_transfer()
879 bits_per_word = (t) ? t->bits_per_word : spi->bits_per_word; in spi_sirfsoc_setup_transfer()
880 hz = t && t->speed_hz ? t->speed_hz : spi->max_speed_hz; in spi_sirfsoc_setup_transfer()
882 usp_mode2 = regval = (sspi->ctrl_freq / (2 * hz)) - 1; in spi_sirfsoc_setup_transfer()
884 dev_err(&spi->dev, "Speed %d not supported\n", hz); in spi_sirfsoc_setup_transfer()
885 return -EINVAL; in spi_sirfsoc_setup_transfer()
890 sspi->rx_word = spi_sirfsoc_rx_word_u8; in spi_sirfsoc_setup_transfer()
891 sspi->tx_word = spi_sirfsoc_tx_word_u8; in spi_sirfsoc_setup_transfer()
898 sspi->rx_word = spi_sirfsoc_rx_word_u16; in spi_sirfsoc_setup_transfer()
899 sspi->tx_word = spi_sirfsoc_tx_word_u16; in spi_sirfsoc_setup_transfer()
903 sspi->rx_word = spi_sirfsoc_rx_word_u32; in spi_sirfsoc_setup_transfer()
904 sspi->tx_word = spi_sirfsoc_tx_word_u32; in spi_sirfsoc_setup_transfer()
907 dev_err(&spi->dev, "bpw %d not supported\n", bits_per_word); in spi_sirfsoc_setup_transfer()
908 return -EINVAL; in spi_sirfsoc_setup_transfer()
910 sspi->word_width = DIV_ROUND_UP(bits_per_word, 8); in spi_sirfsoc_setup_transfer()
911 txfifo_ctrl = (((sspi->fifo_size / 2) & in spi_sirfsoc_setup_transfer()
914 (sspi->word_width >> 1); in spi_sirfsoc_setup_transfer()
915 rxfifo_ctrl = (((sspi->fifo_size / 2) & in spi_sirfsoc_setup_transfer()
918 (sspi->word_width >> 1); in spi_sirfsoc_setup_transfer()
919 writel(txfifo_ctrl, sspi->base + sspi->regs->txfifo_ctrl); in spi_sirfsoc_setup_transfer()
920 writel(rxfifo_ctrl, sspi->base + sspi->regs->rxfifo_ctrl); in spi_sirfsoc_setup_transfer()
921 if (sspi->type == SIRF_USP_SPI_P2 || in spi_sirfsoc_setup_transfer()
922 sspi->type == SIRF_USP_SPI_A7) { in spi_sirfsoc_setup_transfer()
924 tx_frm_ctl |= ((bits_per_word - 1) & SIRFSOC_USP_TX_DATA_MASK) in spi_sirfsoc_setup_transfer()
927 - 1) & SIRFSOC_USP_TX_SYNC_MASK) << in spi_sirfsoc_setup_transfer()
930 + 2 - 1) & SIRFSOC_USP_TX_FRAME_MASK) << in spi_sirfsoc_setup_transfer()
932 tx_frm_ctl |= ((bits_per_word - 1) & in spi_sirfsoc_setup_transfer()
936 rx_frm_ctl |= ((bits_per_word - 1) & SIRFSOC_USP_RX_DATA_MASK) in spi_sirfsoc_setup_transfer()
939 + 2 - 1) & SIRFSOC_USP_RX_FRAME_MASK) << in spi_sirfsoc_setup_transfer()
941 rx_frm_ctl |= ((bits_per_word - 1) in spi_sirfsoc_setup_transfer()
947 sspi->base + sspi->regs->usp_tx_frame_ctrl); in spi_sirfsoc_setup_transfer()
951 sspi->base + sspi->regs->usp_rx_frame_ctrl); in spi_sirfsoc_setup_transfer()
952 writel(readl(sspi->base + sspi->regs->usp_mode2) | in spi_sirfsoc_setup_transfer()
959 sspi->base + sspi->regs->usp_mode2); in spi_sirfsoc_setup_transfer()
961 if (sspi->type == SIRF_REAL_SPI) in spi_sirfsoc_setup_transfer()
962 writel(regval, sspi->base + sspi->regs->spi_ctrl); in spi_sirfsoc_setup_transfer()
963 spi_sirfsoc_config_mode(spi); in spi_sirfsoc_setup_transfer()
964 if (sspi->type == SIRF_REAL_SPI) { in spi_sirfsoc_setup_transfer()
965 if (t && t->tx_buf && !t->rx_buf && in spi_sirfsoc_setup_transfer()
966 (t->len <= SIRFSOC_MAX_CMD_BYTES)) { in spi_sirfsoc_setup_transfer()
967 sspi->tx_by_cmd = true; in spi_sirfsoc_setup_transfer()
968 writel(readl(sspi->base + sspi->regs->spi_ctrl) | in spi_sirfsoc_setup_transfer()
969 (SIRFSOC_SPI_CMD_BYTE_NUM((t->len - 1)) | in spi_sirfsoc_setup_transfer()
971 sspi->base + sspi->regs->spi_ctrl); in spi_sirfsoc_setup_transfer()
973 sspi->tx_by_cmd = false; in spi_sirfsoc_setup_transfer()
974 writel(readl(sspi->base + sspi->regs->spi_ctrl) & in spi_sirfsoc_setup_transfer()
976 sspi->base + sspi->regs->spi_ctrl); in spi_sirfsoc_setup_transfer()
981 writel(0, sspi->base + sspi->regs->tx_dma_io_ctrl); in spi_sirfsoc_setup_transfer()
983 sspi->base + sspi->regs->rx_dma_io_ctrl); in spi_sirfsoc_setup_transfer()
987 sspi->base + sspi->regs->tx_dma_io_ctrl); in spi_sirfsoc_setup_transfer()
989 sspi->base + sspi->regs->rx_dma_io_ctrl); in spi_sirfsoc_setup_transfer()
994 static int spi_sirfsoc_setup(struct spi_device *spi) in spi_sirfsoc_setup() argument
999 sspi = spi_master_get_devdata(spi->master); in spi_sirfsoc_setup()
1000 if (spi->cs_gpio == -ENOENT) in spi_sirfsoc_setup()
1001 sspi->hw_cs = true; in spi_sirfsoc_setup()
1003 sspi->hw_cs = false; in spi_sirfsoc_setup()
1004 if (!spi_get_ctldata(spi)) { in spi_sirfsoc_setup()
1007 ret = -ENOMEM; in spi_sirfsoc_setup()
1010 ret = gpio_is_valid(spi->cs_gpio); in spi_sirfsoc_setup()
1012 dev_err(&spi->dev, "no valid gpio\n"); in spi_sirfsoc_setup()
1013 ret = -ENOENT; in spi_sirfsoc_setup()
1016 ret = gpio_request(spi->cs_gpio, DRIVER_NAME); in spi_sirfsoc_setup()
1018 dev_err(&spi->dev, "failed to request gpio\n"); in spi_sirfsoc_setup()
1021 spi_set_ctldata(spi, cs); in spi_sirfsoc_setup()
1024 spi_sirfsoc_config_mode(spi); in spi_sirfsoc_setup()
1025 spi_sirfsoc_chipselect(spi, BITBANG_CS_INACTIVE); in spi_sirfsoc_setup()
1030 static void spi_sirfsoc_cleanup(struct spi_device *spi) in spi_sirfsoc_cleanup() argument
1032 if (spi_get_ctldata(spi)) { in spi_sirfsoc_cleanup()
1033 gpio_free(spi->cs_gpio); in spi_sirfsoc_cleanup()
1034 kfree(spi_get_ctldata(spi)); in spi_sirfsoc_cleanup()
1062 { .compatible = "sirf,prima2-spi", .data = &sirf_real_spi},
1063 { .compatible = "sirf,prima2-usp-spi", .data = &sirf_usp_spi_p2},
1064 { .compatible = "sirf,atlas7-usp-spi", .data = &sirf_usp_spi_a7},
1078 ret = device_reset(&pdev->dev); in spi_sirfsoc_probe()
1080 dev_err(&pdev->dev, "SPI reset failed!\n"); in spi_sirfsoc_probe()
1084 master = spi_alloc_master(&pdev->dev, sizeof(*sspi)); in spi_sirfsoc_probe()
1086 dev_err(&pdev->dev, "Unable to allocate SPI master\n"); in spi_sirfsoc_probe()
1087 return -ENOMEM; in spi_sirfsoc_probe()
1089 match = of_match_node(spi_sirfsoc_of_match, pdev->dev.of_node); in spi_sirfsoc_probe()
1092 sspi->fifo_full_offset = ilog2(sspi->fifo_size); in spi_sirfsoc_probe()
1093 spi_comp_data = match->data; in spi_sirfsoc_probe()
1094 sspi->regs = spi_comp_data->regs; in spi_sirfsoc_probe()
1095 sspi->type = spi_comp_data->type; in spi_sirfsoc_probe()
1096 sspi->fifo_level_chk_mask = (sspi->fifo_size / 4) - 1; in spi_sirfsoc_probe()
1097 sspi->dat_max_frm_len = spi_comp_data->dat_max_frm_len; in spi_sirfsoc_probe()
1098 sspi->fifo_size = spi_comp_data->fifo_size; in spi_sirfsoc_probe()
1099 sspi->base = devm_platform_ioremap_resource(pdev, 0); in spi_sirfsoc_probe()
1100 if (IS_ERR(sspi->base)) { in spi_sirfsoc_probe()
1101 ret = PTR_ERR(sspi->base); in spi_sirfsoc_probe()
1106 ret = -ENXIO; in spi_sirfsoc_probe()
1109 ret = devm_request_irq(&pdev->dev, irq, spi_sirfsoc_irq, 0, in spi_sirfsoc_probe()
1114 sspi->bitbang.master = master; in spi_sirfsoc_probe()
1115 sspi->bitbang.chipselect = spi_sirfsoc_chipselect; in spi_sirfsoc_probe()
1116 sspi->bitbang.setup_transfer = spi_sirfsoc_setup_transfer; in spi_sirfsoc_probe()
1117 sspi->bitbang.txrx_bufs = spi_sirfsoc_transfer; in spi_sirfsoc_probe()
1118 sspi->bitbang.master->setup = spi_sirfsoc_setup; in spi_sirfsoc_probe()
1119 sspi->bitbang.master->cleanup = spi_sirfsoc_cleanup; in spi_sirfsoc_probe()
1120 master->bus_num = pdev->id; in spi_sirfsoc_probe()
1121 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | SPI_CS_HIGH; in spi_sirfsoc_probe()
1122 master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(12) | in spi_sirfsoc_probe()
1124 master->max_speed_hz = SIRFSOC_SPI_DEFAULT_FRQ; in spi_sirfsoc_probe()
1125 master->flags = SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX; in spi_sirfsoc_probe()
1126 sspi->bitbang.master->dev.of_node = pdev->dev.of_node; in spi_sirfsoc_probe()
1129 sspi->rx_chan = dma_request_chan(&pdev->dev, "rx"); in spi_sirfsoc_probe()
1130 if (IS_ERR(sspi->rx_chan)) { in spi_sirfsoc_probe()
1131 dev_err(&pdev->dev, "can not allocate rx dma channel\n"); in spi_sirfsoc_probe()
1132 ret = PTR_ERR(sspi->rx_chan); in spi_sirfsoc_probe()
1135 sspi->tx_chan = dma_request_chan(&pdev->dev, "tx"); in spi_sirfsoc_probe()
1136 if (IS_ERR(sspi->tx_chan)) { in spi_sirfsoc_probe()
1137 dev_err(&pdev->dev, "can not allocate tx dma channel\n"); in spi_sirfsoc_probe()
1138 ret = PTR_ERR(sspi->tx_chan); in spi_sirfsoc_probe()
1142 sspi->clk = clk_get(&pdev->dev, NULL); in spi_sirfsoc_probe()
1143 if (IS_ERR(sspi->clk)) { in spi_sirfsoc_probe()
1144 ret = PTR_ERR(sspi->clk); in spi_sirfsoc_probe()
1147 clk_prepare_enable(sspi->clk); in spi_sirfsoc_probe()
1148 if (spi_comp_data->hwinit) in spi_sirfsoc_probe()
1149 spi_comp_data->hwinit(sspi); in spi_sirfsoc_probe()
1150 sspi->ctrl_freq = clk_get_rate(sspi->clk); in spi_sirfsoc_probe()
1152 init_completion(&sspi->rx_done); in spi_sirfsoc_probe()
1153 init_completion(&sspi->tx_done); in spi_sirfsoc_probe()
1155 ret = spi_bitbang_start(&sspi->bitbang); in spi_sirfsoc_probe()
1158 dev_info(&pdev->dev, "registered, bus number = %d\n", master->bus_num); in spi_sirfsoc_probe()
1162 clk_disable_unprepare(sspi->clk); in spi_sirfsoc_probe()
1163 clk_put(sspi->clk); in spi_sirfsoc_probe()
1165 dma_release_channel(sspi->tx_chan); in spi_sirfsoc_probe()
1167 dma_release_channel(sspi->rx_chan); in spi_sirfsoc_probe()
1181 spi_bitbang_stop(&sspi->bitbang); in spi_sirfsoc_remove()
1182 clk_disable_unprepare(sspi->clk); in spi_sirfsoc_remove()
1183 clk_put(sspi->clk); in spi_sirfsoc_remove()
1184 dma_release_channel(sspi->rx_chan); in spi_sirfsoc_remove()
1185 dma_release_channel(sspi->tx_chan); in spi_sirfsoc_remove()
1201 clk_disable(sspi->clk); in spi_sirfsoc_suspend()
1210 clk_enable(sspi->clk); in spi_sirfsoc_resume()
1211 writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + sspi->regs->txfifo_op); in spi_sirfsoc_resume()
1212 writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + sspi->regs->rxfifo_op); in spi_sirfsoc_resume()
1213 writel(SIRFSOC_SPI_FIFO_START, sspi->base + sspi->regs->txfifo_op); in spi_sirfsoc_resume()
1214 writel(SIRFSOC_SPI_FIFO_START, sspi->base + sspi->regs->rxfifo_op); in spi_sirfsoc_resume()
1232 MODULE_DESCRIPTION("SiRF SoC SPI master driver");