Lines Matching +full:mclk +full:- +full:div
1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2012 - 2014 Allwinner Tech
7 * Maxime Ripard <maxime.ripard@free-electrons.com>
67 #define SUN6I_CLK_CTL_CDR2(div) (((div) & SUN6I_CLK_CTL_CDR2_MASK) << 0) argument
69 #define SUN6I_CLK_CTL_CDR1(div) (((div) & SUN6I_CLK_CTL_CDR1_MASK) << 8) argument
87 struct clk *mclk; member
100 return readl(sspi->base_addr + reg); in sun6i_spi_read()
105 writel(value, sspi->base_addr + reg); in sun6i_spi_write()
138 while (len--) { in sun6i_spi_drain_fifo()
139 byte = readb(sspi->base_addr + SUN6I_RXDATA_REG); in sun6i_spi_drain_fifo()
140 if (sspi->rx_buf) in sun6i_spi_drain_fifo()
141 *sspi->rx_buf++ = byte; in sun6i_spi_drain_fifo()
152 cnt = sspi->fifo_depth - sun6i_spi_get_tx_fifo_count(sspi); in sun6i_spi_fill_fifo()
154 len = min((int)cnt, sspi->len); in sun6i_spi_fill_fifo()
156 while (len--) { in sun6i_spi_fill_fifo()
157 byte = sspi->tx_buf ? *sspi->tx_buf++ : 0; in sun6i_spi_fill_fifo()
158 writeb(byte, sspi->base_addr + SUN6I_TXDATA_REG); in sun6i_spi_fill_fifo()
159 sspi->len--; in sun6i_spi_fill_fifo()
165 struct sun6i_spi *sspi = spi_master_get_devdata(spi->master); in sun6i_spi_set_cs()
170 reg |= SUN6I_TFR_CTL_CS(spi->chip_select); in sun6i_spi_set_cs()
182 return SUN6I_MAX_XFER_SIZE - 1; in sun6i_spi_max_transfer_size()
190 unsigned int mclk_rate, div, div_cdr1, div_cdr2, timeout; in sun6i_spi_transfer_one() local
197 if (tfr->len > SUN6I_MAX_XFER_SIZE) in sun6i_spi_transfer_one()
198 return -EINVAL; in sun6i_spi_transfer_one()
200 reinit_completion(&sspi->done); in sun6i_spi_transfer_one()
201 sspi->tx_buf = tfr->tx_buf; in sun6i_spi_transfer_one()
202 sspi->rx_buf = tfr->rx_buf; in sun6i_spi_transfer_one()
203 sspi->len = tfr->len; in sun6i_spi_transfer_one()
216 * (See spi-sun4i.c) in sun6i_spi_transfer_one()
218 trig_level = sspi->fifo_depth / 4 * 3; in sun6i_spi_transfer_one()
229 if (spi->mode & SPI_CPOL) in sun6i_spi_transfer_one()
234 if (spi->mode & SPI_CPHA) in sun6i_spi_transfer_one()
239 if (spi->mode & SPI_LSB_FIRST) in sun6i_spi_transfer_one()
248 if (sspi->rx_buf) { in sun6i_spi_transfer_one()
250 rx_len = tfr->len; in sun6i_spi_transfer_one()
261 mclk_rate = clk_get_rate(sspi->mclk); in sun6i_spi_transfer_one()
262 if (mclk_rate < (2 * tfr->speed_hz)) { in sun6i_spi_transfer_one()
263 clk_set_rate(sspi->mclk, 2 * tfr->speed_hz); in sun6i_spi_transfer_one()
264 mclk_rate = clk_get_rate(sspi->mclk); in sun6i_spi_transfer_one()
281 div_cdr1 = DIV_ROUND_UP(mclk_rate, tfr->speed_hz); in sun6i_spi_transfer_one()
284 reg = SUN6I_CLK_CTL_CDR2(div_cdr2 - 1) | SUN6I_CLK_CTL_DRS; in sun6i_spi_transfer_one()
285 tfr->effective_speed_hz = mclk_rate / (2 * div_cdr2); in sun6i_spi_transfer_one()
287 div = min(SUN6I_CLK_CTL_CDR1_MASK, order_base_2(div_cdr1)); in sun6i_spi_transfer_one()
288 reg = SUN6I_CLK_CTL_CDR1(div); in sun6i_spi_transfer_one()
289 tfr->effective_speed_hz = mclk_rate / (1 << div); in sun6i_spi_transfer_one()
293 /* Finally enable the bus - doing so before might raise SCK to HIGH */ in sun6i_spi_transfer_one()
299 if (sspi->tx_buf) in sun6i_spi_transfer_one()
300 tx_len = tfr->len; in sun6i_spi_transfer_one()
303 sun6i_spi_write(sspi, SUN6I_BURST_CNT_REG, tfr->len); in sun6i_spi_transfer_one()
313 if (rx_len > sspi->fifo_depth) in sun6i_spi_transfer_one()
315 if (tx_len > sspi->fifo_depth) in sun6i_spi_transfer_one()
324 tx_time = max(tfr->len * 8 * 2 / (tfr->speed_hz / 1000), 100U); in sun6i_spi_transfer_one()
326 timeout = wait_for_completion_timeout(&sspi->done, in sun6i_spi_transfer_one()
330 dev_warn(&master->dev, in sun6i_spi_transfer_one()
332 dev_name(&spi->dev), tfr->len, tfr->speed_hz, in sun6i_spi_transfer_one()
333 jiffies_to_msecs(end - start), tx_time); in sun6i_spi_transfer_one()
334 ret = -ETIMEDOUT; in sun6i_spi_transfer_one()
351 complete(&sspi->done); in sun6i_spi_handler()
367 if (!sspi->len) in sun6i_spi_handler()
371 /* Only clear the interrupt _after_ re-seeding the FIFO */ in sun6i_spi_handler()
386 ret = clk_prepare_enable(sspi->hclk); in sun6i_spi_runtime_resume()
392 ret = clk_prepare_enable(sspi->mclk); in sun6i_spi_runtime_resume()
398 ret = reset_control_deassert(sspi->rstc); in sun6i_spi_runtime_resume()
410 clk_disable_unprepare(sspi->mclk); in sun6i_spi_runtime_resume()
412 clk_disable_unprepare(sspi->hclk); in sun6i_spi_runtime_resume()
422 reset_control_assert(sspi->rstc); in sun6i_spi_runtime_suspend()
423 clk_disable_unprepare(sspi->mclk); in sun6i_spi_runtime_suspend()
424 clk_disable_unprepare(sspi->hclk); in sun6i_spi_runtime_suspend()
435 master = spi_alloc_master(&pdev->dev, sizeof(struct sun6i_spi)); in sun6i_spi_probe()
437 dev_err(&pdev->dev, "Unable to allocate SPI Master\n"); in sun6i_spi_probe()
438 return -ENOMEM; in sun6i_spi_probe()
444 sspi->base_addr = devm_platform_ioremap_resource(pdev, 0); in sun6i_spi_probe()
445 if (IS_ERR(sspi->base_addr)) { in sun6i_spi_probe()
446 ret = PTR_ERR(sspi->base_addr); in sun6i_spi_probe()
452 ret = -ENXIO; in sun6i_spi_probe()
456 ret = devm_request_irq(&pdev->dev, irq, sun6i_spi_handler, in sun6i_spi_probe()
457 0, "sun6i-spi", sspi); in sun6i_spi_probe()
459 dev_err(&pdev->dev, "Cannot request IRQ\n"); in sun6i_spi_probe()
463 sspi->master = master; in sun6i_spi_probe()
464 sspi->fifo_depth = (unsigned long)of_device_get_match_data(&pdev->dev); in sun6i_spi_probe()
466 master->max_speed_hz = 100 * 1000 * 1000; in sun6i_spi_probe()
467 master->min_speed_hz = 3 * 1000; in sun6i_spi_probe()
468 master->use_gpio_descriptors = true; in sun6i_spi_probe()
469 master->set_cs = sun6i_spi_set_cs; in sun6i_spi_probe()
470 master->transfer_one = sun6i_spi_transfer_one; in sun6i_spi_probe()
471 master->num_chipselect = 4; in sun6i_spi_probe()
472 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST; in sun6i_spi_probe()
473 master->bits_per_word_mask = SPI_BPW_MASK(8); in sun6i_spi_probe()
474 master->dev.of_node = pdev->dev.of_node; in sun6i_spi_probe()
475 master->auto_runtime_pm = true; in sun6i_spi_probe()
476 master->max_transfer_size = sun6i_spi_max_transfer_size; in sun6i_spi_probe()
478 sspi->hclk = devm_clk_get(&pdev->dev, "ahb"); in sun6i_spi_probe()
479 if (IS_ERR(sspi->hclk)) { in sun6i_spi_probe()
480 dev_err(&pdev->dev, "Unable to acquire AHB clock\n"); in sun6i_spi_probe()
481 ret = PTR_ERR(sspi->hclk); in sun6i_spi_probe()
485 sspi->mclk = devm_clk_get(&pdev->dev, "mod"); in sun6i_spi_probe()
486 if (IS_ERR(sspi->mclk)) { in sun6i_spi_probe()
487 dev_err(&pdev->dev, "Unable to acquire module clock\n"); in sun6i_spi_probe()
488 ret = PTR_ERR(sspi->mclk); in sun6i_spi_probe()
492 init_completion(&sspi->done); in sun6i_spi_probe()
494 sspi->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL); in sun6i_spi_probe()
495 if (IS_ERR(sspi->rstc)) { in sun6i_spi_probe()
496 dev_err(&pdev->dev, "Couldn't get reset controller\n"); in sun6i_spi_probe()
497 ret = PTR_ERR(sspi->rstc); in sun6i_spi_probe()
502 * This wake-up/shutdown pattern is to be able to have the in sun6i_spi_probe()
505 ret = sun6i_spi_runtime_resume(&pdev->dev); in sun6i_spi_probe()
507 dev_err(&pdev->dev, "Couldn't resume the device\n"); in sun6i_spi_probe()
511 pm_runtime_set_active(&pdev->dev); in sun6i_spi_probe()
512 pm_runtime_enable(&pdev->dev); in sun6i_spi_probe()
513 pm_runtime_idle(&pdev->dev); in sun6i_spi_probe()
515 ret = devm_spi_register_master(&pdev->dev, master); in sun6i_spi_probe()
517 dev_err(&pdev->dev, "cannot register SPI master\n"); in sun6i_spi_probe()
524 pm_runtime_disable(&pdev->dev); in sun6i_spi_probe()
525 sun6i_spi_runtime_suspend(&pdev->dev); in sun6i_spi_probe()
533 pm_runtime_force_suspend(&pdev->dev); in sun6i_spi_remove()
539 { .compatible = "allwinner,sun6i-a31-spi", .data = (void *)SUN6I_FIFO_DEPTH },
540 { .compatible = "allwinner,sun8i-h3-spi", .data = (void *)SUN8I_FIFO_DEPTH },
554 .name = "sun6i-spi",
562 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");