65 	cr = readb(uap->port.membase + UART010_CR);  in pl010_stop_tx()
67 	writel(cr, uap->port.membase + UART010_CR);  in pl010_stop_tx()
76 	cr = readb(uap->port.membase + UART010_CR);  in pl010_start_tx()
78 	writel(cr, uap->port.membase + UART010_CR);  in pl010_start_tx()
87 	cr = readb(uap->port.membase + UART010_CR);  in pl010_stop_rx()
89 	writel(cr, uap->port.membase + UART010_CR);  in pl010_stop_rx()
97 	cr = readb(uap->port.membase + UART010_CR);  in pl010_disable_ms()
99 	writel(cr, uap->port.membase + UART010_CR);  in pl010_disable_ms()
108 	cr = readb(uap->port.membase + UART010_CR);  in pl010_enable_ms()
110 	writel(cr, uap->port.membase + UART010_CR);  in pl010_enable_ms()
117 	status = readb(uap->port.membase + UART01x_FR);  in pl010_rx_chars()
119 		ch = readb(uap->port.membase + UART01x_DR);  in pl010_rx_chars()
128 		rsr = readb(uap->port.membase + UART01x_RSR) | UART_DUMMY_RSR_RX;  in pl010_rx_chars()
130 			writel(0, uap->port.membase + UART01x_ECR);  in pl010_rx_chars()
160 		status = readb(uap->port.membase + UART01x_FR);  in pl010_rx_chars()
173 		writel(uap->port.x_char, uap->port.membase + UART01x_DR);  in pl010_tx_chars()
185 		writel(xmit->buf[xmit->tail], uap->port.membase + UART01x_DR);  in pl010_tx_chars()
203 	writel(0, uap->port.membase + UART010_ICR);  in pl010_modem_status()
205 	status = readb(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;  in pl010_modem_status()
233 	status = readb(uap->port.membase + UART010_IIR);  in pl010_int()
246 			status = readb(uap->port.membase + UART010_IIR);  in pl010_int()
261 	unsigned int status = readb(uap->port.membase + UART01x_FR);  in pl010_tx_empty()
272 	status = readb(uap->port.membase + UART01x_FR);  in pl010_get_mctrl()
289 		uap->data->set_mctrl(uap->dev, uap->port.membase, mctrl);  in pl010_set_mctrl()
300 	lcr_h = readb(uap->port.membase + UART010_LCRH);  in pl010_break_ctl()
305 	writel(lcr_h, uap->port.membase + UART010_LCRH);  in pl010_break_ctl()
334 	uap->old_status = readb(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;  in pl010_startup()
340 	       uap->port.membase + UART010_CR);  in pl010_startup()
363 	writel(0, uap->port.membase + UART010_CR);  in pl010_shutdown()
366 	writel(readb(uap->port.membase + UART010_LCRH) &  in pl010_shutdown()
368 	       uap->port.membase + UART010_LCRH);  in pl010_shutdown()
451 	old_cr = readb(uap->port.membase + UART010_CR) & ~UART010_CR_MSIE;  in pl010_set_termios()
458 	writel((quot & 0xf00) >> 8, uap->port.membase + UART010_LCRM);  in pl010_set_termios()
459 	writel(quot & 0xff, uap->port.membase + UART010_LCRL);  in pl010_set_termios()
466 	writel(lcr_h, uap->port.membase + UART010_LCRH);  in pl010_set_termios()
467 	writel(old_cr, uap->port.membase + UART010_CR);  in pl010_set_termios()
568 		status = readb(uap->port.membase + UART01x_FR);  in pl010_console_putchar()
571 	writel(ch, uap->port.membase + UART01x_DR);  in pl010_console_putchar()
585 	old_cr = readb(uap->port.membase + UART010_CR);  in pl010_console_write()
586 	writel(UART01x_CR_UARTEN, uap->port.membase + UART010_CR);  in pl010_console_write()
595 		status = readb(uap->port.membase + UART01x_FR);  in pl010_console_write()
598 	writel(old_cr, uap->port.membase + UART010_CR);  in pl010_console_write()
607 	if (readb(uap->port.membase + UART010_CR) & UART01x_CR_UARTEN) {  in pl010_console_get_options()
609 		lcr_h = readb(uap->port.membase + UART010_LCRH);  in pl010_console_get_options()
624 		quot = readb(uap->port.membase + UART010_LCRL) |  in pl010_console_get_options()
625 		       readb(uap->port.membase + UART010_LCRM) << 8;  in pl010_console_get_options()
720 	uap->port.membase = base;  in pl010_probe()