Lines Matching +full:imx7ulp +full:- +full:edma
1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright 2012-2014 Freescale Semiconductor, Inc.
10 #include <linux/dma-mapping.h>
23 /* All registers are 8-bit width */
112 /* 32-bit register definition */
225 #define DRIVER_NAME "fsl-lpuart"
302 { .compatible = "fsl,vf610-lpuart", .data = &vf_data, },
303 { .compatible = "fsl,ls1021a-lpuart", .data = &ls1021a_data, },
304 { .compatible = "fsl,ls1028a-lpuart", .data = &ls1028a_data, },
305 { .compatible = "fsl,imx7ulp-lpuart", .data = &imx7ulp_data, },
306 { .compatible = "fsl,imx8qxp-lpuart", .data = &imx8qxp_data, },
316 return (sport->devtype == LS1021A_LPUART || in is_layerscape_lpuart()
317 sport->devtype == LS1028A_LPUART); in is_layerscape_lpuart()
322 return sport->devtype == IMX8QXP_LPUART; in is_imx8qxp_lpuart()
327 switch (port->iotype) { in lpuart32_read()
329 return readl(port->membase + off); in lpuart32_read()
331 return ioread32be(port->membase + off); in lpuart32_read()
340 switch (port->iotype) { in lpuart32_write()
342 writel(val, port->membase + off); in lpuart32_write()
345 iowrite32be(val, port->membase + off); in lpuart32_write()
355 ret = clk_prepare_enable(sport->ipg_clk); in __lpuart_enable_clks()
359 ret = clk_prepare_enable(sport->baud_clk); in __lpuart_enable_clks()
361 clk_disable_unprepare(sport->ipg_clk); in __lpuart_enable_clks()
365 clk_disable_unprepare(sport->baud_clk); in __lpuart_enable_clks()
366 clk_disable_unprepare(sport->ipg_clk); in __lpuart_enable_clks()
375 return clk_get_rate(sport->baud_clk); in lpuart_get_baud_clk_rate()
377 return clk_get_rate(sport->ipg_clk); in lpuart_get_baud_clk_rate()
387 temp = readb(port->membase + UARTCR2); in lpuart_stop_tx()
389 writeb(temp, port->membase + UARTCR2); in lpuart_stop_tx()
405 temp = readb(port->membase + UARTCR2); in lpuart_stop_rx()
406 writeb(temp & ~UARTCR2_RE, port->membase + UARTCR2); in lpuart_stop_rx()
419 struct circ_buf *xmit = &sport->port.state->xmit; in lpuart_dma_tx()
420 struct scatterlist *sgl = sport->tx_sgl; in lpuart_dma_tx()
421 struct device *dev = sport->port.dev; in lpuart_dma_tx()
422 struct dma_chan *chan = sport->dma_tx_chan; in lpuart_dma_tx()
425 if (sport->dma_tx_in_progress) in lpuart_dma_tx()
428 sport->dma_tx_bytes = uart_circ_chars_pending(xmit); in lpuart_dma_tx()
430 if (xmit->tail < xmit->head || xmit->head == 0) { in lpuart_dma_tx()
431 sport->dma_tx_nents = 1; in lpuart_dma_tx()
432 sg_init_one(sgl, xmit->buf + xmit->tail, sport->dma_tx_bytes); in lpuart_dma_tx()
434 sport->dma_tx_nents = 2; in lpuart_dma_tx()
436 sg_set_buf(sgl, xmit->buf + xmit->tail, in lpuart_dma_tx()
437 UART_XMIT_SIZE - xmit->tail); in lpuart_dma_tx()
438 sg_set_buf(sgl + 1, xmit->buf, xmit->head); in lpuart_dma_tx()
441 ret = dma_map_sg(chan->device->dev, sgl, sport->dma_tx_nents, in lpuart_dma_tx()
448 sport->dma_tx_desc = dmaengine_prep_slave_sg(chan, sgl, in lpuart_dma_tx()
451 if (!sport->dma_tx_desc) { in lpuart_dma_tx()
452 dma_unmap_sg(chan->device->dev, sgl, sport->dma_tx_nents, in lpuart_dma_tx()
458 sport->dma_tx_desc->callback = lpuart_dma_tx_complete; in lpuart_dma_tx()
459 sport->dma_tx_desc->callback_param = sport; in lpuart_dma_tx()
460 sport->dma_tx_in_progress = true; in lpuart_dma_tx()
461 sport->dma_tx_cookie = dmaengine_submit(sport->dma_tx_desc); in lpuart_dma_tx()
467 return uart_circ_empty(&port->state->xmit) || uart_tx_stopped(port); in lpuart_stopped_or_empty()
473 struct scatterlist *sgl = &sport->tx_sgl[0]; in lpuart_dma_tx_complete()
474 struct circ_buf *xmit = &sport->port.state->xmit; in lpuart_dma_tx_complete()
475 struct dma_chan *chan = sport->dma_tx_chan; in lpuart_dma_tx_complete()
478 spin_lock_irqsave(&sport->port.lock, flags); in lpuart_dma_tx_complete()
480 dma_unmap_sg(chan->device->dev, sgl, sport->dma_tx_nents, in lpuart_dma_tx_complete()
483 xmit->tail = (xmit->tail + sport->dma_tx_bytes) & (UART_XMIT_SIZE - 1); in lpuart_dma_tx_complete()
485 sport->port.icount.tx += sport->dma_tx_bytes; in lpuart_dma_tx_complete()
486 sport->dma_tx_in_progress = false; in lpuart_dma_tx_complete()
487 spin_unlock_irqrestore(&sport->port.lock, flags); in lpuart_dma_tx_complete()
490 uart_write_wakeup(&sport->port); in lpuart_dma_tx_complete()
492 if (waitqueue_active(&sport->dma_wait)) { in lpuart_dma_tx_complete()
493 wake_up(&sport->dma_wait); in lpuart_dma_tx_complete()
497 spin_lock_irqsave(&sport->port.lock, flags); in lpuart_dma_tx_complete()
499 if (!lpuart_stopped_or_empty(&sport->port)) in lpuart_dma_tx_complete()
502 spin_unlock_irqrestore(&sport->port.lock, flags); in lpuart_dma_tx_complete()
507 switch (sport->port.iotype) { in lpuart_dma_datareg_addr()
509 return sport->port.mapbase + UARTDATA; in lpuart_dma_datareg_addr()
511 return sport->port.mapbase + UARTDATA + sizeof(u32) - 1; in lpuart_dma_datareg_addr()
513 return sport->port.mapbase + UARTDR; in lpuart_dma_datareg_addr()
527 ret = dmaengine_slave_config(sport->dma_tx_chan, &dma_tx_sconfig); in lpuart_dma_tx_request()
530 dev_err(sport->port.dev, in lpuart_dma_tx_request()
540 return sport->port.iotype == UPIO_MEM32 || in lpuart_is_32()
541 sport->port.iotype == UPIO_MEM32BE; in lpuart_is_32()
547 struct dma_chan *chan = sport->dma_tx_chan; in lpuart_flush_buffer()
550 if (sport->lpuart_dma_tx_use) { in lpuart_flush_buffer()
551 if (sport->dma_tx_in_progress) { in lpuart_flush_buffer()
552 dma_unmap_sg(chan->device->dev, &sport->tx_sgl[0], in lpuart_flush_buffer()
553 sport->dma_tx_nents, DMA_TO_DEVICE); in lpuart_flush_buffer()
554 sport->dma_tx_in_progress = false; in lpuart_flush_buffer()
560 val = lpuart32_read(&sport->port, UARTFIFO); in lpuart_flush_buffer()
562 lpuart32_write(&sport->port, val, UARTFIFO); in lpuart_flush_buffer()
564 val = readb(sport->port.membase + UARTCFIFO); in lpuart_flush_buffer()
566 writeb(val, sport->port.membase + UARTCFIFO); in lpuart_flush_buffer()
573 while (!(readb(port->membase + offset) & bit)) in lpuart_wait_bit_set()
593 sport->port.fifosize = 0; in lpuart_poll_init()
595 spin_lock_irqsave(&sport->port.lock, flags); in lpuart_poll_init()
597 writeb(0, sport->port.membase + UARTCR2); in lpuart_poll_init()
599 temp = readb(sport->port.membase + UARTPFIFO); in lpuart_poll_init()
602 sport->port.membase + UARTPFIFO); in lpuart_poll_init()
606 sport->port.membase + UARTCFIFO); in lpuart_poll_init()
609 if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) { in lpuart_poll_init()
610 readb(sport->port.membase + UARTDR); in lpuart_poll_init()
611 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO); in lpuart_poll_init()
614 writeb(0, sport->port.membase + UARTTWFIFO); in lpuart_poll_init()
615 writeb(1, sport->port.membase + UARTRWFIFO); in lpuart_poll_init()
618 writeb(UARTCR2_RE | UARTCR2_TE, sport->port.membase + UARTCR2); in lpuart_poll_init()
619 spin_unlock_irqrestore(&sport->port.lock, flags); in lpuart_poll_init()
628 writeb(c, port->membase + UARTDR); in lpuart_poll_put_char()
633 if (!(readb(port->membase + UARTSR1) & UARTSR1_RDRF)) in lpuart_poll_get_char()
636 return readb(port->membase + UARTDR); in lpuart_poll_get_char()
645 sport->port.fifosize = 0; in lpuart32_poll_init()
647 spin_lock_irqsave(&sport->port.lock, flags); in lpuart32_poll_init()
650 lpuart32_write(&sport->port, 0, UARTCTRL); in lpuart32_poll_init()
652 temp = lpuart32_read(&sport->port, UARTFIFO); in lpuart32_poll_init()
655 lpuart32_write(&sport->port, temp | UARTFIFO_RXFE | UARTFIFO_TXFE, UARTFIFO); in lpuart32_poll_init()
658 lpuart32_write(&sport->port, UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH, UARTFIFO); in lpuart32_poll_init()
661 if (lpuart32_read(&sport->port, UARTSTAT) & UARTSTAT_RDRF) { in lpuart32_poll_init()
662 lpuart32_read(&sport->port, UARTDATA); in lpuart32_poll_init()
663 lpuart32_write(&sport->port, UARTFIFO_RXUF, UARTFIFO); in lpuart32_poll_init()
667 lpuart32_write(&sport->port, UARTCTRL_RE | UARTCTRL_TE, UARTCTRL); in lpuart32_poll_init()
668 spin_unlock_irqrestore(&sport->port.lock, flags); in lpuart32_poll_init()
690 struct circ_buf *xmit = &sport->port.state->xmit; in lpuart_transmit_buffer()
692 if (sport->port.x_char) { in lpuart_transmit_buffer()
693 writeb(sport->port.x_char, sport->port.membase + UARTDR); in lpuart_transmit_buffer()
694 sport->port.icount.tx++; in lpuart_transmit_buffer()
695 sport->port.x_char = 0; in lpuart_transmit_buffer()
699 if (lpuart_stopped_or_empty(&sport->port)) { in lpuart_transmit_buffer()
700 lpuart_stop_tx(&sport->port); in lpuart_transmit_buffer()
705 (readb(sport->port.membase + UARTTCFIFO) < sport->txfifo_size)) { in lpuart_transmit_buffer()
706 writeb(xmit->buf[xmit->tail], sport->port.membase + UARTDR); in lpuart_transmit_buffer()
707 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); in lpuart_transmit_buffer()
708 sport->port.icount.tx++; in lpuart_transmit_buffer()
712 uart_write_wakeup(&sport->port); in lpuart_transmit_buffer()
715 lpuart_stop_tx(&sport->port); in lpuart_transmit_buffer()
720 struct circ_buf *xmit = &sport->port.state->xmit; in lpuart32_transmit_buffer()
723 if (sport->port.x_char) { in lpuart32_transmit_buffer()
724 lpuart32_write(&sport->port, sport->port.x_char, UARTDATA); in lpuart32_transmit_buffer()
725 sport->port.icount.tx++; in lpuart32_transmit_buffer()
726 sport->port.x_char = 0; in lpuart32_transmit_buffer()
730 if (lpuart_stopped_or_empty(&sport->port)) { in lpuart32_transmit_buffer()
731 lpuart32_stop_tx(&sport->port); in lpuart32_transmit_buffer()
735 txcnt = lpuart32_read(&sport->port, UARTWATER); in lpuart32_transmit_buffer()
738 while (!uart_circ_empty(xmit) && (txcnt < sport->txfifo_size)) { in lpuart32_transmit_buffer()
739 lpuart32_write(&sport->port, xmit->buf[xmit->tail], UARTDATA); in lpuart32_transmit_buffer()
740 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); in lpuart32_transmit_buffer()
741 sport->port.icount.tx++; in lpuart32_transmit_buffer()
742 txcnt = lpuart32_read(&sport->port, UARTWATER); in lpuart32_transmit_buffer()
748 uart_write_wakeup(&sport->port); in lpuart32_transmit_buffer()
751 lpuart32_stop_tx(&sport->port); in lpuart32_transmit_buffer()
760 temp = readb(port->membase + UARTCR2); in lpuart_start_tx()
761 writeb(temp | UARTCR2_TIE, port->membase + UARTCR2); in lpuart_start_tx()
763 if (sport->lpuart_dma_tx_use) { in lpuart_start_tx()
767 if (readb(port->membase + UARTSR1) & UARTSR1_TDRE) in lpuart_start_tx()
777 if (sport->lpuart_dma_tx_use) { in lpuart32_start_tx()
794 unsigned char sr1 = readb(port->membase + UARTSR1); in lpuart_tx_empty()
795 unsigned char sfifo = readb(port->membase + UARTSFIFO); in lpuart_tx_empty()
797 if (sport->dma_tx_in_progress) in lpuart_tx_empty()
814 if (sport->dma_tx_in_progress) in lpuart32_tx_empty()
832 spin_lock_irqsave(&sport->port.lock, flags); in lpuart_txint()
834 spin_unlock_irqrestore(&sport->port.lock, flags); in lpuart_txint()
840 struct tty_port *port = &sport->port.state->port; in lpuart_rxint()
844 spin_lock_irqsave(&sport->port.lock, flags); in lpuart_rxint()
846 while (!(readb(sport->port.membase + UARTSFIFO) & UARTSFIFO_RXEMPT)) { in lpuart_rxint()
848 sport->port.icount.rx++; in lpuart_rxint()
853 sr = readb(sport->port.membase + UARTSR1); in lpuart_rxint()
854 rx = readb(sport->port.membase + UARTDR); in lpuart_rxint()
856 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) in lpuart_rxint()
861 sport->port.icount.parity++; in lpuart_rxint()
863 sport->port.icount.frame++; in lpuart_rxint()
868 if (sr & sport->port.ignore_status_mask) { in lpuart_rxint()
874 sr &= sport->port.read_status_mask; in lpuart_rxint()
884 sport->port.sysrq = 0; in lpuart_rxint()
892 sport->port.icount.overrun += overrun; in lpuart_rxint()
898 writeb(UARTCFIFO_RXFLUSH, sport->port.membase + UARTCFIFO); in lpuart_rxint()
899 writeb(UARTSFIFO_RXOF, sport->port.membase + UARTSFIFO); in lpuart_rxint()
902 spin_unlock_irqrestore(&sport->port.lock, flags); in lpuart_rxint()
911 spin_lock_irqsave(&sport->port.lock, flags); in lpuart32_txint()
913 spin_unlock_irqrestore(&sport->port.lock, flags); in lpuart32_txint()
919 struct tty_port *port = &sport->port.state->port; in lpuart32_rxint()
923 spin_lock_irqsave(&sport->port.lock, flags); in lpuart32_rxint()
925 while (!(lpuart32_read(&sport->port, UARTFIFO) & UARTFIFO_RXEMPT)) { in lpuart32_rxint()
927 sport->port.icount.rx++; in lpuart32_rxint()
932 sr = lpuart32_read(&sport->port, UARTSTAT); in lpuart32_rxint()
933 rx = lpuart32_read(&sport->port, UARTDATA); in lpuart32_rxint()
936 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) in lpuart32_rxint()
941 sport->port.icount.parity++; in lpuart32_rxint()
943 sport->port.icount.frame++; in lpuart32_rxint()
946 sport->port.icount.overrun++; in lpuart32_rxint()
948 if (sr & sport->port.ignore_status_mask) { in lpuart32_rxint()
954 sr &= sport->port.read_status_mask; in lpuart32_rxint()
964 sport->port.sysrq = 0; in lpuart32_rxint()
971 spin_unlock_irqrestore(&sport->port.lock, flags); in lpuart32_rxint()
981 sts = readb(sport->port.membase + UARTSR1); in lpuart_int()
984 if (sts & UARTSR1_FE && sport->lpuart_dma_rx_use) { in lpuart_int()
985 readb(sport->port.membase + UARTDR); in lpuart_int()
986 uart_handle_break(&sport->port); in lpuart_int()
988 writeb(UARTCFIFO_RXFLUSH, sport->port.membase + UARTCFIFO); in lpuart_int()
992 if (sts & UARTSR1_RDRF && !sport->lpuart_dma_rx_use) in lpuart_int()
995 if (sts & UARTSR1_TDRE && !sport->lpuart_dma_tx_use) in lpuart_int()
1006 sts = lpuart32_read(&sport->port, UARTSTAT); in lpuart32_int()
1007 rxcount = lpuart32_read(&sport->port, UARTWATER); in lpuart32_int()
1010 if ((sts & UARTSTAT_RDRF || rxcount > 0) && !sport->lpuart_dma_rx_use) in lpuart32_int()
1013 if ((sts & UARTSTAT_TDRE) && !sport->lpuart_dma_tx_use) in lpuart32_int()
1016 lpuart32_write(&sport->port, sts, UARTSTAT); in lpuart32_int()
1024 while (count--) { in lpuart_handle_sysrq_chars()
1033 struct circ_buf *ring = &sport->rx_ring; in lpuart_handle_sysrq()
1036 if (ring->head < ring->tail) { in lpuart_handle_sysrq()
1037 count = sport->rx_sgl.length - ring->tail; in lpuart_handle_sysrq()
1038 lpuart_handle_sysrq_chars(&sport->port, in lpuart_handle_sysrq()
1039 ring->buf + ring->tail, count); in lpuart_handle_sysrq()
1040 ring->tail = 0; in lpuart_handle_sysrq()
1043 if (ring->head > ring->tail) { in lpuart_handle_sysrq()
1044 count = ring->head - ring->tail; in lpuart_handle_sysrq()
1045 lpuart_handle_sysrq_chars(&sport->port, in lpuart_handle_sysrq()
1046 ring->buf + ring->tail, count); in lpuart_handle_sysrq()
1047 ring->tail = ring->head; in lpuart_handle_sysrq()
1053 struct tty_port *port = &sport->port.state->port; in lpuart_copy_rx_to_tty()
1056 struct dma_chan *chan = sport->dma_rx_chan; in lpuart_copy_rx_to_tty()
1057 struct circ_buf *ring = &sport->rx_ring; in lpuart_copy_rx_to_tty()
1062 unsigned long sr = lpuart32_read(&sport->port, UARTSTAT); in lpuart_copy_rx_to_tty()
1066 lpuart32_write(&sport->port, sr, UARTSTAT); in lpuart_copy_rx_to_tty()
1069 sport->port.icount.parity++; in lpuart_copy_rx_to_tty()
1071 sport->port.icount.frame++; in lpuart_copy_rx_to_tty()
1074 unsigned char sr = readb(sport->port.membase + UARTSR1); in lpuart_copy_rx_to_tty()
1080 cr2 = readb(sport->port.membase + UARTCR2); in lpuart_copy_rx_to_tty()
1082 writeb(cr2, sport->port.membase + UARTCR2); in lpuart_copy_rx_to_tty()
1085 readb(sport->port.membase + UARTDR); in lpuart_copy_rx_to_tty()
1088 sport->port.icount.parity++; in lpuart_copy_rx_to_tty()
1090 sport->port.icount.frame++; in lpuart_copy_rx_to_tty()
1100 if (readb(sport->port.membase + UARTSFIFO) & in lpuart_copy_rx_to_tty()
1103 sport->port.membase + UARTSFIFO); in lpuart_copy_rx_to_tty()
1105 sport->port.membase + UARTCFIFO); in lpuart_copy_rx_to_tty()
1109 writeb(cr2, sport->port.membase + UARTCR2); in lpuart_copy_rx_to_tty()
1113 async_tx_ack(sport->dma_rx_desc); in lpuart_copy_rx_to_tty()
1115 spin_lock_irqsave(&sport->port.lock, flags); in lpuart_copy_rx_to_tty()
1117 dmastat = dmaengine_tx_status(chan, sport->dma_rx_cookie, &state); in lpuart_copy_rx_to_tty()
1119 dev_err(sport->port.dev, "Rx DMA transfer failed!\n"); in lpuart_copy_rx_to_tty()
1120 spin_unlock_irqrestore(&sport->port.lock, flags); in lpuart_copy_rx_to_tty()
1125 dma_sync_sg_for_cpu(chan->device->dev, &sport->rx_sgl, 1, in lpuart_copy_rx_to_tty()
1129 * ring->head points to the end of data already written by the DMA. in lpuart_copy_rx_to_tty()
1130 * ring->tail points to the beginning of data to be read by the in lpuart_copy_rx_to_tty()
1135 ring->head = sport->rx_sgl.length - state.residue; in lpuart_copy_rx_to_tty()
1136 BUG_ON(ring->head > sport->rx_sgl.length); in lpuart_copy_rx_to_tty()
1141 if (sport->port.sysrq) { in lpuart_copy_rx_to_tty()
1147 * At this point ring->head may point to the first byte right after the in lpuart_copy_rx_to_tty()
1149 * 0 <= ring->head <= sport->rx_sgl.length in lpuart_copy_rx_to_tty()
1151 * However ring->tail must always points inside the dma buffer: in lpuart_copy_rx_to_tty()
1152 * 0 <= ring->tail <= sport->rx_sgl.length - 1 in lpuart_copy_rx_to_tty()
1158 if (ring->head < ring->tail) { in lpuart_copy_rx_to_tty()
1159 count = sport->rx_sgl.length - ring->tail; in lpuart_copy_rx_to_tty()
1161 tty_insert_flip_string(port, ring->buf + ring->tail, count); in lpuart_copy_rx_to_tty()
1162 ring->tail = 0; in lpuart_copy_rx_to_tty()
1163 sport->port.icount.rx += count; in lpuart_copy_rx_to_tty()
1167 if (ring->tail < ring->head) { in lpuart_copy_rx_to_tty()
1168 count = ring->head - ring->tail; in lpuart_copy_rx_to_tty()
1169 tty_insert_flip_string(port, ring->buf + ring->tail, count); in lpuart_copy_rx_to_tty()
1170 /* Wrap ring->head if needed */ in lpuart_copy_rx_to_tty()
1171 if (ring->head >= sport->rx_sgl.length) in lpuart_copy_rx_to_tty()
1172 ring->head = 0; in lpuart_copy_rx_to_tty()
1173 ring->tail = ring->head; in lpuart_copy_rx_to_tty()
1174 sport->port.icount.rx += count; in lpuart_copy_rx_to_tty()
1178 dma_sync_sg_for_device(chan->device->dev, &sport->rx_sgl, 1, in lpuart_copy_rx_to_tty()
1181 spin_unlock_irqrestore(&sport->port.lock, flags); in lpuart_copy_rx_to_tty()
1184 mod_timer(&sport->lpuart_timer, jiffies + sport->dma_rx_timeout); in lpuart_copy_rx_to_tty()
1204 struct circ_buf *ring = &sport->rx_ring; in lpuart_start_rx_dma()
1207 struct tty_port *port = &sport->port.state->port; in lpuart_start_rx_dma()
1208 struct tty_struct *tty = port->tty; in lpuart_start_rx_dma()
1209 struct ktermios *termios = &tty->termios; in lpuart_start_rx_dma()
1210 struct dma_chan *chan = sport->dma_rx_chan; in lpuart_start_rx_dma()
1214 bits = (termios->c_cflag & CSIZE) == CS7 ? 9 : 10; in lpuart_start_rx_dma()
1215 if (termios->c_cflag & PARENB) in lpuart_start_rx_dma()
1222 sport->rx_dma_rng_buf_len = (DMA_RX_TIMEOUT * baud / bits / 1000) * 2; in lpuart_start_rx_dma()
1223 sport->rx_dma_rng_buf_len = (1 << fls(sport->rx_dma_rng_buf_len)); in lpuart_start_rx_dma()
1224 if (sport->rx_dma_rng_buf_len < 16) in lpuart_start_rx_dma()
1225 sport->rx_dma_rng_buf_len = 16; in lpuart_start_rx_dma()
1227 ring->buf = kzalloc(sport->rx_dma_rng_buf_len, GFP_ATOMIC); in lpuart_start_rx_dma()
1228 if (!ring->buf) in lpuart_start_rx_dma()
1229 return -ENOMEM; in lpuart_start_rx_dma()
1231 sg_init_one(&sport->rx_sgl, ring->buf, sport->rx_dma_rng_buf_len); in lpuart_start_rx_dma()
1232 nent = dma_map_sg(chan->device->dev, &sport->rx_sgl, 1, in lpuart_start_rx_dma()
1236 dev_err(sport->port.dev, "DMA Rx mapping error\n"); in lpuart_start_rx_dma()
1237 return -EINVAL; in lpuart_start_rx_dma()
1247 dev_err(sport->port.dev, in lpuart_start_rx_dma()
1252 sport->dma_rx_desc = dmaengine_prep_dma_cyclic(chan, in lpuart_start_rx_dma()
1253 sg_dma_address(&sport->rx_sgl), in lpuart_start_rx_dma()
1254 sport->rx_sgl.length, in lpuart_start_rx_dma()
1255 sport->rx_sgl.length / 2, in lpuart_start_rx_dma()
1258 if (!sport->dma_rx_desc) { in lpuart_start_rx_dma()
1259 dev_err(sport->port.dev, "Cannot prepare cyclic DMA\n"); in lpuart_start_rx_dma()
1260 return -EFAULT; in lpuart_start_rx_dma()
1263 sport->dma_rx_desc->callback = lpuart_dma_rx_complete; in lpuart_start_rx_dma()
1264 sport->dma_rx_desc->callback_param = sport; in lpuart_start_rx_dma()
1265 sport->dma_rx_cookie = dmaengine_submit(sport->dma_rx_desc); in lpuart_start_rx_dma()
1269 unsigned long temp = lpuart32_read(&sport->port, UARTBAUD); in lpuart_start_rx_dma()
1271 lpuart32_write(&sport->port, temp | UARTBAUD_RDMAE, UARTBAUD); in lpuart_start_rx_dma()
1273 writeb(readb(sport->port.membase + UARTCR5) | UARTCR5_RDMAS, in lpuart_start_rx_dma()
1274 sport->port.membase + UARTCR5); in lpuart_start_rx_dma()
1284 struct dma_chan *chan = sport->dma_rx_chan; in lpuart_dma_rx_free()
1287 del_timer_sync(&sport->lpuart_timer); in lpuart_dma_rx_free()
1288 dma_unmap_sg(chan->device->dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE); in lpuart_dma_rx_free()
1289 kfree(sport->rx_ring.buf); in lpuart_dma_rx_free()
1290 sport->rx_ring.tail = 0; in lpuart_dma_rx_free()
1291 sport->rx_ring.head = 0; in lpuart_dma_rx_free()
1292 sport->dma_rx_desc = NULL; in lpuart_dma_rx_free()
1293 sport->dma_rx_cookie = -EINVAL; in lpuart_dma_rx_free()
1302 u8 modem = readb(sport->port.membase + UARTMODEM) & in lpuart_config_rs485()
1304 writeb(modem, sport->port.membase + UARTMODEM); in lpuart_config_rs485()
1307 rs485->delay_rts_before_send = 0; in lpuart_config_rs485()
1308 rs485->delay_rts_after_send = 0; in lpuart_config_rs485()
1309 rs485->flags &= ~SER_RS485_RX_DURING_TX; in lpuart_config_rs485()
1311 if (rs485->flags & SER_RS485_ENABLED) { in lpuart_config_rs485()
1312 /* Enable auto RS-485 RTS mode */ in lpuart_config_rs485()
1320 if (!(rs485->flags & (SER_RS485_RTS_ON_SEND | in lpuart_config_rs485()
1322 rs485->flags |= SER_RS485_RTS_ON_SEND; in lpuart_config_rs485()
1324 if (rs485->flags & SER_RS485_RTS_ON_SEND && in lpuart_config_rs485()
1325 rs485->flags & SER_RS485_RTS_AFTER_SEND) in lpuart_config_rs485()
1326 rs485->flags &= ~SER_RS485_RTS_AFTER_SEND; in lpuart_config_rs485()
1334 if (rs485->flags & SER_RS485_RTS_ON_SEND) in lpuart_config_rs485()
1336 else if (rs485->flags & SER_RS485_RTS_AFTER_SEND) in lpuart_config_rs485()
1341 sport->port.rs485 = *rs485; in lpuart_config_rs485()
1343 writeb(modem, sport->port.membase + UARTMODEM); in lpuart_config_rs485()
1353 unsigned long modem = lpuart32_read(&sport->port, UARTMODIR) in lpuart32_config_rs485()
1355 lpuart32_write(&sport->port, modem, UARTMODIR); in lpuart32_config_rs485()
1358 rs485->delay_rts_before_send = 0; in lpuart32_config_rs485()
1359 rs485->delay_rts_after_send = 0; in lpuart32_config_rs485()
1360 rs485->flags &= ~SER_RS485_RX_DURING_TX; in lpuart32_config_rs485()
1362 if (rs485->flags & SER_RS485_ENABLED) { in lpuart32_config_rs485()
1363 /* Enable auto RS-485 RTS mode */ in lpuart32_config_rs485()
1371 if (!(rs485->flags & (SER_RS485_RTS_ON_SEND | in lpuart32_config_rs485()
1373 rs485->flags |= SER_RS485_RTS_ON_SEND; in lpuart32_config_rs485()
1375 if (rs485->flags & SER_RS485_RTS_ON_SEND && in lpuart32_config_rs485()
1376 rs485->flags & SER_RS485_RTS_AFTER_SEND) in lpuart32_config_rs485()
1377 rs485->flags &= ~SER_RS485_RTS_AFTER_SEND; in lpuart32_config_rs485()
1385 if (rs485->flags & SER_RS485_RTS_ON_SEND) in lpuart32_config_rs485()
1387 else if (rs485->flags & SER_RS485_RTS_AFTER_SEND) in lpuart32_config_rs485()
1392 sport->port.rs485 = *rs485; in lpuart32_config_rs485()
1394 lpuart32_write(&sport->port, modem, UARTMODIR); in lpuart32_config_rs485()
1403 reg = readb(port->membase + UARTMODEM); in lpuart_get_mctrl()
1425 if (!(sport->port.rs485.flags & SER_RS485_ENABLED)) { in lpuart_set_mctrl()
1426 temp = readb(sport->port.membase + UARTMODEM) & in lpuart_set_mctrl()
1435 writeb(temp, port->membase + UARTMODEM); in lpuart_set_mctrl()
1448 temp = readb(port->membase + UARTCR2) & ~UARTCR2_SBK; in lpuart_break_ctl()
1453 writeb(temp, port->membase + UARTCR2); in lpuart_break_ctl()
1482 /* Disable the TXINV to turn off break and re-enable transmitter. */ in lpuart32_break_ctl()
1495 cr2 = readb(sport->port.membase + UARTCR2); in lpuart_setup_watermark()
1499 writeb(cr2, sport->port.membase + UARTCR2); in lpuart_setup_watermark()
1501 val = readb(sport->port.membase + UARTPFIFO); in lpuart_setup_watermark()
1503 sport->port.membase + UARTPFIFO); in lpuart_setup_watermark()
1507 sport->port.membase + UARTCFIFO); in lpuart_setup_watermark()
1510 if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) { in lpuart_setup_watermark()
1511 readb(sport->port.membase + UARTDR); in lpuart_setup_watermark()
1512 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO); in lpuart_setup_watermark()
1515 writeb(0, sport->port.membase + UARTTWFIFO); in lpuart_setup_watermark()
1516 writeb(1, sport->port.membase + UARTRWFIFO); in lpuart_setup_watermark()
1519 writeb(cr2_saved, sport->port.membase + UARTCR2); in lpuart_setup_watermark()
1528 cr2 = readb(sport->port.membase + UARTCR2); in lpuart_setup_watermark_enable()
1530 writeb(cr2, sport->port.membase + UARTCR2); in lpuart_setup_watermark_enable()
1538 ctrl = lpuart32_read(&sport->port, UARTCTRL); in lpuart32_setup_watermark()
1542 lpuart32_write(&sport->port, ctrl, UARTCTRL); in lpuart32_setup_watermark()
1545 val = lpuart32_read(&sport->port, UARTFIFO); in lpuart32_setup_watermark()
1548 lpuart32_write(&sport->port, val, UARTFIFO); in lpuart32_setup_watermark()
1552 lpuart32_write(&sport->port, val, UARTWATER); in lpuart32_setup_watermark()
1555 lpuart32_write(&sport->port, ctrl_saved, UARTCTRL); in lpuart32_setup_watermark()
1564 temp = lpuart32_read(&sport->port, UARTCTRL); in lpuart32_setup_watermark_enable()
1566 lpuart32_write(&sport->port, temp, UARTCTRL); in lpuart32_setup_watermark_enable()
1571 timer_setup(&sport->lpuart_timer, lpuart_timer_func, 0); in rx_dma_timer_init()
1572 sport->lpuart_timer.expires = jiffies + sport->dma_rx_timeout; in rx_dma_timer_init()
1573 add_timer(&sport->lpuart_timer); in rx_dma_timer_init()
1578 sport->dma_tx_chan = dma_request_chan(sport->port.dev, "tx"); in lpuart_request_dma()
1579 if (IS_ERR(sport->dma_tx_chan)) { in lpuart_request_dma()
1580 dev_dbg_once(sport->port.dev, in lpuart_request_dma()
1582 PTR_ERR(sport->dma_tx_chan)); in lpuart_request_dma()
1583 sport->dma_tx_chan = NULL; in lpuart_request_dma()
1586 sport->dma_rx_chan = dma_request_chan(sport->port.dev, "rx"); in lpuart_request_dma()
1587 if (IS_ERR(sport->dma_rx_chan)) { in lpuart_request_dma()
1588 dev_dbg_once(sport->port.dev, in lpuart_request_dma()
1590 PTR_ERR(sport->dma_rx_chan)); in lpuart_request_dma()
1591 sport->dma_rx_chan = NULL; in lpuart_request_dma()
1600 if (uart_console(&sport->port)) in lpuart_tx_dma_startup()
1603 if (!sport->dma_tx_chan) in lpuart_tx_dma_startup()
1606 ret = lpuart_dma_tx_request(&sport->port); in lpuart_tx_dma_startup()
1610 init_waitqueue_head(&sport->dma_wait); in lpuart_tx_dma_startup()
1611 sport->lpuart_dma_tx_use = true; in lpuart_tx_dma_startup()
1613 uartbaud = lpuart32_read(&sport->port, UARTBAUD); in lpuart_tx_dma_startup()
1614 lpuart32_write(&sport->port, in lpuart_tx_dma_startup()
1617 writeb(readb(sport->port.membase + UARTCR5) | in lpuart_tx_dma_startup()
1618 UARTCR5_TDMAS, sport->port.membase + UARTCR5); in lpuart_tx_dma_startup()
1624 sport->lpuart_dma_tx_use = false; in lpuart_tx_dma_startup()
1632 if (uart_console(&sport->port)) in lpuart_rx_dma_startup()
1635 if (!sport->dma_rx_chan) in lpuart_rx_dma_startup()
1643 sport->dma_rx_timeout = msecs_to_jiffies(DMA_RX_TIMEOUT); in lpuart_rx_dma_startup()
1644 if (!sport->dma_rx_timeout) in lpuart_rx_dma_startup()
1645 sport->dma_rx_timeout = 1; in lpuart_rx_dma_startup()
1647 sport->lpuart_dma_rx_use = true; in lpuart_rx_dma_startup()
1650 if (sport->port.has_sysrq && !lpuart_is_32(sport)) { in lpuart_rx_dma_startup()
1651 cr3 = readb(sport->port.membase + UARTCR3); in lpuart_rx_dma_startup()
1653 writeb(cr3, sport->port.membase + UARTCR3); in lpuart_rx_dma_startup()
1659 sport->lpuart_dma_rx_use = false; in lpuart_rx_dma_startup()
1669 temp = readb(sport->port.membase + UARTPFIFO); in lpuart_startup()
1671 sport->txfifo_size = UARTFIFO_DEPTH((temp >> UARTPFIFO_TXSIZE_OFF) & in lpuart_startup()
1673 sport->port.fifosize = sport->txfifo_size; in lpuart_startup()
1675 sport->rxfifo_size = UARTFIFO_DEPTH((temp >> UARTPFIFO_RXSIZE_OFF) & in lpuart_startup()
1680 spin_lock_irqsave(&sport->port.lock, flags); in lpuart_startup()
1687 spin_unlock_irqrestore(&sport->port.lock, flags); in lpuart_startup()
1696 if (sport->lpuart_dma_rx_use) { in lpuart32_configure()
1698 temp = lpuart32_read(&sport->port, UARTWATER); in lpuart32_configure()
1700 lpuart32_write(&sport->port, temp, UARTWATER); in lpuart32_configure()
1702 temp = lpuart32_read(&sport->port, UARTCTRL); in lpuart32_configure()
1703 if (!sport->lpuart_dma_rx_use) in lpuart32_configure()
1705 if (!sport->lpuart_dma_tx_use) in lpuart32_configure()
1707 lpuart32_write(&sport->port, temp, UARTCTRL); in lpuart32_configure()
1717 temp = lpuart32_read(&sport->port, UARTFIFO); in lpuart32_startup()
1719 sport->txfifo_size = UARTFIFO_DEPTH((temp >> UARTFIFO_TXSIZE_OFF) & in lpuart32_startup()
1721 sport->port.fifosize = sport->txfifo_size; in lpuart32_startup()
1723 sport->rxfifo_size = UARTFIFO_DEPTH((temp >> UARTFIFO_RXSIZE_OFF) & in lpuart32_startup()
1732 sport->rxfifo_size = 16; in lpuart32_startup()
1733 sport->txfifo_size = 16; in lpuart32_startup()
1734 sport->port.fifosize = sport->txfifo_size; in lpuart32_startup()
1739 spin_lock_irqsave(&sport->port.lock, flags); in lpuart32_startup()
1748 spin_unlock_irqrestore(&sport->port.lock, flags); in lpuart32_startup()
1754 if (sport->lpuart_dma_rx_use) { in lpuart_dma_shutdown()
1755 lpuart_dma_rx_free(&sport->port); in lpuart_dma_shutdown()
1756 sport->lpuart_dma_rx_use = false; in lpuart_dma_shutdown()
1759 if (sport->lpuart_dma_tx_use) { in lpuart_dma_shutdown()
1760 if (wait_event_interruptible(sport->dma_wait, in lpuart_dma_shutdown()
1761 !sport->dma_tx_in_progress) != false) { in lpuart_dma_shutdown()
1762 sport->dma_tx_in_progress = false; in lpuart_dma_shutdown()
1763 dmaengine_terminate_all(sport->dma_tx_chan); in lpuart_dma_shutdown()
1765 sport->lpuart_dma_tx_use = false; in lpuart_dma_shutdown()
1768 if (sport->dma_tx_chan) in lpuart_dma_shutdown()
1769 dma_release_channel(sport->dma_tx_chan); in lpuart_dma_shutdown()
1770 if (sport->dma_rx_chan) in lpuart_dma_shutdown()
1771 dma_release_channel(sport->dma_rx_chan); in lpuart_dma_shutdown()
1780 spin_lock_irqsave(&port->lock, flags); in lpuart_shutdown()
1783 temp = readb(port->membase + UARTCR2); in lpuart_shutdown()
1786 writeb(temp, port->membase + UARTCR2); in lpuart_shutdown()
1788 spin_unlock_irqrestore(&port->lock, flags); in lpuart_shutdown()
1800 spin_lock_irqsave(&port->lock, flags); in lpuart32_shutdown()
1808 spin_unlock_irqrestore(&port->lock, flags); in lpuart32_shutdown()
1821 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; in lpuart_set_termios()
1824 cr1 = old_cr1 = readb(sport->port.membase + UARTCR1); in lpuart_set_termios()
1825 old_cr2 = readb(sport->port.membase + UARTCR2); in lpuart_set_termios()
1826 cr3 = readb(sport->port.membase + UARTCR3); in lpuart_set_termios()
1827 cr4 = readb(sport->port.membase + UARTCR4); in lpuart_set_termios()
1828 bdh = readb(sport->port.membase + UARTBDH); in lpuart_set_termios()
1829 modem = readb(sport->port.membase + UARTMODEM); in lpuart_set_termios()
1833 * - (7,e/o,1) in lpuart_set_termios()
1834 * - (8,n,1) in lpuart_set_termios()
1835 * - (8,m/s,1) in lpuart_set_termios()
1836 * - (8,e/o,1) in lpuart_set_termios()
1838 while ((termios->c_cflag & CSIZE) != CS8 && in lpuart_set_termios()
1839 (termios->c_cflag & CSIZE) != CS7) { in lpuart_set_termios()
1840 termios->c_cflag &= ~CSIZE; in lpuart_set_termios()
1841 termios->c_cflag |= old_csize; in lpuart_set_termios()
1845 if ((termios->c_cflag & CSIZE) == CS8 || in lpuart_set_termios()
1846 (termios->c_cflag & CSIZE) == CS7) in lpuart_set_termios()
1849 if (termios->c_cflag & CMSPAR) { in lpuart_set_termios()
1850 if ((termios->c_cflag & CSIZE) != CS8) { in lpuart_set_termios()
1851 termios->c_cflag &= ~CSIZE; in lpuart_set_termios()
1852 termios->c_cflag |= CS8; in lpuart_set_termios()
1858 * When auto RS-485 RTS mode is enabled, in lpuart_set_termios()
1861 if (sport->port.rs485.flags & SER_RS485_ENABLED) in lpuart_set_termios()
1862 termios->c_cflag &= ~CRTSCTS; in lpuart_set_termios()
1864 if (termios->c_cflag & CRTSCTS) in lpuart_set_termios()
1869 termios->c_cflag &= ~CSTOPB; in lpuart_set_termios()
1871 /* parity must be enabled when CS7 to match 8-bits format */ in lpuart_set_termios()
1872 if ((termios->c_cflag & CSIZE) == CS7) in lpuart_set_termios()
1873 termios->c_cflag |= PARENB; in lpuart_set_termios()
1875 if (termios->c_cflag & PARENB) { in lpuart_set_termios()
1876 if (termios->c_cflag & CMSPAR) { in lpuart_set_termios()
1878 if (termios->c_cflag & PARODD) in lpuart_set_termios()
1884 if ((termios->c_cflag & CSIZE) == CS8) in lpuart_set_termios()
1886 if (termios->c_cflag & PARODD) in lpuart_set_termios()
1896 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16); in lpuart_set_termios()
1902 * Since timer function acqures sport->port.lock, need to stop before in lpuart_set_termios()
1905 if (old && sport->lpuart_dma_rx_use) in lpuart_set_termios()
1906 lpuart_dma_rx_free(&sport->port); in lpuart_set_termios()
1908 spin_lock_irqsave(&sport->port.lock, flags); in lpuart_set_termios()
1910 sport->port.read_status_mask = 0; in lpuart_set_termios()
1911 if (termios->c_iflag & INPCK) in lpuart_set_termios()
1912 sport->port.read_status_mask |= UARTSR1_FE | UARTSR1_PE; in lpuart_set_termios()
1913 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) in lpuart_set_termios()
1914 sport->port.read_status_mask |= UARTSR1_FE; in lpuart_set_termios()
1917 sport->port.ignore_status_mask = 0; in lpuart_set_termios()
1918 if (termios->c_iflag & IGNPAR) in lpuart_set_termios()
1919 sport->port.ignore_status_mask |= UARTSR1_PE; in lpuart_set_termios()
1920 if (termios->c_iflag & IGNBRK) { in lpuart_set_termios()
1921 sport->port.ignore_status_mask |= UARTSR1_FE; in lpuart_set_termios()
1926 if (termios->c_iflag & IGNPAR) in lpuart_set_termios()
1927 sport->port.ignore_status_mask |= UARTSR1_OR; in lpuart_set_termios()
1930 /* update the per-port timeout */ in lpuart_set_termios()
1931 uart_update_timeout(port, termios->c_cflag, baud); in lpuart_set_termios()
1934 lpuart_wait_bit_set(&sport->port, UARTSR1, UARTSR1_TC); in lpuart_set_termios()
1938 sport->port.membase + UARTCR2); in lpuart_set_termios()
1940 sbr = sport->port.uartclk / (16 * baud); in lpuart_set_termios()
1941 brfa = ((sport->port.uartclk - (16 * sbr * baud)) * 2) / baud; in lpuart_set_termios()
1946 writeb(cr4 | brfa, sport->port.membase + UARTCR4); in lpuart_set_termios()
1947 writeb(bdh, sport->port.membase + UARTBDH); in lpuart_set_termios()
1948 writeb(sbr & 0xFF, sport->port.membase + UARTBDL); in lpuart_set_termios()
1949 writeb(cr3, sport->port.membase + UARTCR3); in lpuart_set_termios()
1950 writeb(cr1, sport->port.membase + UARTCR1); in lpuart_set_termios()
1951 writeb(modem, sport->port.membase + UARTMODEM); in lpuart_set_termios()
1954 writeb(old_cr2, sport->port.membase + UARTCR2); in lpuart_set_termios()
1956 if (old && sport->lpuart_dma_rx_use) { in lpuart_set_termios()
1960 sport->lpuart_dma_rx_use = false; in lpuart_set_termios()
1963 spin_unlock_irqrestore(&sport->port.lock, flags); in lpuart_set_termios()
1971 u32 clk = port->uartclk; in __lpuart32_serial_setbrg()
1974 * The idea is to use the best OSR (over-sampling rate) possible. in __lpuart32_serial_setbrg()
1975 * Note, OSR is typically hard-set to 16 in other LPUART instantiations. in __lpuart32_serial_setbrg()
1996 tmp_diff = clk / (tmp_osr * tmp_sbr) - baudrate; in __lpuart32_serial_setbrg()
2000 if (tmp_diff > (baudrate - tmp)) { in __lpuart32_serial_setbrg()
2001 tmp_diff = baudrate - tmp; in __lpuart32_serial_setbrg()
2020 dev_warn(port->dev, in __lpuart32_serial_setbrg()
2029 tmp |= ((osr-1) & UARTBAUD_OSR_MASK) << UARTBAUD_OSR_SHIFT; in __lpuart32_serial_setbrg()
2045 __lpuart32_serial_setbrg(&sport->port, baudrate, in lpuart32_serial_setbrg()
2046 sport->lpuart_dma_rx_use, in lpuart32_serial_setbrg()
2047 sport->lpuart_dma_tx_use); in lpuart32_serial_setbrg()
2059 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; in lpuart32_set_termios()
2061 ctrl = old_ctrl = lpuart32_read(&sport->port, UARTCTRL); in lpuart32_set_termios()
2062 modem = lpuart32_read(&sport->port, UARTMODIR); in lpuart32_set_termios()
2066 * - (7,e/o,1) in lpuart32_set_termios()
2067 * - (8,n,1) in lpuart32_set_termios()
2068 * - (8,m/s,1) in lpuart32_set_termios()
2069 * - (8,e/o,1) in lpuart32_set_termios()
2071 while ((termios->c_cflag & CSIZE) != CS8 && in lpuart32_set_termios()
2072 (termios->c_cflag & CSIZE) != CS7) { in lpuart32_set_termios()
2073 termios->c_cflag &= ~CSIZE; in lpuart32_set_termios()
2074 termios->c_cflag |= old_csize; in lpuart32_set_termios()
2078 if ((termios->c_cflag & CSIZE) == CS8 || in lpuart32_set_termios()
2079 (termios->c_cflag & CSIZE) == CS7) in lpuart32_set_termios()
2082 if (termios->c_cflag & CMSPAR) { in lpuart32_set_termios()
2083 if ((termios->c_cflag & CSIZE) != CS8) { in lpuart32_set_termios()
2084 termios->c_cflag &= ~CSIZE; in lpuart32_set_termios()
2085 termios->c_cflag |= CS8; in lpuart32_set_termios()
2091 * When auto RS-485 RTS mode is enabled, in lpuart32_set_termios()
2094 if (sport->port.rs485.flags & SER_RS485_ENABLED) in lpuart32_set_termios()
2095 termios->c_cflag &= ~CRTSCTS; in lpuart32_set_termios()
2097 if (termios->c_cflag & CRTSCTS) { in lpuart32_set_termios()
2100 termios->c_cflag &= ~CRTSCTS; in lpuart32_set_termios()
2104 if (termios->c_cflag & CSTOPB) in lpuart32_set_termios()
2105 termios->c_cflag &= ~CSTOPB; in lpuart32_set_termios()
2107 /* parity must be enabled when CS7 to match 8-bits format */ in lpuart32_set_termios()
2108 if ((termios->c_cflag & CSIZE) == CS7) in lpuart32_set_termios()
2109 termios->c_cflag |= PARENB; in lpuart32_set_termios()
2111 if ((termios->c_cflag & PARENB)) { in lpuart32_set_termios()
2112 if (termios->c_cflag & CMSPAR) { in lpuart32_set_termios()
2117 if ((termios->c_cflag & CSIZE) == CS8) in lpuart32_set_termios()
2119 if (termios->c_cflag & PARODD) in lpuart32_set_termios()
2129 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 4); in lpuart32_set_termios()
2135 * Since timer function acqures sport->port.lock, need to stop before in lpuart32_set_termios()
2138 if (old && sport->lpuart_dma_rx_use) in lpuart32_set_termios()
2139 lpuart_dma_rx_free(&sport->port); in lpuart32_set_termios()
2141 spin_lock_irqsave(&sport->port.lock, flags); in lpuart32_set_termios()
2143 sport->port.read_status_mask = 0; in lpuart32_set_termios()
2144 if (termios->c_iflag & INPCK) in lpuart32_set_termios()
2145 sport->port.read_status_mask |= UARTSTAT_FE | UARTSTAT_PE; in lpuart32_set_termios()
2146 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) in lpuart32_set_termios()
2147 sport->port.read_status_mask |= UARTSTAT_FE; in lpuart32_set_termios()
2150 sport->port.ignore_status_mask = 0; in lpuart32_set_termios()
2151 if (termios->c_iflag & IGNPAR) in lpuart32_set_termios()
2152 sport->port.ignore_status_mask |= UARTSTAT_PE; in lpuart32_set_termios()
2153 if (termios->c_iflag & IGNBRK) { in lpuart32_set_termios()
2154 sport->port.ignore_status_mask |= UARTSTAT_FE; in lpuart32_set_termios()
2159 if (termios->c_iflag & IGNPAR) in lpuart32_set_termios()
2160 sport->port.ignore_status_mask |= UARTSTAT_OR; in lpuart32_set_termios()
2163 /* update the per-port timeout */ in lpuart32_set_termios()
2164 uart_update_timeout(port, termios->c_cflag, baud); in lpuart32_set_termios()
2172 lpuart32_write(&sport->port, 0, UARTMODIR); in lpuart32_set_termios()
2173 lpuart32_wait_bit_set(&sport->port, UARTSTAT, UARTSTAT_TC); in lpuart32_set_termios()
2177 lpuart32_write(&sport->port, old_ctrl & ~(UARTCTRL_TE | UARTCTRL_RE), in lpuart32_set_termios()
2181 lpuart32_write(&sport->port, modem, UARTMODIR); in lpuart32_set_termios()
2182 lpuart32_write(&sport->port, ctrl, UARTCTRL); in lpuart32_set_termios()
2185 if (old && sport->lpuart_dma_rx_use) { in lpuart32_set_termios()
2189 sport->lpuart_dma_rx_use = false; in lpuart32_set_termios()
2192 spin_unlock_irqrestore(&sport->port.lock, flags); in lpuart32_set_termios()
2214 port->type = PORT_LPUART; in lpuart_config_port()
2221 if (ser->type != PORT_UNKNOWN && ser->type != PORT_LPUART) in lpuart_verify_port()
2222 ret = -EINVAL; in lpuart_verify_port()
2223 if (port->irq != ser->irq) in lpuart_verify_port()
2224 ret = -EINVAL; in lpuart_verify_port()
2225 if (ser->io_type != UPIO_MEM) in lpuart_verify_port()
2226 ret = -EINVAL; in lpuart_verify_port()
2227 if (port->uartclk / 16 != ser->baud_base) in lpuart_verify_port()
2228 ret = -EINVAL; in lpuart_verify_port()
2229 if (port->iobase != ser->port) in lpuart_verify_port()
2230 ret = -EINVAL; in lpuart_verify_port()
2231 if (ser->hub6 != 0) in lpuart_verify_port()
2232 ret = -EINVAL; in lpuart_verify_port()
2290 writeb(ch, port->membase + UARTDR); in lpuart_console_putchar()
2302 struct lpuart_port *sport = lpuart_ports[co->index]; in lpuart_console_write()
2307 if (sport->port.sysrq || oops_in_progress) in lpuart_console_write()
2308 locked = spin_trylock_irqsave(&sport->port.lock, flags); in lpuart_console_write()
2310 spin_lock_irqsave(&sport->port.lock, flags); in lpuart_console_write()
2313 cr2 = old_cr2 = readb(sport->port.membase + UARTCR2); in lpuart_console_write()
2316 writeb(cr2, sport->port.membase + UARTCR2); in lpuart_console_write()
2318 uart_console_write(&sport->port, s, count, lpuart_console_putchar); in lpuart_console_write()
2321 lpuart_wait_bit_set(&sport->port, UARTSR1, UARTSR1_TC); in lpuart_console_write()
2323 writeb(old_cr2, sport->port.membase + UARTCR2); in lpuart_console_write()
2326 spin_unlock_irqrestore(&sport->port.lock, flags); in lpuart_console_write()
2332 struct lpuart_port *sport = lpuart_ports[co->index]; in lpuart32_console_write()
2337 if (sport->port.sysrq || oops_in_progress) in lpuart32_console_write()
2338 locked = spin_trylock_irqsave(&sport->port.lock, flags); in lpuart32_console_write()
2340 spin_lock_irqsave(&sport->port.lock, flags); in lpuart32_console_write()
2343 cr = old_cr = lpuart32_read(&sport->port, UARTCTRL); in lpuart32_console_write()
2346 lpuart32_write(&sport->port, cr, UARTCTRL); in lpuart32_console_write()
2348 uart_console_write(&sport->port, s, count, lpuart32_console_putchar); in lpuart32_console_write()
2351 lpuart32_wait_bit_set(&sport->port, UARTSTAT, UARTSTAT_TC); in lpuart32_console_write()
2353 lpuart32_write(&sport->port, old_cr, UARTCTRL); in lpuart32_console_write()
2356 spin_unlock_irqrestore(&sport->port.lock, flags); in lpuart32_console_write()
2370 cr = readb(sport->port.membase + UARTCR2); in lpuart_console_get_options()
2377 cr = readb(sport->port.membase + UARTCR1); in lpuart_console_get_options()
2392 bdh = readb(sport->port.membase + UARTBDH); in lpuart_console_get_options()
2394 bdl = readb(sport->port.membase + UARTBDL); in lpuart_console_get_options()
2398 brfa = readb(sport->port.membase + UARTCR4); in lpuart_console_get_options()
2408 dev_info(sport->port.dev, "Serial: Console lpuart rounded baud rate" in lpuart_console_get_options()
2419 cr = lpuart32_read(&sport->port, UARTCTRL); in lpuart32_console_get_options()
2426 cr = lpuart32_read(&sport->port, UARTCTRL); in lpuart32_console_get_options()
2441 bd = lpuart32_read(&sport->port, UARTBAUD); in lpuart32_console_get_options()
2454 dev_info(sport->port.dev, "Serial: Console lpuart rounded baud rate" in lpuart32_console_get_options()
2471 if (co->index == -1 || co->index >= ARRAY_SIZE(lpuart_ports)) in lpuart_console_setup()
2472 co->index = 0; in lpuart_console_setup()
2474 sport = lpuart_ports[co->index]; in lpuart_console_setup()
2476 return -ENODEV; in lpuart_console_setup()
2491 return uart_set_options(&sport->port, co, baud, parity, bits, flow); in lpuart_console_setup()
2501 .index = -1,
2511 .index = -1,
2517 struct earlycon_device *dev = con->data; in lpuart_early_write()
2519 uart_console_write(&dev->port, s, n, lpuart_console_putchar); in lpuart_early_write()
2524 struct earlycon_device *dev = con->data; in lpuart32_early_write()
2526 uart_console_write(&dev->port, s, n, lpuart32_console_putchar); in lpuart32_early_write()
2532 if (!device->port.membase) in lpuart_early_console_setup()
2533 return -ENODEV; in lpuart_early_console_setup()
2535 device->con->write = lpuart_early_write; in lpuart_early_console_setup()
2542 if (!device->port.membase) in lpuart32_early_console_setup()
2543 return -ENODEV; in lpuart32_early_console_setup()
2545 if (device->port.iotype != UPIO_MEM32) in lpuart32_early_console_setup()
2546 device->port.iotype = UPIO_MEM32BE; in lpuart32_early_console_setup()
2548 device->con->write = lpuart32_early_write; in lpuart32_early_console_setup()
2557 if (!device->port.membase) in ls1028a_early_console_setup()
2558 return -ENODEV; in ls1028a_early_console_setup()
2560 device->port.iotype = UPIO_MEM32; in ls1028a_early_console_setup()
2561 device->con->write = lpuart32_early_write; in ls1028a_early_console_setup()
2564 if (device->port.uartclk && device->baud) in ls1028a_early_console_setup()
2565 __lpuart32_serial_setbrg(&device->port, device->baud, in ls1028a_early_console_setup()
2569 cr = lpuart32_read(&device->port, UARTCTRL); in ls1028a_early_console_setup()
2571 lpuart32_write(&device->port, cr, UARTCTRL); in ls1028a_early_console_setup()
2579 if (!device->port.membase) in lpuart32_imx_early_console_setup()
2580 return -ENODEV; in lpuart32_imx_early_console_setup()
2582 device->port.iotype = UPIO_MEM32; in lpuart32_imx_early_console_setup()
2583 device->port.membase += IMX_REG_OFF; in lpuart32_imx_early_console_setup()
2584 device->con->write = lpuart32_early_write; in lpuart32_imx_early_console_setup()
2588 OF_EARLYCON_DECLARE(lpuart, "fsl,vf610-lpuart", lpuart_early_console_setup);
2589 OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1021a-lpuart", lpuart32_early_console_setup);
2590 OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1028a-lpuart", ls1028a_early_console_setup);
2591 OF_EARLYCON_DECLARE(lpuart32, "fsl,imx7ulp-lpuart", lpuart32_imx_early_console_setup);
2592 OF_EARLYCON_DECLARE(lpuart32, "fsl,imx8ulp-lpuart", lpuart32_imx_early_console_setup);
2593 OF_EARLYCON_DECLARE(lpuart32, "fsl,imx8qxp-lpuart", lpuart32_imx_early_console_setup);
2615 &pdev->dev); in lpuart_probe()
2616 const struct lpuart_soc_data *sdata = of_id->data; in lpuart_probe()
2617 struct device_node *np = pdev->dev.of_node; in lpuart_probe()
2623 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL); in lpuart_probe()
2625 return -ENOMEM; in lpuart_probe()
2628 sport->port.membase = devm_ioremap_resource(&pdev->dev, res); in lpuart_probe()
2629 if (IS_ERR(sport->port.membase)) in lpuart_probe()
2630 return PTR_ERR(sport->port.membase); in lpuart_probe()
2632 sport->port.membase += sdata->reg_off; in lpuart_probe()
2633 sport->port.mapbase = res->start + sdata->reg_off; in lpuart_probe()
2634 sport->port.dev = &pdev->dev; in lpuart_probe()
2635 sport->port.type = PORT_LPUART; in lpuart_probe()
2636 sport->devtype = sdata->devtype; in lpuart_probe()
2640 sport->port.irq = ret; in lpuart_probe()
2641 sport->port.iotype = sdata->iotype; in lpuart_probe()
2643 sport->port.ops = &lpuart32_pops; in lpuart_probe()
2645 sport->port.ops = &lpuart_pops; in lpuart_probe()
2646 sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_FSL_LPUART_CONSOLE); in lpuart_probe()
2647 sport->port.flags = UPF_BOOT_AUTOCONF; in lpuart_probe()
2650 sport->port.rs485_config = lpuart32_config_rs485; in lpuart_probe()
2652 sport->port.rs485_config = lpuart_config_rs485; in lpuart_probe()
2654 sport->ipg_clk = devm_clk_get(&pdev->dev, "ipg"); in lpuart_probe()
2655 if (IS_ERR(sport->ipg_clk)) { in lpuart_probe()
2656 ret = PTR_ERR(sport->ipg_clk); in lpuart_probe()
2657 dev_err(&pdev->dev, "failed to get uart ipg clk: %d\n", ret); in lpuart_probe()
2661 sport->baud_clk = NULL; in lpuart_probe()
2663 sport->baud_clk = devm_clk_get(&pdev->dev, "baud"); in lpuart_probe()
2664 if (IS_ERR(sport->baud_clk)) { in lpuart_probe()
2665 ret = PTR_ERR(sport->baud_clk); in lpuart_probe()
2666 dev_err(&pdev->dev, "failed to get uart baud clk: %d\n", ret); in lpuart_probe()
2673 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret); in lpuart_probe()
2677 dev_err(&pdev->dev, "serial%d out of range\n", ret); in lpuart_probe()
2678 return -EINVAL; in lpuart_probe()
2680 sport->port.line = ret; in lpuart_probe()
2685 sport->port.uartclk = lpuart_get_baud_clk_rate(sport); in lpuart_probe()
2687 lpuart_ports[sport->port.line] = sport; in lpuart_probe()
2689 platform_set_drvdata(pdev, &sport->port); in lpuart_probe()
2699 ret = uart_get_rs485_mode(&sport->port); in lpuart_probe()
2703 if (sport->port.rs485.flags & SER_RS485_RX_DURING_TX) in lpuart_probe()
2704 dev_err(&pdev->dev, "driver doesn't support RX during TX\n"); in lpuart_probe()
2706 if (sport->port.rs485.delay_rts_before_send || in lpuart_probe()
2707 sport->port.rs485.delay_rts_after_send) in lpuart_probe()
2708 dev_err(&pdev->dev, "driver doesn't support RTS delays\n"); in lpuart_probe()
2710 ret = uart_add_one_port(&lpuart_reg, &sport->port); in lpuart_probe()
2714 ret = devm_request_irq(&pdev->dev, sport->port.irq, handler, 0, in lpuart_probe()
2722 uart_remove_one_port(&lpuart_reg, &sport->port); in lpuart_probe()
2733 uart_remove_one_port(&lpuart_reg, &sport->port); in lpuart_remove()
2737 if (sport->dma_tx_chan) in lpuart_remove()
2738 dma_release_channel(sport->dma_tx_chan); in lpuart_remove()
2740 if (sport->dma_rx_chan) in lpuart_remove()
2741 dma_release_channel(sport->dma_rx_chan); in lpuart_remove()
2754 temp = lpuart32_read(&sport->port, UARTCTRL); in lpuart_suspend()
2756 lpuart32_write(&sport->port, temp, UARTCTRL); in lpuart_suspend()
2759 temp = readb(sport->port.membase + UARTCR2); in lpuart_suspend()
2761 writeb(temp, sport->port.membase + UARTCR2); in lpuart_suspend()
2764 uart_suspend_port(&lpuart_reg, &sport->port); in lpuart_suspend()
2767 irq_wake = irqd_is_wakeup_set(irq_get_irq_data(sport->port.irq)); in lpuart_suspend()
2769 if (sport->lpuart_dma_rx_use) { in lpuart_suspend()
2771 * EDMA driver during suspend will forcefully release any in lpuart_suspend()
2772 * non-idle DMA channels. If port wakeup is enabled or if port in lpuart_suspend()
2778 lpuart_dma_rx_free(&sport->port); in lpuart_suspend()
2783 temp = lpuart32_read(&sport->port, UARTBAUD); in lpuart_suspend()
2784 lpuart32_write(&sport->port, temp & ~UARTBAUD_RDMAE, in lpuart_suspend()
2787 writeb(readb(sport->port.membase + UARTCR5) & in lpuart_suspend()
2788 ~UARTCR5_RDMAS, sport->port.membase + UARTCR5); in lpuart_suspend()
2792 if (sport->lpuart_dma_tx_use) { in lpuart_suspend()
2793 sport->dma_tx_in_progress = false; in lpuart_suspend()
2794 dmaengine_terminate_all(sport->dma_tx_chan); in lpuart_suspend()
2797 if (sport->port.suspended && !irq_wake) in lpuart_suspend()
2806 bool irq_wake = irqd_is_wakeup_set(irq_get_irq_data(sport->port.irq)); in lpuart_resume()
2808 if (sport->port.suspended && !irq_wake) in lpuart_resume()
2816 if (sport->lpuart_dma_rx_use) { in lpuart_resume()
2821 sport->lpuart_dma_rx_use = false; in lpuart_resume()
2830 uart_resume_port(&lpuart_reg, &sport->port); in lpuart_resume()
2841 .name = "fsl-lpuart",