Lines Matching +full:clock +full:- +full:generator
1 /* SPDX-License-Identifier: GPL-2.0 */
25 * of "escc" node (ie. ch-a or ch-b)
74 if (uap->flags & PMACZILOG_FLAG_IS_CHANNEL_A) in pmz_get_port_A()
76 return uap->mate; in pmz_get_port_A()
88 writeb(reg, port->control_reg); in read_zsreg()
89 return readb(port->control_reg); in read_zsreg()
95 writeb(reg, port->control_reg); in write_zsreg()
96 writeb(value, port->control_reg); in write_zsreg()
101 return readb(port->data_reg); in read_zsdata()
106 writeb(data, port->data_reg); in write_zsdata()
111 (void)readb(port->control_reg); in zssync()
118 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
120 #define ZS_CLOCK 3686400 /* Z8530 RTxC input clock rate */
206 #define X1CLK 0x0 /* x1 clock mode */
207 #define X16CLK 0x40 /* x16 clock mode */
208 #define X32CLK 0x80 /* x32 clock mode */
209 #define X64CLK 0xC0 /* x64 clock mode */
216 #define SDLC_CRC 0x4 /* SDLC/CRC-16 */
226 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
228 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
258 /* Write Register 11 (Clock Mode control) */
260 #define TRxCTC 1 /* TRxC = Transmit clock */
261 #define TRxCBR 2 /* TRxC = BR Generator Output */
264 #define TCRTxCP 0 /* Transmit clock = RTxC pin */
265 #define TCTRxCP 8 /* Transmit clock = TRxC pin */
266 #define TCBR 0x10 /* Transmit clock = BR Generator output */
267 #define TCDPLL 0x18 /* Transmit clock = DPLL output */
268 #define RCRTxCP 0 /* Receive clock = RTxC pin */
269 #define RCTRxCP 0x20 /* Receive clock = TRxC pin */
270 #define RCBR 0x40 /* Receive clock = BR Generator output */
271 #define RCDPLL 0x60 /* Receive clock = DPLL output */
274 /* Write Register 12 (lower byte of baud rate generator time constant) */
276 /* Write Register 13 (upper byte of baud rate generator time constant) */
279 #define BRENAB 1 /* Baud rate generator enable */
280 #define BRSRC 2 /* Baud rate generator source */
285 #define RMC 0x40 /* Reset missing clock */
287 #define SSBR 0x80 /* Set DPLL source = BR generator */
293 #define EN85C30 1 /* Enable some 85c30-enhanced registers */
330 /* Read Register 2 (channel b only) - Interrupt vector */
355 #define CLK1MIS 0x80 /* One clock missing */
357 /* Read Register 12 (lower byte of baud rate generator constant) */
359 /* Read Register 13 (upper byte of baud rate generator constant) */
371 #define ZS_IS_CONS(UP) ((UP)->flags & PMACZILOG_FLAG_IS_CONS)
372 #define ZS_IS_KGDB(UP) ((UP)->flags & PMACZILOG_FLAG_IS_KGDB)
373 #define ZS_IS_CHANNEL_A(UP) ((UP)->flags & PMACZILOG_FLAG_IS_CHANNEL_A)
374 #define ZS_REGS_HELD(UP) ((UP)->flags & PMACZILOG_FLAG_REGS_HELD)
375 #define ZS_TX_STOPPED(UP) ((UP)->flags & PMACZILOG_FLAG_TX_STOPPED)
376 #define ZS_TX_ACTIVE(UP) ((UP)->flags & PMACZILOG_FLAG_TX_ACTIVE)
377 #define ZS_WANTS_MODEM_STATUS(UP) ((UP)->flags & PMACZILOG_FLAG_MODEM_STATUS)
378 #define ZS_IS_IRDA(UP) ((UP)->flags & PMACZILOG_FLAG_IS_IRDA)
379 #define ZS_IS_INTMODEM(UP) ((UP)->flags & PMACZILOG_FLAG_IS_INTMODEM)
380 #define ZS_HAS_DMA(UP) ((UP)->flags & PMACZILOG_FLAG_HAS_DMA)
381 #define ZS_IS_OPEN(UP) ((UP)->flags & PMACZILOG_FLAG_IS_OPEN)
382 #define ZS_IS_EXTCLK(UP) ((UP)->flags & PMACZILOG_FLAG_IS_EXTCLK)