Lines Matching +full:stm32 +full:- +full:uart
1 // SPDX-License-Identifier: GPL-2.0
5 * Authors: Maxime Coquelin <mcoquelin.stm32@gmail.com>
8 * Inspired by st-asc.c from STMicroelectronics (c)
14 #include <linux/dma-direction.h>
16 #include <linux/dma-mapping.h>
35 #include "stm32-usart.h"
49 val = readl_relaxed(port->membase + reg); in stm32_usart_set_bits()
51 writel_relaxed(val, port->membase + reg); in stm32_usart_set_bits()
58 val = readl_relaxed(port->membase + reg); in stm32_usart_clr_bits()
60 writel_relaxed(val, port->membase + reg); in stm32_usart_clr_bits()
104 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_config_rs485()
105 const struct stm32_usart_config *cfg = &stm32_port->info->cfg; in stm32_usart_config_rs485()
109 stm32_usart_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); in stm32_usart_config_rs485()
111 port->rs485 = *rs485conf; in stm32_usart_config_rs485()
113 rs485conf->flags |= SER_RS485_RX_DURING_TX; in stm32_usart_config_rs485()
115 if (rs485conf->flags & SER_RS485_ENABLED) { in stm32_usart_config_rs485()
116 cr1 = readl_relaxed(port->membase + ofs->cr1); in stm32_usart_config_rs485()
117 cr3 = readl_relaxed(port->membase + ofs->cr3); in stm32_usart_config_rs485()
118 usartdiv = readl_relaxed(port->membase + ofs->brr); in stm32_usart_config_rs485()
126 baud = DIV_ROUND_CLOSEST(port->uartclk, usartdiv); in stm32_usart_config_rs485()
128 rs485conf->delay_rts_before_send, in stm32_usart_config_rs485()
129 rs485conf->delay_rts_after_send, in stm32_usart_config_rs485()
132 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) { in stm32_usart_config_rs485()
134 rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND; in stm32_usart_config_rs485()
137 rs485conf->flags |= SER_RS485_RTS_AFTER_SEND; in stm32_usart_config_rs485()
140 writel_relaxed(cr3, port->membase + ofs->cr3); in stm32_usart_config_rs485()
141 writel_relaxed(cr1, port->membase + ofs->cr1); in stm32_usart_config_rs485()
143 stm32_usart_clr_bits(port, ofs->cr3, in stm32_usart_config_rs485()
145 stm32_usart_clr_bits(port, ofs->cr1, in stm32_usart_config_rs485()
149 stm32_usart_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); in stm32_usart_config_rs485()
157 struct serial_rs485 *rs485conf = &port->rs485; in stm32_usart_init_rs485()
159 rs485conf->flags = 0; in stm32_usart_init_rs485()
160 rs485conf->delay_rts_before_send = 0; in stm32_usart_init_rs485()
161 rs485conf->delay_rts_after_send = 0; in stm32_usart_init_rs485()
163 if (!pdev->dev.of_node) in stm32_usart_init_rs485()
164 return -ENODEV; in stm32_usart_init_rs485()
173 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_pending_rx()
177 *sr = readl_relaxed(port->membase + ofs->isr); in stm32_usart_pending_rx()
179 if (threaded && stm32_port->rx_ch) { in stm32_usart_pending_rx()
180 status = dmaengine_tx_status(stm32_port->rx_ch, in stm32_usart_pending_rx()
181 stm32_port->rx_ch->cookie, in stm32_usart_pending_rx()
197 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_get_char()
200 if (stm32_port->rx_ch) { in stm32_usart_get_char()
201 c = stm32_port->rx_buf[RX_BUF_L - (*last_res)--]; in stm32_usart_get_char()
205 c = readl_relaxed(port->membase + ofs->rdr); in stm32_usart_get_char()
207 c &= stm32_port->rdr_mask; in stm32_usart_get_char()
215 struct tty_port *tport = &port->state->port; in stm32_usart_receive_chars()
217 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_receive_chars()
222 spin_lock(&port->lock); in stm32_usart_receive_chars()
224 while (stm32_usart_pending_rx(port, &sr, &stm32_port->last_res, in stm32_usart_receive_chars()
238 * cleared by the sequence [read SR - read DR]. in stm32_usart_receive_chars()
240 if ((sr & USART_SR_ERR_MASK) && ofs->icr != UNDEF_REG) in stm32_usart_receive_chars()
242 port->membase + ofs->icr); in stm32_usart_receive_chars()
244 c = stm32_usart_get_char(port, &sr, &stm32_port->last_res); in stm32_usart_receive_chars()
245 port->icount.rx++; in stm32_usart_receive_chars()
248 port->icount.overrun++; in stm32_usart_receive_chars()
250 port->icount.parity++; in stm32_usart_receive_chars()
254 port->icount.brk++; in stm32_usart_receive_chars()
258 port->icount.frame++; in stm32_usart_receive_chars()
262 sr &= port->read_status_mask; in stm32_usart_receive_chars()
279 spin_unlock(&port->lock); in stm32_usart_receive_chars()
288 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs; in stm32_usart_tx_dma_complete()
291 dmaengine_terminate_async(stm32port->tx_ch); in stm32_usart_tx_dma_complete()
292 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT); in stm32_usart_tx_dma_complete()
293 stm32port->tx_dma_busy = false; in stm32_usart_tx_dma_complete()
296 spin_lock_irqsave(&port->lock, flags); in stm32_usart_tx_dma_complete()
298 spin_unlock_irqrestore(&port->lock, flags); in stm32_usart_tx_dma_complete()
304 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_tx_interrupt_enable()
310 if (stm32_port->fifoen) in stm32_usart_tx_interrupt_enable()
311 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_TXFTIE); in stm32_usart_tx_interrupt_enable()
313 stm32_usart_set_bits(port, ofs->cr1, USART_CR1_TXEIE); in stm32_usart_tx_interrupt_enable()
319 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_tx_interrupt_disable()
321 if (stm32_port->fifoen) in stm32_usart_tx_interrupt_disable()
322 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_TXFTIE); in stm32_usart_tx_interrupt_disable()
324 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_TXEIE); in stm32_usart_tx_interrupt_disable()
330 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_transmit_chars_pio()
331 struct circ_buf *xmit = &port->state->xmit; in stm32_usart_transmit_chars_pio()
333 if (stm32_port->tx_dma_busy) { in stm32_usart_transmit_chars_pio()
334 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT); in stm32_usart_transmit_chars_pio()
335 stm32_port->tx_dma_busy = false; in stm32_usart_transmit_chars_pio()
340 if (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE)) in stm32_usart_transmit_chars_pio()
342 writel_relaxed(xmit->buf[xmit->tail], port->membase + ofs->tdr); in stm32_usart_transmit_chars_pio()
343 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); in stm32_usart_transmit_chars_pio()
344 port->icount.tx++; in stm32_usart_transmit_chars_pio()
357 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs; in stm32_usart_transmit_chars_dma()
358 struct circ_buf *xmit = &port->state->xmit; in stm32_usart_transmit_chars_dma()
362 if (stm32port->tx_dma_busy) in stm32_usart_transmit_chars_dma()
365 stm32port->tx_dma_busy = true; in stm32_usart_transmit_chars_dma()
372 if (xmit->tail < xmit->head) { in stm32_usart_transmit_chars_dma()
373 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], count); in stm32_usart_transmit_chars_dma()
375 size_t one = UART_XMIT_SIZE - xmit->tail; in stm32_usart_transmit_chars_dma()
380 two = count - one; in stm32_usart_transmit_chars_dma()
382 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], one); in stm32_usart_transmit_chars_dma()
384 memcpy(&stm32port->tx_buf[one], &xmit->buf[0], two); in stm32_usart_transmit_chars_dma()
387 desc = dmaengine_prep_slave_single(stm32port->tx_ch, in stm32_usart_transmit_chars_dma()
388 stm32port->tx_dma_buf, in stm32_usart_transmit_chars_dma()
396 desc->callback = stm32_usart_tx_dma_complete; in stm32_usart_transmit_chars_dma()
397 desc->callback_param = port; in stm32_usart_transmit_chars_dma()
402 dmaengine_terminate_async(stm32port->tx_ch); in stm32_usart_transmit_chars_dma()
407 dma_async_issue_pending(stm32port->tx_ch); in stm32_usart_transmit_chars_dma()
409 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_DMAT); in stm32_usart_transmit_chars_dma()
411 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1); in stm32_usart_transmit_chars_dma()
412 port->icount.tx += count; in stm32_usart_transmit_chars_dma()
416 for (i = count; i > 0; i--) in stm32_usart_transmit_chars_dma()
423 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_transmit_chars()
424 struct circ_buf *xmit = &port->state->xmit; in stm32_usart_transmit_chars()
428 if (port->x_char) { in stm32_usart_transmit_chars()
429 if (stm32_port->tx_dma_busy) in stm32_usart_transmit_chars()
430 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT); in stm32_usart_transmit_chars()
434 readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr, in stm32_usart_transmit_chars()
439 dev_warn(port->dev, "1 character may be erased\n"); in stm32_usart_transmit_chars()
441 writel_relaxed(port->x_char, port->membase + ofs->tdr); in stm32_usart_transmit_chars()
442 port->x_char = 0; in stm32_usart_transmit_chars()
443 port->icount.tx++; in stm32_usart_transmit_chars()
444 if (stm32_port->tx_dma_busy) in stm32_usart_transmit_chars()
445 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_DMAT); in stm32_usart_transmit_chars()
454 if (ofs->icr == UNDEF_REG) in stm32_usart_transmit_chars()
455 stm32_usart_clr_bits(port, ofs->isr, USART_SR_TC); in stm32_usart_transmit_chars()
457 writel_relaxed(USART_ICR_TCCF, port->membase + ofs->icr); in stm32_usart_transmit_chars()
459 if (stm32_port->tx_ch) in stm32_usart_transmit_chars()
474 struct tty_port *tport = &port->state->port; in stm32_usart_interrupt()
476 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_interrupt()
479 sr = readl_relaxed(port->membase + ofs->isr); in stm32_usart_interrupt()
481 if ((sr & USART_SR_RTOF) && ofs->icr != UNDEF_REG) in stm32_usart_interrupt()
483 port->membase + ofs->icr); in stm32_usart_interrupt()
485 if ((sr & USART_SR_WUF) && ofs->icr != UNDEF_REG) { in stm32_usart_interrupt()
488 port->membase + ofs->icr); in stm32_usart_interrupt()
489 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_WUFIE); in stm32_usart_interrupt()
490 if (irqd_is_wakeup_set(irq_get_irq_data(port->irq))) in stm32_usart_interrupt()
491 pm_wakeup_event(tport->tty->dev, 0); in stm32_usart_interrupt()
494 if ((sr & USART_SR_RXNE) && !(stm32_port->rx_ch)) in stm32_usart_interrupt()
497 if ((sr & USART_SR_TXE) && !(stm32_port->tx_ch)) { in stm32_usart_interrupt()
498 spin_lock(&port->lock); in stm32_usart_interrupt()
500 spin_unlock(&port->lock); in stm32_usart_interrupt()
503 if (stm32_port->rx_ch) in stm32_usart_interrupt()
514 if (stm32_port->rx_ch) in stm32_usart_threaded_interrupt()
523 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_tx_empty()
525 if (readl_relaxed(port->membase + ofs->isr) & USART_SR_TC) in stm32_usart_tx_empty()
534 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_set_mctrl()
536 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS)) in stm32_usart_set_mctrl()
537 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_RTSE); in stm32_usart_set_mctrl()
539 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_RTSE); in stm32_usart_set_mctrl()
541 mctrl_gpio_set(stm32_port->gpios, mctrl); in stm32_usart_set_mctrl()
552 return mctrl_gpio_get(stm32_port->gpios, &ret); in stm32_usart_get_mctrl()
557 mctrl_gpio_enable_ms(to_stm32_port(port)->gpios); in stm32_usart_enable_ms()
562 mctrl_gpio_disable_ms(to_stm32_port(port)->gpios); in stm32_usart_disable_ms()
569 struct serial_rs485 *rs485conf = &port->rs485; in stm32_usart_stop_tx()
573 if (rs485conf->flags & SER_RS485_ENABLED) { in stm32_usart_stop_tx()
574 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) { in stm32_usart_stop_tx()
575 mctrl_gpio_set(stm32_port->gpios, in stm32_usart_stop_tx()
576 stm32_port->port.mctrl & ~TIOCM_RTS); in stm32_usart_stop_tx()
578 mctrl_gpio_set(stm32_port->gpios, in stm32_usart_stop_tx()
579 stm32_port->port.mctrl | TIOCM_RTS); in stm32_usart_stop_tx()
588 struct serial_rs485 *rs485conf = &port->rs485; in stm32_usart_start_tx()
589 struct circ_buf *xmit = &port->state->xmit; in stm32_usart_start_tx()
591 if (uart_circ_empty(xmit) && !port->x_char) in stm32_usart_start_tx()
594 if (rs485conf->flags & SER_RS485_ENABLED) { in stm32_usart_start_tx()
595 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) { in stm32_usart_start_tx()
596 mctrl_gpio_set(stm32_port->gpios, in stm32_usart_start_tx()
597 stm32_port->port.mctrl | TIOCM_RTS); in stm32_usart_start_tx()
599 mctrl_gpio_set(stm32_port->gpios, in stm32_usart_start_tx()
600 stm32_port->port.mctrl & ~TIOCM_RTS); in stm32_usart_start_tx()
611 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_throttle()
614 spin_lock_irqsave(&port->lock, flags); in stm32_usart_throttle()
615 stm32_usart_clr_bits(port, ofs->cr1, stm32_port->cr1_irq); in stm32_usart_throttle()
616 if (stm32_port->cr3_irq) in stm32_usart_throttle()
617 stm32_usart_clr_bits(port, ofs->cr3, stm32_port->cr3_irq); in stm32_usart_throttle()
619 spin_unlock_irqrestore(&port->lock, flags); in stm32_usart_throttle()
626 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_unthrottle()
629 spin_lock_irqsave(&port->lock, flags); in stm32_usart_unthrottle()
630 stm32_usart_set_bits(port, ofs->cr1, stm32_port->cr1_irq); in stm32_usart_unthrottle()
631 if (stm32_port->cr3_irq) in stm32_usart_unthrottle()
632 stm32_usart_set_bits(port, ofs->cr3, stm32_port->cr3_irq); in stm32_usart_unthrottle()
634 spin_unlock_irqrestore(&port->lock, flags); in stm32_usart_unthrottle()
641 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_stop_rx()
643 stm32_usart_clr_bits(port, ofs->cr1, stm32_port->cr1_irq); in stm32_usart_stop_rx()
644 if (stm32_port->cr3_irq) in stm32_usart_stop_rx()
645 stm32_usart_clr_bits(port, ofs->cr3, stm32_port->cr3_irq); in stm32_usart_stop_rx()
648 /* Handle breaks - ignored by us */
656 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_startup()
657 const struct stm32_usart_config *cfg = &stm32_port->info->cfg; in stm32_usart_startup()
658 const char *name = to_platform_device(port->dev)->name; in stm32_usart_startup()
662 ret = request_threaded_irq(port->irq, stm32_usart_interrupt, in stm32_usart_startup()
670 if (ofs->rqr != UNDEF_REG) in stm32_usart_startup()
671 writel_relaxed(USART_RQR_RXFRQ, port->membase + ofs->rqr); in stm32_usart_startup()
674 val = stm32_port->cr1_irq | USART_CR1_RE | BIT(cfg->uart_enable_bit); in stm32_usart_startup()
675 stm32_usart_set_bits(port, ofs->cr1, val); in stm32_usart_startup()
683 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_shutdown()
684 const struct stm32_usart_config *cfg = &stm32_port->info->cfg; in stm32_usart_shutdown()
692 val |= stm32_port->cr1_irq | USART_CR1_RE; in stm32_usart_shutdown()
693 val |= BIT(cfg->uart_enable_bit); in stm32_usart_shutdown()
694 if (stm32_port->fifoen) in stm32_usart_shutdown()
697 ret = readl_relaxed_poll_timeout(port->membase + ofs->isr, in stm32_usart_shutdown()
702 dev_err(port->dev, "transmission complete not set\n"); in stm32_usart_shutdown()
705 if (ofs->rqr != UNDEF_REG) in stm32_usart_shutdown()
707 port->membase + ofs->rqr); in stm32_usart_shutdown()
709 stm32_usart_clr_bits(port, ofs->cr1, val); in stm32_usart_shutdown()
711 free_irq(port->irq, port); in stm32_usart_shutdown()
718 tcflag_t cflag = termios->c_cflag; in stm32_usart_get_databits()
749 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_set_termios()
750 const struct stm32_usart_config *cfg = &stm32_port->info->cfg; in stm32_usart_set_termios()
751 struct serial_rs485 *rs485conf = &port->rs485; in stm32_usart_set_termios()
754 tcflag_t cflag = termios->c_cflag; in stm32_usart_set_termios()
759 if (!stm32_port->hw_flow_control) in stm32_usart_set_termios()
762 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 8); in stm32_usart_set_termios()
764 spin_lock_irqsave(&port->lock, flags); in stm32_usart_set_termios()
766 ret = readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr, in stm32_usart_set_termios()
773 dev_err(port->dev, "Transmission is not complete\n"); in stm32_usart_set_termios()
776 writel_relaxed(0, port->membase + ofs->cr1); in stm32_usart_set_termios()
779 if (ofs->rqr != UNDEF_REG) in stm32_usart_set_termios()
781 port->membase + ofs->rqr); in stm32_usart_set_termios()
784 if (stm32_port->fifoen) in stm32_usart_set_termios()
789 cr3 = readl_relaxed(port->membase + ofs->cr3); in stm32_usart_set_termios()
791 if (stm32_port->fifoen) { in stm32_usart_set_termios()
801 stm32_port->rdr_mask = (BIT(bits) - 1); in stm32_usart_set_termios()
817 } else if ((bits == 7) && cfg->has_7bits_data) { in stm32_usart_set_termios()
820 dev_dbg(port->dev, "Unsupported data bits config: %u bits\n" in stm32_usart_set_termios()
824 termios->c_cflag = cflag; in stm32_usart_set_termios()
832 if (ofs->rtor != UNDEF_REG && (stm32_port->rx_ch || in stm32_usart_set_termios()
833 stm32_port->fifoen)) { in stm32_usart_set_termios()
840 stm32_port->cr1_irq = USART_CR1_RTOIE; in stm32_usart_set_termios()
841 writel_relaxed(bits, port->membase + ofs->rtor); in stm32_usart_set_termios()
844 if (!stm32_port->rx_ch) in stm32_usart_set_termios()
845 stm32_port->cr3_irq = USART_CR3_RXFTIE; in stm32_usart_set_termios()
848 cr1 |= stm32_port->cr1_irq; in stm32_usart_set_termios()
849 cr3 |= stm32_port->cr3_irq; in stm32_usart_set_termios()
854 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS); in stm32_usart_set_termios()
856 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; in stm32_usart_set_termios()
860 usartdiv = DIV_ROUND_CLOSEST(port->uartclk, baud); in stm32_usart_set_termios()
871 stm32_usart_set_bits(port, ofs->cr1, USART_CR1_OVER8); in stm32_usart_set_termios()
875 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_OVER8); in stm32_usart_set_termios()
880 writel_relaxed(mantissa | fraction, port->membase + ofs->brr); in stm32_usart_set_termios()
884 port->read_status_mask = USART_SR_ORE; in stm32_usart_set_termios()
885 if (termios->c_iflag & INPCK) in stm32_usart_set_termios()
886 port->read_status_mask |= USART_SR_PE | USART_SR_FE; in stm32_usart_set_termios()
887 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) in stm32_usart_set_termios()
888 port->read_status_mask |= USART_SR_FE; in stm32_usart_set_termios()
891 port->ignore_status_mask = 0; in stm32_usart_set_termios()
892 if (termios->c_iflag & IGNPAR) in stm32_usart_set_termios()
893 port->ignore_status_mask = USART_SR_PE | USART_SR_FE; in stm32_usart_set_termios()
894 if (termios->c_iflag & IGNBRK) { in stm32_usart_set_termios()
895 port->ignore_status_mask |= USART_SR_FE; in stm32_usart_set_termios()
900 if (termios->c_iflag & IGNPAR) in stm32_usart_set_termios()
901 port->ignore_status_mask |= USART_SR_ORE; in stm32_usart_set_termios()
905 if ((termios->c_cflag & CREAD) == 0) in stm32_usart_set_termios()
906 port->ignore_status_mask |= USART_SR_DUMMY_RX; in stm32_usart_set_termios()
908 if (stm32_port->rx_ch) in stm32_usart_set_termios()
911 if (rs485conf->flags & SER_RS485_ENABLED) { in stm32_usart_set_termios()
913 rs485conf->delay_rts_before_send, in stm32_usart_set_termios()
914 rs485conf->delay_rts_after_send, in stm32_usart_set_termios()
916 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) { in stm32_usart_set_termios()
918 rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND; in stm32_usart_set_termios()
921 rs485conf->flags |= SER_RS485_RTS_AFTER_SEND; in stm32_usart_set_termios()
930 if (stm32_port->wakeirq > 0) { in stm32_usart_set_termios()
935 writel_relaxed(cr3, port->membase + ofs->cr3); in stm32_usart_set_termios()
936 writel_relaxed(cr2, port->membase + ofs->cr2); in stm32_usart_set_termios()
937 writel_relaxed(cr1, port->membase + ofs->cr1); in stm32_usart_set_termios()
939 stm32_usart_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); in stm32_usart_set_termios()
940 spin_unlock_irqrestore(&port->lock, flags); in stm32_usart_set_termios()
943 if (UART_ENABLE_MS(port, termios->c_cflag)) in stm32_usart_set_termios()
951 return (port->type == PORT_STM32) ? DRIVER_NAME : NULL; in stm32_usart_type()
966 port->type = PORT_STM32; in stm32_usart_config_port()
973 return -EINVAL; in stm32_usart_verify_port()
981 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs; in stm32_usart_pm()
982 const struct stm32_usart_config *cfg = &stm32port->info->cfg; in stm32_usart_pm()
987 pm_runtime_get_sync(port->dev); in stm32_usart_pm()
990 spin_lock_irqsave(&port->lock, flags); in stm32_usart_pm()
991 stm32_usart_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); in stm32_usart_pm()
992 spin_unlock_irqrestore(&port->lock, flags); in stm32_usart_pm()
993 pm_runtime_put_sync(port->dev); in stm32_usart_pm()
1023 struct uart_port *port = &stm32port->port; in stm32_usart_init_port()
1029 return ret ? : -ENODEV; in stm32_usart_init_port()
1031 port->iotype = UPIO_MEM; in stm32_usart_init_port()
1032 port->flags = UPF_BOOT_AUTOCONF; in stm32_usart_init_port()
1033 port->ops = &stm32_uart_ops; in stm32_usart_init_port()
1034 port->dev = &pdev->dev; in stm32_usart_init_port()
1035 port->fifosize = stm32port->info->cfg.fifosize; in stm32_usart_init_port()
1036 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_STM32_CONSOLE); in stm32_usart_init_port()
1037 port->irq = ret; in stm32_usart_init_port()
1038 port->rs485_config = stm32_usart_config_rs485; in stm32_usart_init_port()
1044 if (stm32port->info->cfg.has_wakeup) { in stm32_usart_init_port()
1045 stm32port->wakeirq = platform_get_irq_optional(pdev, 1); in stm32_usart_init_port()
1046 if (stm32port->wakeirq <= 0 && stm32port->wakeirq != -ENXIO) in stm32_usart_init_port()
1047 return stm32port->wakeirq ? : -ENODEV; in stm32_usart_init_port()
1050 stm32port->fifoen = stm32port->info->cfg.has_fifo; in stm32_usart_init_port()
1053 port->membase = devm_ioremap_resource(&pdev->dev, res); in stm32_usart_init_port()
1054 if (IS_ERR(port->membase)) in stm32_usart_init_port()
1055 return PTR_ERR(port->membase); in stm32_usart_init_port()
1056 port->mapbase = res->start; in stm32_usart_init_port()
1058 spin_lock_init(&port->lock); in stm32_usart_init_port()
1060 stm32port->clk = devm_clk_get(&pdev->dev, NULL); in stm32_usart_init_port()
1061 if (IS_ERR(stm32port->clk)) in stm32_usart_init_port()
1062 return PTR_ERR(stm32port->clk); in stm32_usart_init_port()
1065 ret = clk_prepare_enable(stm32port->clk); in stm32_usart_init_port()
1069 stm32port->port.uartclk = clk_get_rate(stm32port->clk); in stm32_usart_init_port()
1070 if (!stm32port->port.uartclk) { in stm32_usart_init_port()
1071 ret = -EINVAL; in stm32_usart_init_port()
1075 stm32port->gpios = mctrl_gpio_init(&stm32port->port, 0); in stm32_usart_init_port()
1076 if (IS_ERR(stm32port->gpios)) { in stm32_usart_init_port()
1077 ret = PTR_ERR(stm32port->gpios); in stm32_usart_init_port()
1081 /* Both CTS/RTS gpios and "st,hw-flow-ctrl" should not be specified */ in stm32_usart_init_port()
1082 if (stm32port->hw_flow_control) { in stm32_usart_init_port()
1083 if (mctrl_gpio_to_gpiod(stm32port->gpios, UART_GPIO_CTS) || in stm32_usart_init_port()
1084 mctrl_gpio_to_gpiod(stm32port->gpios, UART_GPIO_RTS)) { in stm32_usart_init_port()
1085 dev_err(&pdev->dev, "Conflicting RTS/CTS config\n"); in stm32_usart_init_port()
1086 ret = -EINVAL; in stm32_usart_init_port()
1094 clk_disable_unprepare(stm32port->clk); in stm32_usart_init_port()
1101 struct device_node *np = pdev->dev.of_node; in stm32_usart_of_get_port()
1109 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", id); in stm32_usart_of_get_port()
1117 of_property_read_bool (np, "st,hw-flow-ctrl") /*deprecated*/ || in stm32_usart_of_get_port()
1118 of_property_read_bool (np, "uart-has-rtscts"); in stm32_usart_of_get_port()
1128 { .compatible = "st,stm32-uart", .data = &stm32f4_info},
1129 { .compatible = "st,stm32f7-uart", .data = &stm32f7_info},
1130 { .compatible = "st,stm32h7-uart", .data = &stm32h7_info},
1140 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs; in stm32_usart_of_dma_rx_probe()
1141 struct uart_port *port = &stm32port->port; in stm32_usart_of_dma_rx_probe()
1142 struct device *dev = &pdev->dev; in stm32_usart_of_dma_rx_probe()
1152 return -ENODEV; in stm32_usart_of_dma_rx_probe()
1155 stm32port->rx_ch = dma_request_slave_channel(dev, "rx"); in stm32_usart_of_dma_rx_probe()
1156 if (!stm32port->rx_ch) { in stm32_usart_of_dma_rx_probe()
1158 return -ENODEV; in stm32_usart_of_dma_rx_probe()
1160 stm32port->rx_buf = dma_alloc_coherent(&pdev->dev, RX_BUF_L, in stm32_usart_of_dma_rx_probe()
1161 &stm32port->rx_dma_buf, in stm32_usart_of_dma_rx_probe()
1163 if (!stm32port->rx_buf) { in stm32_usart_of_dma_rx_probe()
1164 ret = -ENOMEM; in stm32_usart_of_dma_rx_probe()
1170 config.src_addr = port->mapbase + ofs->rdr; in stm32_usart_of_dma_rx_probe()
1173 ret = dmaengine_slave_config(stm32port->rx_ch, &config); in stm32_usart_of_dma_rx_probe()
1176 ret = -ENODEV; in stm32_usart_of_dma_rx_probe()
1181 desc = dmaengine_prep_dma_cyclic(stm32port->rx_ch, in stm32_usart_of_dma_rx_probe()
1182 stm32port->rx_dma_buf, in stm32_usart_of_dma_rx_probe()
1187 ret = -ENODEV; in stm32_usart_of_dma_rx_probe()
1192 desc->callback = NULL; in stm32_usart_of_dma_rx_probe()
1193 desc->callback_param = NULL; in stm32_usart_of_dma_rx_probe()
1198 dmaengine_terminate_sync(stm32port->rx_ch); in stm32_usart_of_dma_rx_probe()
1203 dma_async_issue_pending(stm32port->rx_ch); in stm32_usart_of_dma_rx_probe()
1208 dma_free_coherent(&pdev->dev, in stm32_usart_of_dma_rx_probe()
1209 RX_BUF_L, stm32port->rx_buf, in stm32_usart_of_dma_rx_probe()
1210 stm32port->rx_dma_buf); in stm32_usart_of_dma_rx_probe()
1213 dma_release_channel(stm32port->rx_ch); in stm32_usart_of_dma_rx_probe()
1214 stm32port->rx_ch = NULL; in stm32_usart_of_dma_rx_probe()
1222 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs; in stm32_usart_of_dma_tx_probe()
1223 struct uart_port *port = &stm32port->port; in stm32_usart_of_dma_tx_probe()
1224 struct device *dev = &pdev->dev; in stm32_usart_of_dma_tx_probe()
1228 stm32port->tx_dma_busy = false; in stm32_usart_of_dma_tx_probe()
1231 stm32port->tx_ch = dma_request_slave_channel(dev, "tx"); in stm32_usart_of_dma_tx_probe()
1232 if (!stm32port->tx_ch) { in stm32_usart_of_dma_tx_probe()
1234 return -ENODEV; in stm32_usart_of_dma_tx_probe()
1236 stm32port->tx_buf = dma_alloc_coherent(&pdev->dev, TX_BUF_L, in stm32_usart_of_dma_tx_probe()
1237 &stm32port->tx_dma_buf, in stm32_usart_of_dma_tx_probe()
1239 if (!stm32port->tx_buf) { in stm32_usart_of_dma_tx_probe()
1240 ret = -ENOMEM; in stm32_usart_of_dma_tx_probe()
1246 config.dst_addr = port->mapbase + ofs->tdr; in stm32_usart_of_dma_tx_probe()
1249 ret = dmaengine_slave_config(stm32port->tx_ch, &config); in stm32_usart_of_dma_tx_probe()
1252 ret = -ENODEV; in stm32_usart_of_dma_tx_probe()
1259 dma_free_coherent(&pdev->dev, in stm32_usart_of_dma_tx_probe()
1260 TX_BUF_L, stm32port->tx_buf, in stm32_usart_of_dma_tx_probe()
1261 stm32port->tx_dma_buf); in stm32_usart_of_dma_tx_probe()
1264 dma_release_channel(stm32port->tx_ch); in stm32_usart_of_dma_tx_probe()
1265 stm32port->tx_ch = NULL; in stm32_usart_of_dma_tx_probe()
1277 return -ENODEV; in stm32_usart_serial_probe()
1279 stm32port->info = of_device_get_match_data(&pdev->dev); in stm32_usart_serial_probe()
1280 if (!stm32port->info) in stm32_usart_serial_probe()
1281 return -EINVAL; in stm32_usart_serial_probe()
1287 if (stm32port->wakeirq > 0) { in stm32_usart_serial_probe()
1288 ret = device_init_wakeup(&pdev->dev, true); in stm32_usart_serial_probe()
1292 ret = dev_pm_set_dedicated_wake_irq(&pdev->dev, in stm32_usart_serial_probe()
1293 stm32port->wakeirq); in stm32_usart_serial_probe()
1297 device_set_wakeup_enable(&pdev->dev, false); in stm32_usart_serial_probe()
1302 dev_info(&pdev->dev, "interrupt mode used for rx (no dma)\n"); in stm32_usart_serial_probe()
1306 dev_info(&pdev->dev, "interrupt mode used for tx (no dma)\n"); in stm32_usart_serial_probe()
1308 platform_set_drvdata(pdev, &stm32port->port); in stm32_usart_serial_probe()
1310 pm_runtime_get_noresume(&pdev->dev); in stm32_usart_serial_probe()
1311 pm_runtime_set_active(&pdev->dev); in stm32_usart_serial_probe()
1312 pm_runtime_enable(&pdev->dev); in stm32_usart_serial_probe()
1314 ret = uart_add_one_port(&stm32_usart_driver, &stm32port->port); in stm32_usart_serial_probe()
1318 pm_runtime_put_sync(&pdev->dev); in stm32_usart_serial_probe()
1323 pm_runtime_disable(&pdev->dev); in stm32_usart_serial_probe()
1324 pm_runtime_set_suspended(&pdev->dev); in stm32_usart_serial_probe()
1325 pm_runtime_put_noidle(&pdev->dev); in stm32_usart_serial_probe()
1327 if (stm32port->rx_ch) { in stm32_usart_serial_probe()
1328 dmaengine_terminate_async(stm32port->rx_ch); in stm32_usart_serial_probe()
1329 dma_release_channel(stm32port->rx_ch); in stm32_usart_serial_probe()
1332 if (stm32port->rx_dma_buf) in stm32_usart_serial_probe()
1333 dma_free_coherent(&pdev->dev, in stm32_usart_serial_probe()
1334 RX_BUF_L, stm32port->rx_buf, in stm32_usart_serial_probe()
1335 stm32port->rx_dma_buf); in stm32_usart_serial_probe()
1337 if (stm32port->tx_ch) { in stm32_usart_serial_probe()
1338 dmaengine_terminate_async(stm32port->tx_ch); in stm32_usart_serial_probe()
1339 dma_release_channel(stm32port->tx_ch); in stm32_usart_serial_probe()
1342 if (stm32port->tx_dma_buf) in stm32_usart_serial_probe()
1343 dma_free_coherent(&pdev->dev, in stm32_usart_serial_probe()
1344 TX_BUF_L, stm32port->tx_buf, in stm32_usart_serial_probe()
1345 stm32port->tx_dma_buf); in stm32_usart_serial_probe()
1347 if (stm32port->wakeirq > 0) in stm32_usart_serial_probe()
1348 dev_pm_clear_wake_irq(&pdev->dev); in stm32_usart_serial_probe()
1351 if (stm32port->wakeirq > 0) in stm32_usart_serial_probe()
1352 device_init_wakeup(&pdev->dev, false); in stm32_usart_serial_probe()
1355 clk_disable_unprepare(stm32port->clk); in stm32_usart_serial_probe()
1364 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_serial_remove()
1367 pm_runtime_get_sync(&pdev->dev); in stm32_usart_serial_remove()
1372 pm_runtime_disable(&pdev->dev); in stm32_usart_serial_remove()
1373 pm_runtime_set_suspended(&pdev->dev); in stm32_usart_serial_remove()
1374 pm_runtime_put_noidle(&pdev->dev); in stm32_usart_serial_remove()
1376 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAR); in stm32_usart_serial_remove()
1378 if (stm32_port->rx_ch) { in stm32_usart_serial_remove()
1379 dmaengine_terminate_async(stm32_port->rx_ch); in stm32_usart_serial_remove()
1380 dma_release_channel(stm32_port->rx_ch); in stm32_usart_serial_remove()
1383 if (stm32_port->rx_dma_buf) in stm32_usart_serial_remove()
1384 dma_free_coherent(&pdev->dev, in stm32_usart_serial_remove()
1385 RX_BUF_L, stm32_port->rx_buf, in stm32_usart_serial_remove()
1386 stm32_port->rx_dma_buf); in stm32_usart_serial_remove()
1388 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT); in stm32_usart_serial_remove()
1390 if (stm32_port->tx_ch) { in stm32_usart_serial_remove()
1391 dmaengine_terminate_async(stm32_port->tx_ch); in stm32_usart_serial_remove()
1392 dma_release_channel(stm32_port->tx_ch); in stm32_usart_serial_remove()
1395 if (stm32_port->tx_dma_buf) in stm32_usart_serial_remove()
1396 dma_free_coherent(&pdev->dev, in stm32_usart_serial_remove()
1397 TX_BUF_L, stm32_port->tx_buf, in stm32_usart_serial_remove()
1398 stm32_port->tx_dma_buf); in stm32_usart_serial_remove()
1400 if (stm32_port->wakeirq > 0) { in stm32_usart_serial_remove()
1401 dev_pm_clear_wake_irq(&pdev->dev); in stm32_usart_serial_remove()
1402 device_init_wakeup(&pdev->dev, false); in stm32_usart_serial_remove()
1405 clk_disable_unprepare(stm32_port->clk); in stm32_usart_serial_remove()
1414 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_console_putchar()
1416 while (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE)) in stm32_usart_console_putchar()
1419 writel_relaxed(ch, port->membase + ofs->tdr); in stm32_usart_console_putchar()
1425 struct uart_port *port = &stm32_ports[co->index].port; in stm32_usart_console_write()
1427 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_console_write()
1428 const struct stm32_usart_config *cfg = &stm32_port->info->cfg; in stm32_usart_console_write()
1434 if (port->sysrq) in stm32_usart_console_write()
1437 locked = spin_trylock(&port->lock); in stm32_usart_console_write()
1439 spin_lock(&port->lock); in stm32_usart_console_write()
1442 old_cr1 = readl_relaxed(port->membase + ofs->cr1); in stm32_usart_console_write()
1444 new_cr1 |= USART_CR1_TE | BIT(cfg->uart_enable_bit); in stm32_usart_console_write()
1445 writel_relaxed(new_cr1, port->membase + ofs->cr1); in stm32_usart_console_write()
1450 writel_relaxed(old_cr1, port->membase + ofs->cr1); in stm32_usart_console_write()
1453 spin_unlock(&port->lock); in stm32_usart_console_write()
1465 if (co->index >= STM32_MAX_PORTS) in stm32_usart_console_setup()
1466 return -ENODEV; in stm32_usart_console_setup()
1468 stm32port = &stm32_ports[co->index]; in stm32_usart_console_setup()
1473 * this to be called during the uart port registration when the in stm32_usart_console_setup()
1476 if (stm32port->port.mapbase == 0 || !stm32port->port.membase) in stm32_usart_console_setup()
1477 return -ENXIO; in stm32_usart_console_setup()
1482 return uart_set_options(&stm32port->port, co, baud, parity, bits, flow); in stm32_usart_console_setup()
1491 .index = -1,
1514 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_serial_en_wakeup()
1516 if (stm32_port->wakeirq <= 0) in stm32_usart_serial_en_wakeup()
1520 * Enable low-power wake-up and wake-up irq if argument is set to in stm32_usart_serial_en_wakeup()
1521 * "enable", disable low-power wake-up and wake-up irq otherwise in stm32_usart_serial_en_wakeup()
1524 stm32_usart_set_bits(port, ofs->cr1, USART_CR1_UESM); in stm32_usart_serial_en_wakeup()
1525 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_WUFIE); in stm32_usart_serial_en_wakeup()
1527 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_UESM); in stm32_usart_serial_en_wakeup()
1528 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_WUFIE); in stm32_usart_serial_en_wakeup()
1577 clk_disable_unprepare(stm32port->clk); in stm32_usart_runtime_suspend()
1588 return clk_prepare_enable(stm32port->clk); in stm32_usart_runtime_resume()
1610 static char banner[] __initdata = "STM32 USART driver initialized"; in stm32_usart_init()
1636 MODULE_DESCRIPTION("STMicroelectronics STM32 serial port driver");