Lines Matching +full:3 +full:x3
1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
16 * 3. The names of the above-listed copyright holders may not be used
61 #define GOTGCTL_VBVALOVAL BIT(3)
85 #define GAHBCFG_HBSTLEN_INCR4 3
119 #define GUSBCFG_PHYIF16 BIT(3)
120 #define GUSBCFG_PHYIF8 (0 << 3)
136 #define GRSTCTL_IN_TKNQ_FLSH BIT(3)
172 #define GINTSTS_SOF BIT(3)
186 #define GRXSTS_PKTSTS_OUTDONE 3
187 #define GRXSTS_PKTSTS_HCHIN_XFER_COMP 3
194 #define GRXSTS_DPID_MASK (0x3 << 15)
222 #define GI2CCTL_I2CDEVADDR_MASK (0x3 << 26)
249 #define GHWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK (0x3 << 24)
251 #define GHWCFG2_NONPERIO_TX_Q_DEPTH_MASK (0x3 << 22)
260 #define GHWCFG2_FS_PHY_TYPE_MASK (0x3 << 8)
265 #define GHWCFG2_FS_PHY_TYPE_SHARED_ULPI 3
266 #define GHWCFG2_HS_PHY_TYPE_MASK (0x3 << 6)
271 #define GHWCFG2_HS_PHY_TYPE_UTMI_ULPI 3
273 #define GHWCFG2_ARCHITECTURE_MASK (0x3 << 3)
274 #define GHWCFG2_ARCHITECTURE_SHIFT 3
283 #define GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE 3
320 #define GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK (0x3 << 14)
351 #define GLPMCFG_COREL1RES_MASK (0x3 << 13)
369 #define GPWRDN_LINESTATE_MASK (0x3 << 19)
386 #define GPWRDN_PWRDNCLMP BIT(3)
398 #define ADPCTL_AR_MASK (0x3 << 27)
412 #define ADPCTL_PRB_PER_MASK (0x3 << 4)
414 #define ADPCTL_PRB_DELTA_MASK (0x3 << 2)
416 #define ADPCTL_PRB_DSCHRG_MASK (0x3 << 0)
454 #define DCFG_PERFRINT_MASK (0x3 << 11)
456 #define DCFG_PERFRINT_LIMIT 0x3
463 #define DCFG_DEVSPD_MASK (0x3 << 0)
468 #define DCFG_DEVSPD_FS48 3
479 #define DCTL_GOUTNAKSTS BIT(3)
489 #define DSTS_ERRATICERR BIT(3)
490 #define DSTS_ENUMSPD_MASK (0x3 << 1)
495 #define DSTS_ENUMSPD_FS48 3
506 #define DIEPMSK_TIMEOUTMSK BIT(3)
516 #define DOEPMSK_SETUPMSK BIT(3)
547 #define D0EPCTL_MPS_MASK (0x3 << 0)
552 #define D0EPCTL_MPS_8 3
568 #define DXEPCTL_EPTYPE_MASK (0x3 << 18)
572 #define DXEPCTL_EPTYPE_INTERRUPT (0x3 << 18)
604 #define DXEPINT_TIMEOUT BIT(3)
605 #define DXEPINT_SETUP BIT(3)
611 #define DIEPTSIZ0_PKTCNT_MASK (0x3 << 19)
613 #define DIEPTSIZ0_PKTCNT_LIMIT 0x3
621 #define DOEPTSIZ0_SUPCNT_MASK (0x3 << 29)
623 #define DOEPTSIZ0_SUPCNT_LIMIT 0x3
631 #define DXEPTSIZ_MC_MASK (0x3 << 29)
633 #define DXEPTSIZ_MC_LIMIT 0x3
653 #define PCGCTL_P2HD_PRT_SPD_MASK (0x3 << 29)
655 #define PCGCTL_P2HD_DEV_ENUM_SPD_MASK (0x3 << 27)
660 #define PCGCTL_MAX_XCVRSELECT_MASK (0x3 << 17)
663 #define PCGCTL_PRT_CLK_SEL_MASK (0x3 << 14)
674 #define PCGCTL_RSTPDWNMODULE BIT(3)
680 #define PCGCCTL1_TIMER (0x3 << 1)
690 #define HCFG_FRLISTEN_MASK (0x3 << 24)
698 #define HCFG_FRLISTEN_64 (3 << 24)
705 #define HCFG_FSLSPCLKSEL_MASK (0x3 << 0)
727 #define TXSTS_QTOP_TOKEN_MASK (0x3 << 25)
740 #define HPRT0_SPD_MASK (0x3 << 17)
748 #define HPRT0_LNSTS_MASK (0x3 << 10)
755 #define HPRT0_ENACHG BIT(3)
766 #define HCCHAR_MULTICNT_MASK (0x3 << 20)
768 #define HCCHAR_EPTYPE_MASK (0x3 << 18)
780 #define HCSPLT_XACTPOS_MASK (0x3 << 14)
785 #define HCSPLT_XACTPOS_ALL 3
804 #define HCINTMSK_STALL BIT(3)
811 #define TSIZ_SC_MC_PID_MASK (0x3 << 29)
816 #define TSIZ_SC_MC_PID_MDATA 3
817 #define TSIZ_SC_MC_PID_SETUP 3
851 #define HOST_DMA_STS_MASK (0x3 << 28)
868 #define DEV_DMA_BUFF_STS_MASK (0x3 << 30)
873 #define DEV_DMA_BUFF_STS_HBUSY 3
874 #define DEV_DMA_STS_MASK (0x3 << 28)
878 #define DEV_DMA_STS_BUFF_ERR 3
884 #define DEV_DMA_ISOC_PID_MASK (0x3 << 23)
889 #define DEV_DMA_ISOC_PID_MDATA 3