Lines Matching +full:io +full:- +full:multiplex
2 * linux/drivers/video/s3fb.c -- Frame buffer device driver for S3 Trio/Virge
4 * Copyright (c) 2006-2007 Ondrej Zajicek <santiago@crfreenet.org>
29 #include <linux/i2c-algo-bit.h>
47 /* ------------------------------------------------------------------------- */
147 /* ------------------------------------------------------------------------- */
157 MODULE_AUTHOR("(c) 2006-2007 Ondrej Zajicek <santiago@crfreenet.org>");
162 MODULE_PARM_DESC(mode_option, "Default video mode ('640x480-8@60', etc)");
164 MODULE_PARM_DESC(mode, "Default video mode ('640x480-8@60', etc) (deprecated)");
166 MODULE_PARM_DESC(mtrr, "Enable write-combining with MTRR (1=enable, 0=disable, default=1)");
172 /* ------------------------------------------------------------------------- */
193 if (s3fb_ddc_needs_mmio(par->chip)) in s3fb_ddc_read()
194 return readb(par->mmio + DDC_MMIO_REG); in s3fb_ddc_read()
196 return vga_rcrt(par->state.vgabase, DDC_REG); in s3fb_ddc_read()
201 if (s3fb_ddc_needs_mmio(par->chip)) in s3fb_ddc_write()
202 writeb(val, par->mmio + DDC_MMIO_REG); in s3fb_ddc_write()
204 vga_wcrt(par->state.vgabase, DDC_REG, val); in s3fb_ddc_write()
249 struct s3fb_info *par = info->par; in s3fb_setup_ddc_bus()
251 strlcpy(par->ddc_adapter.name, info->fix.id, in s3fb_setup_ddc_bus()
252 sizeof(par->ddc_adapter.name)); in s3fb_setup_ddc_bus()
253 par->ddc_adapter.owner = THIS_MODULE; in s3fb_setup_ddc_bus()
254 par->ddc_adapter.class = I2C_CLASS_DDC; in s3fb_setup_ddc_bus()
255 par->ddc_adapter.algo_data = &par->ddc_algo; in s3fb_setup_ddc_bus()
256 par->ddc_adapter.dev.parent = info->device; in s3fb_setup_ddc_bus()
257 par->ddc_algo.setsda = s3fb_ddc_setsda; in s3fb_setup_ddc_bus()
258 par->ddc_algo.setscl = s3fb_ddc_setscl; in s3fb_setup_ddc_bus()
259 par->ddc_algo.getsda = s3fb_ddc_getsda; in s3fb_setup_ddc_bus()
260 par->ddc_algo.getscl = s3fb_ddc_getscl; in s3fb_setup_ddc_bus()
261 par->ddc_algo.udelay = 10; in s3fb_setup_ddc_bus()
262 par->ddc_algo.timeout = 20; in s3fb_setup_ddc_bus()
263 par->ddc_algo.data = par; in s3fb_setup_ddc_bus()
265 i2c_set_adapdata(&par->ddc_adapter, par); in s3fb_setup_ddc_bus()
269 * DDC and extension pins - switch it do DDC in s3fb_setup_ddc_bus()
271 /* vga_wseq(par->state.vgabase, 0x08, 0x06); - not needed, already unlocked */ in s3fb_setup_ddc_bus()
272 if (par->chip == CHIP_357_VIRGE_GX2 || in s3fb_setup_ddc_bus()
273 par->chip == CHIP_359_VIRGE_GX2P || in s3fb_setup_ddc_bus()
274 par->chip == CHIP_260_VIRGE_MX) in s3fb_setup_ddc_bus()
275 svga_wseq_mask(par->state.vgabase, 0x0d, 0x01, 0x03); in s3fb_setup_ddc_bus()
277 svga_wseq_mask(par->state.vgabase, 0x0d, 0x00, 0x03); in s3fb_setup_ddc_bus()
279 svga_wcrt_mask(par->state.vgabase, 0x5c, 0x03, 0x03); in s3fb_setup_ddc_bus()
281 return i2c_bit_add_bus(&par->ddc_adapter); in s3fb_setup_ddc_bus()
286 /* ------------------------------------------------------------------------- */
292 const u8 *font = map->data; in s3fb_settile_fast()
293 u8 __iomem *fb = (u8 __iomem *) info->screen_base; in s3fb_settile_fast()
296 if ((map->width != 8) || (map->height != 16) || in s3fb_settile_fast()
297 (map->depth != 1) || (map->length != 256)) { in s3fb_settile_fast()
299 map->width, map->height, map->depth, map->length); in s3fb_settile_fast()
304 for (i = 0; i < map->height; i++) { in s3fb_settile_fast()
305 for (c = 0; c < map->length; c++) { in s3fb_settile_fast()
306 fb_writeb(font[c * map->height + i], fb + c * 4); in s3fb_settile_fast()
314 struct s3fb_info *par = info->par; in s3fb_tilecursor()
316 svga_tilecursor(par->state.vgabase, info, cursor); in s3fb_tilecursor()
338 /* ------------------------------------------------------------------------- */
340 /* image data is MSB-first, fb structure is MSB-first too */
346 /* s3fb_iplan_imageblit silently assumes that almost everything is 8-pixel aligned */
349 u32 fg = expand_color(image->fg_color); in s3fb_iplan_imageblit()
350 u32 bg = expand_color(image->bg_color); in s3fb_iplan_imageblit()
357 src1 = image->data; in s3fb_iplan_imageblit()
358 dst1 = info->screen_base + (image->dy * info->fix.line_length) in s3fb_iplan_imageblit()
359 + ((image->dx / 8) * 4); in s3fb_iplan_imageblit()
361 for (y = 0; y < image->height; y++) { in s3fb_iplan_imageblit()
364 for (x = 0; x < image->width; x += 8) { in s3fb_iplan_imageblit()
369 src1 += image->width / 8; in s3fb_iplan_imageblit()
370 dst1 += info->fix.line_length; in s3fb_iplan_imageblit()
375 /* s3fb_iplan_fillrect silently assumes that almost everything is 8-pixel aligned */
378 u32 fg = expand_color(rect->color); in s3fb_iplan_fillrect()
383 dst1 = info->screen_base + (rect->dy * info->fix.line_length) in s3fb_iplan_fillrect()
384 + ((rect->dx / 8) * 4); in s3fb_iplan_fillrect()
386 for (y = 0; y < rect->height; y++) { in s3fb_iplan_fillrect()
388 for (x = 0; x < rect->width; x += 8) { in s3fb_iplan_fillrect()
391 dst1 += info->fix.line_length; in s3fb_iplan_fillrect()
396 /* image data is MSB-first, fb structure is high-nibble-in-low-byte-first */
403 /* s3fb_cfb4_imageblit silently assumes that almost everything is 8-pixel aligned */
406 u32 fg = image->fg_color * 0x11111111; in s3fb_cfb4_imageblit()
407 u32 bg = image->bg_color * 0x11111111; in s3fb_cfb4_imageblit()
414 src1 = image->data; in s3fb_cfb4_imageblit()
415 dst1 = info->screen_base + (image->dy * info->fix.line_length) in s3fb_cfb4_imageblit()
416 + ((image->dx / 8) * 4); in s3fb_cfb4_imageblit()
418 for (y = 0; y < image->height; y++) { in s3fb_cfb4_imageblit()
421 for (x = 0; x < image->width; x += 8) { in s3fb_cfb4_imageblit()
426 src1 += image->width / 8; in s3fb_cfb4_imageblit()
427 dst1 += info->fix.line_length; in s3fb_cfb4_imageblit()
433 if ((info->var.bits_per_pixel == 4) && (image->depth == 1) in s3fb_imageblit()
434 && ((image->width % 8) == 0) && ((image->dx % 8) == 0)) { in s3fb_imageblit()
435 if (info->fix.type == FB_TYPE_INTERLEAVED_PLANES) in s3fb_imageblit()
445 if ((info->var.bits_per_pixel == 4) in s3fb_fillrect()
446 && ((rect->width % 8) == 0) && ((rect->dx % 8) == 0) in s3fb_fillrect()
447 && (info->fix.type == FB_TYPE_INTERLEAVED_PLANES)) in s3fb_fillrect()
455 /* ------------------------------------------------------------------------- */
460 struct s3fb_info *par = info->par; in s3_set_pixclock()
465 rv = svga_compute_pll((par->chip == CHIP_365_TRIO3D) ? &s3_trio3d_pll : &s3_pll, in s3_set_pixclock()
466 1000000000 / pixclock, &m, &n, &r, info->node); in s3_set_pixclock()
473 regval = vga_r(par->state.vgabase, VGA_MIS_R); in s3_set_pixclock()
474 vga_w(par->state.vgabase, VGA_MIS_W, regval | VGA_MIS_ENB_PLL_LOAD); in s3_set_pixclock()
477 if (par->chip == CHIP_357_VIRGE_GX2 || in s3_set_pixclock()
478 par->chip == CHIP_359_VIRGE_GX2P || in s3_set_pixclock()
479 par->chip == CHIP_360_TRIO3D_1X || in s3_set_pixclock()
480 par->chip == CHIP_362_TRIO3D_2X || in s3_set_pixclock()
481 par->chip == CHIP_368_TRIO3D_2X || in s3_set_pixclock()
482 par->chip == CHIP_260_VIRGE_MX) { in s3_set_pixclock()
483 vga_wseq(par->state.vgabase, 0x12, (n - 2) | ((r & 3) << 6)); /* n and two bits of r */ in s3_set_pixclock()
484 vga_wseq(par->state.vgabase, 0x29, r >> 2); /* remaining highest bit of r */ in s3_set_pixclock()
486 vga_wseq(par->state.vgabase, 0x12, (n - 2) | (r << 5)); in s3_set_pixclock()
487 vga_wseq(par->state.vgabase, 0x13, m - 2); in s3_set_pixclock()
491 /* Activate clock - write 0, 1, 0 to seq/15 bit 5 */ in s3_set_pixclock()
492 regval = vga_rseq (par->state.vgabase, 0x15); /* | 0x80; */ in s3_set_pixclock()
493 vga_wseq(par->state.vgabase, 0x15, regval & ~(1<<5)); in s3_set_pixclock()
494 vga_wseq(par->state.vgabase, 0x15, regval | (1<<5)); in s3_set_pixclock()
495 vga_wseq(par->state.vgabase, 0x15, regval & ~(1<<5)); in s3_set_pixclock()
503 struct s3fb_info *par = info->par; in s3fb_open()
505 mutex_lock(&(par->open_lock)); in s3fb_open()
506 if (par->ref_count == 0) { in s3fb_open()
507 void __iomem *vgabase = par->state.vgabase; in s3fb_open()
509 memset(&(par->state), 0, sizeof(struct vgastate)); in s3fb_open()
510 par->state.vgabase = vgabase; in s3fb_open()
511 par->state.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS | VGA_SAVE_CMAP; in s3fb_open()
512 par->state.num_crtc = 0x70; in s3fb_open()
513 par->state.num_seq = 0x20; in s3fb_open()
514 save_vga(&(par->state)); in s3fb_open()
517 par->ref_count++; in s3fb_open()
518 mutex_unlock(&(par->open_lock)); in s3fb_open()
527 struct s3fb_info *par = info->par; in s3fb_release()
529 mutex_lock(&(par->open_lock)); in s3fb_release()
530 if (par->ref_count == 0) { in s3fb_release()
531 mutex_unlock(&(par->open_lock)); in s3fb_release()
532 return -EINVAL; in s3fb_release()
535 if (par->ref_count == 1) in s3fb_release()
536 restore_vga(&(par->state)); in s3fb_release()
538 par->ref_count--; in s3fb_release()
539 mutex_unlock(&(par->open_lock)); in s3fb_release()
548 struct s3fb_info *par = info->par; in s3fb_check_var()
557 if ((par->chip == CHIP_988_VIRGE_VX) ? (rv == 7) : (rv == 6)) in s3fb_check_var()
558 rv = -EINVAL; in s3fb_check_var()
566 if (var->xres > var->xres_virtual) in s3fb_check_var()
567 var->xres_virtual = var->xres; in s3fb_check_var()
569 if (var->yres > var->yres_virtual) in s3fb_check_var()
570 var->yres_virtual = var->yres; in s3fb_check_var()
573 step = s3fb_formats[rv].xresstep - 1; in s3fb_check_var()
574 var->xres_virtual = (var->xres_virtual+step) & ~step; in s3fb_check_var()
577 mem = ((var->bits_per_pixel * var->xres_virtual) >> 3) * var->yres_virtual; in s3fb_check_var()
578 if (mem > info->screen_size) { in s3fb_check_var()
580 mem >> 10, (unsigned int) (info->screen_size >> 10)); in s3fb_check_var()
581 return -EINVAL; in s3fb_check_var()
584 rv = svga_check_timings (&s3_timing_regs, var, info->node); in s3fb_check_var()
590 rv = svga_compute_pll(&s3_pll, PICOS2KHZ(var->pixclock), &m, &n, &r, in s3fb_check_var()
591 info->node); in s3fb_check_var()
604 struct s3fb_info *par = info->par; in s3fb_set_par()
605 u32 value, mode, hmul, offset_value, screen_size, multiplex, dbytes; in s3fb_set_par() local
606 u32 bpp = info->var.bits_per_pixel; in s3fb_set_par()
610 info->fix.ypanstep = 1; in s3fb_set_par()
611 info->fix.line_length = (info->var.xres_virtual * bpp) / 8; in s3fb_set_par()
613 info->flags &= ~FBINFO_MISC_TILEBLITTING; in s3fb_set_par()
614 info->tileops = NULL; in s3fb_set_par()
617 info->pixmap.blit_x = (bpp == 4) ? (1 << (8 - 1)) : (~(u32)0); in s3fb_set_par()
618 info->pixmap.blit_y = ~(u32)0; in s3fb_set_par()
620 offset_value = (info->var.xres_virtual * bpp) / 64; in s3fb_set_par()
621 screen_size = info->var.yres_virtual * info->fix.line_length; in s3fb_set_par()
623 info->fix.ypanstep = 16; in s3fb_set_par()
624 info->fix.line_length = 0; in s3fb_set_par()
626 info->flags |= FBINFO_MISC_TILEBLITTING; in s3fb_set_par()
627 info->tileops = fasttext ? &s3fb_fast_tile_ops : &s3fb_tile_ops; in s3fb_set_par()
630 info->pixmap.blit_x = 1 << (8 - 1); in s3fb_set_par()
631 info->pixmap.blit_y = 1 << (16 - 1); in s3fb_set_par()
633 offset_value = info->var.xres_virtual / 16; in s3fb_set_par()
634 screen_size = (info->var.xres_virtual * info->var.yres_virtual) / 64; in s3fb_set_par()
637 info->var.xoffset = 0; in s3fb_set_par()
638 info->var.yoffset = 0; in s3fb_set_par()
639 info->var.activate = FB_ACTIVATE_NOW; in s3fb_set_par()
642 vga_wcrt(par->state.vgabase, 0x38, 0x48); in s3fb_set_par()
643 vga_wcrt(par->state.vgabase, 0x39, 0xA5); in s3fb_set_par()
644 vga_wseq(par->state.vgabase, 0x08, 0x06); in s3fb_set_par()
645 svga_wcrt_mask(par->state.vgabase, 0x11, 0x00, 0x80); in s3fb_set_par()
648 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); in s3fb_set_par()
649 svga_wcrt_mask(par->state.vgabase, 0x17, 0x00, 0x80); in s3fb_set_par()
652 svga_set_default_gfx_regs(par->state.vgabase); in s3fb_set_par()
653 svga_set_default_atc_regs(par->state.vgabase); in s3fb_set_par()
654 svga_set_default_seq_regs(par->state.vgabase); in s3fb_set_par()
655 svga_set_default_crt_regs(par->state.vgabase); in s3fb_set_par()
656 svga_wcrt_multi(par->state.vgabase, s3_line_compare_regs, 0xFFFFFFFF); in s3fb_set_par()
657 svga_wcrt_multi(par->state.vgabase, s3_start_address_regs, 0); in s3fb_set_par()
660 svga_wcrt_mask(par->state.vgabase, 0x58, 0x10, 0x10); /* enable linear framebuffer */ in s3fb_set_par()
661 …svga_wcrt_mask(par->state.vgabase, 0x31, 0x08, 0x08); /* enable sequencer access to framebuffer ab… in s3fb_set_par()
663 /* svga_wcrt_mask(par->state.vgabase, 0x33, 0x08, 0x08); */ /* DDR ? */ in s3fb_set_par()
664 /* svga_wcrt_mask(par->state.vgabase, 0x43, 0x01, 0x01); */ /* DDR ? */ in s3fb_set_par()
665 svga_wcrt_mask(par->state.vgabase, 0x33, 0x00, 0x08); /* no DDR ? */ in s3fb_set_par()
666 svga_wcrt_mask(par->state.vgabase, 0x43, 0x00, 0x01); /* no DDR ? */ in s3fb_set_par()
668 svga_wcrt_mask(par->state.vgabase, 0x5D, 0x00, 0x28); /* Clear strange HSlen bits */ in s3fb_set_par()
670 /* svga_wcrt_mask(par->state.vgabase, 0x58, 0x03, 0x03); */ in s3fb_set_par()
672 /* svga_wcrt_mask(par->state.vgabase, 0x53, 0x12, 0x13); */ /* enable MMIO */ in s3fb_set_par()
673 /* svga_wcrt_mask(par->state.vgabase, 0x40, 0x08, 0x08); */ /* enable write buffer */ in s3fb_set_par()
678 svga_wcrt_multi(par->state.vgabase, s3_offset_regs, offset_value); in s3fb_set_par()
680 if (par->chip != CHIP_357_VIRGE_GX2 && in s3fb_set_par()
681 par->chip != CHIP_359_VIRGE_GX2P && in s3fb_set_par()
682 par->chip != CHIP_360_TRIO3D_1X && in s3fb_set_par()
683 par->chip != CHIP_362_TRIO3D_2X && in s3fb_set_par()
684 par->chip != CHIP_368_TRIO3D_2X && in s3fb_set_par()
685 par->chip != CHIP_260_VIRGE_MX) { in s3fb_set_par()
686 vga_wcrt(par->state.vgabase, 0x54, 0x18); /* M parameter */ in s3fb_set_par()
687 vga_wcrt(par->state.vgabase, 0x60, 0xff); /* N parameter */ in s3fb_set_par()
688 vga_wcrt(par->state.vgabase, 0x61, 0xff); /* L parameter */ in s3fb_set_par()
689 vga_wcrt(par->state.vgabase, 0x62, 0xff); /* L parameter */ in s3fb_set_par()
692 vga_wcrt(par->state.vgabase, 0x3A, 0x35); in s3fb_set_par()
693 svga_wattr(par->state.vgabase, 0x33, 0x00); in s3fb_set_par()
695 if (info->var.vmode & FB_VMODE_DOUBLE) in s3fb_set_par()
696 svga_wcrt_mask(par->state.vgabase, 0x09, 0x80, 0x80); in s3fb_set_par()
698 svga_wcrt_mask(par->state.vgabase, 0x09, 0x00, 0x80); in s3fb_set_par()
700 if (info->var.vmode & FB_VMODE_INTERLACED) in s3fb_set_par()
701 svga_wcrt_mask(par->state.vgabase, 0x42, 0x20, 0x20); in s3fb_set_par()
703 svga_wcrt_mask(par->state.vgabase, 0x42, 0x00, 0x20); in s3fb_set_par()
706 svga_wcrt_mask(par->state.vgabase, 0x45, 0x00, 0x01); in s3fb_set_par()
708 svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0x0C); in s3fb_set_par()
710 mode = svga_match_format(s3fb_formats, &(info->var), &(info->fix)); in s3fb_set_par()
713 if (par->chip == CHIP_375_VIRGE_DX) { in s3fb_set_par()
714 vga_wcrt(par->state.vgabase, 0x86, 0x80); in s3fb_set_par()
715 vga_wcrt(par->state.vgabase, 0x90, 0x00); in s3fb_set_par()
719 if (par->chip == CHIP_988_VIRGE_VX) { in s3fb_set_par()
720 vga_wcrt(par->state.vgabase, 0x50, 0x00); in s3fb_set_par()
721 vga_wcrt(par->state.vgabase, 0x67, 0x50); in s3fb_set_par()
723 vga_wcrt(par->state.vgabase, 0x63, (mode <= 2) ? 0x90 : 0x09); in s3fb_set_par()
724 vga_wcrt(par->state.vgabase, 0x66, 0x90); in s3fb_set_par()
727 if (par->chip == CHIP_357_VIRGE_GX2 || in s3fb_set_par()
728 par->chip == CHIP_359_VIRGE_GX2P || in s3fb_set_par()
729 par->chip == CHIP_360_TRIO3D_1X || in s3fb_set_par()
730 par->chip == CHIP_362_TRIO3D_2X || in s3fb_set_par()
731 par->chip == CHIP_368_TRIO3D_2X || in s3fb_set_par()
732 par->chip == CHIP_365_TRIO3D || in s3fb_set_par()
733 par->chip == CHIP_375_VIRGE_DX || in s3fb_set_par()
734 par->chip == CHIP_385_VIRGE_GX || in s3fb_set_par()
735 par->chip == CHIP_260_VIRGE_MX) { in s3fb_set_par()
736 dbytes = info->var.xres * ((bpp+7)/8); in s3fb_set_par()
737 vga_wcrt(par->state.vgabase, 0x91, (dbytes + 7) / 8); in s3fb_set_par()
738 vga_wcrt(par->state.vgabase, 0x90, (((dbytes + 7) / 8) >> 8) | 0x80); in s3fb_set_par()
740 vga_wcrt(par->state.vgabase, 0x66, 0x81); in s3fb_set_par()
743 if (par->chip == CHIP_357_VIRGE_GX2 || in s3fb_set_par()
744 par->chip == CHIP_359_VIRGE_GX2P || in s3fb_set_par()
745 par->chip == CHIP_360_TRIO3D_1X || in s3fb_set_par()
746 par->chip == CHIP_362_TRIO3D_2X || in s3fb_set_par()
747 par->chip == CHIP_368_TRIO3D_2X || in s3fb_set_par()
748 par->chip == CHIP_260_VIRGE_MX) in s3fb_set_par()
749 vga_wcrt(par->state.vgabase, 0x34, 0x00); in s3fb_set_par()
751 vga_wcrt(par->state.vgabase, 0x34, 0x10); in s3fb_set_par()
753 svga_wcrt_mask(par->state.vgabase, 0x31, 0x00, 0x40); in s3fb_set_par()
754 multiplex = 0; in s3fb_set_par()
757 /* Set mode-specific register values */ in s3fb_set_par()
761 svga_set_textmode_vga_regs(par->state.vgabase); in s3fb_set_par()
763 /* Set additional registers like in 8-bit mode */ in s3fb_set_par()
764 svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30); in s3fb_set_par()
765 svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0); in s3fb_set_par()
768 svga_wcrt_mask(par->state.vgabase, 0x3A, 0x00, 0x30); in s3fb_set_par()
772 svga_wcrt_mask(par->state.vgabase, 0x31, 0x40, 0x40); in s3fb_set_par()
777 vga_wgfx(par->state.vgabase, VGA_GFX_MODE, 0x40); in s3fb_set_par()
779 /* Set additional registers like in 8-bit mode */ in s3fb_set_par()
780 svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30); in s3fb_set_par()
781 svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0); in s3fb_set_par()
784 svga_wcrt_mask(par->state.vgabase, 0x3A, 0x00, 0x30); in s3fb_set_par()
789 /* Set additional registers like in 8-bit mode */ in s3fb_set_par()
790 svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30); in s3fb_set_par()
791 svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0); in s3fb_set_par()
794 svga_wcrt_mask(par->state.vgabase, 0x3A, 0x00, 0x30); in s3fb_set_par()
798 svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30); in s3fb_set_par()
799 if (info->var.pixclock > 20000 || in s3fb_set_par()
800 par->chip == CHIP_357_VIRGE_GX2 || in s3fb_set_par()
801 par->chip == CHIP_359_VIRGE_GX2P || in s3fb_set_par()
802 par->chip == CHIP_360_TRIO3D_1X || in s3fb_set_par()
803 par->chip == CHIP_362_TRIO3D_2X || in s3fb_set_par()
804 par->chip == CHIP_368_TRIO3D_2X || in s3fb_set_par()
805 par->chip == CHIP_260_VIRGE_MX) in s3fb_set_par()
806 svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0); in s3fb_set_par()
808 svga_wcrt_mask(par->state.vgabase, 0x67, 0x10, 0xF0); in s3fb_set_par()
809 multiplex = 1; in s3fb_set_par()
814 if (par->chip == CHIP_988_VIRGE_VX) { in s3fb_set_par()
815 if (info->var.pixclock > 20000) in s3fb_set_par()
816 svga_wcrt_mask(par->state.vgabase, 0x67, 0x20, 0xF0); in s3fb_set_par()
818 svga_wcrt_mask(par->state.vgabase, 0x67, 0x30, 0xF0); in s3fb_set_par()
819 } else if (par->chip == CHIP_365_TRIO3D) { in s3fb_set_par()
820 svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30); in s3fb_set_par()
821 if (info->var.pixclock > 8695) { in s3fb_set_par()
822 svga_wcrt_mask(par->state.vgabase, 0x67, 0x30, 0xF0); in s3fb_set_par()
825 svga_wcrt_mask(par->state.vgabase, 0x67, 0x20, 0xF0); in s3fb_set_par()
826 multiplex = 1; in s3fb_set_par()
829 svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30); in s3fb_set_par()
830 svga_wcrt_mask(par->state.vgabase, 0x67, 0x30, 0xF0); in s3fb_set_par()
831 if (par->chip != CHIP_357_VIRGE_GX2 && in s3fb_set_par()
832 par->chip != CHIP_359_VIRGE_GX2P && in s3fb_set_par()
833 par->chip != CHIP_360_TRIO3D_1X && in s3fb_set_par()
834 par->chip != CHIP_362_TRIO3D_2X && in s3fb_set_par()
835 par->chip != CHIP_368_TRIO3D_2X && in s3fb_set_par()
836 par->chip != CHIP_260_VIRGE_MX) in s3fb_set_par()
842 if (par->chip == CHIP_988_VIRGE_VX) { in s3fb_set_par()
843 if (info->var.pixclock > 20000) in s3fb_set_par()
844 svga_wcrt_mask(par->state.vgabase, 0x67, 0x40, 0xF0); in s3fb_set_par()
846 svga_wcrt_mask(par->state.vgabase, 0x67, 0x50, 0xF0); in s3fb_set_par()
847 } else if (par->chip == CHIP_365_TRIO3D) { in s3fb_set_par()
848 svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30); in s3fb_set_par()
849 if (info->var.pixclock > 8695) { in s3fb_set_par()
850 svga_wcrt_mask(par->state.vgabase, 0x67, 0x50, 0xF0); in s3fb_set_par()
853 svga_wcrt_mask(par->state.vgabase, 0x67, 0x40, 0xF0); in s3fb_set_par()
854 multiplex = 1; in s3fb_set_par()
857 svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30); in s3fb_set_par()
858 svga_wcrt_mask(par->state.vgabase, 0x67, 0x50, 0xF0); in s3fb_set_par()
859 if (par->chip != CHIP_357_VIRGE_GX2 && in s3fb_set_par()
860 par->chip != CHIP_359_VIRGE_GX2P && in s3fb_set_par()
861 par->chip != CHIP_360_TRIO3D_1X && in s3fb_set_par()
862 par->chip != CHIP_362_TRIO3D_2X && in s3fb_set_par()
863 par->chip != CHIP_368_TRIO3D_2X && in s3fb_set_par()
864 par->chip != CHIP_260_VIRGE_MX) in s3fb_set_par()
871 svga_wcrt_mask(par->state.vgabase, 0x67, 0xD0, 0xF0); in s3fb_set_par()
875 svga_wcrt_mask(par->state.vgabase, 0x50, 0x30, 0x30); in s3fb_set_par()
876 svga_wcrt_mask(par->state.vgabase, 0x67, 0xD0, 0xF0); in s3fb_set_par()
879 fb_err(info, "unsupported mode - bug\n"); in s3fb_set_par()
880 return -EINVAL; in s3fb_set_par()
883 if (par->chip != CHIP_988_VIRGE_VX) { in s3fb_set_par()
884 svga_wseq_mask(par->state.vgabase, 0x15, multiplex ? 0x10 : 0x00, 0x10); in s3fb_set_par()
885 svga_wseq_mask(par->state.vgabase, 0x18, multiplex ? 0x80 : 0x00, 0x80); in s3fb_set_par()
888 s3_set_pixclock(info, info->var.pixclock); in s3fb_set_par()
889 svga_set_timings(par->state.vgabase, &s3_timing_regs, &(info->var), hmul, 1, in s3fb_set_par()
890 (info->var.vmode & FB_VMODE_DOUBLE) ? 2 : 1, in s3fb_set_par()
891 (info->var.vmode & FB_VMODE_INTERLACED) ? 2 : 1, in s3fb_set_par()
892 hmul, info->node); in s3fb_set_par()
895 htotal = info->var.xres + info->var.left_margin + info->var.right_margin + info->var.hsync_len; in s3fb_set_par()
896 htotal = ((htotal * hmul) / 8) - 5; in s3fb_set_par()
897 vga_wcrt(par->state.vgabase, 0x3C, (htotal + 1) / 2); in s3fb_set_par()
900 hsstart = ((info->var.xres + info->var.right_margin) * hmul) / 8; in s3fb_set_par()
903 svga_wcrt_multi(par->state.vgabase, s3_dtpc_regs, value); in s3fb_set_par()
905 if (screen_size > info->screen_size) in s3fb_set_par()
906 screen_size = info->screen_size; in s3fb_set_par()
907 memset_io(info->screen_base, 0x00, screen_size); in s3fb_set_par()
909 svga_wcrt_mask(par->state.vgabase, 0x17, 0x80, 0x80); in s3fb_set_par()
910 svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20); in s3fb_set_par()
920 switch (fb->var.bits_per_pixel) { in s3fb_setcolreg()
924 return -EINVAL; in s3fb_setcolreg()
926 if ((fb->var.bits_per_pixel == 4) && in s3fb_setcolreg()
927 (fb->var.nonstd == 0)) { in s3fb_setcolreg()
940 return -EINVAL; in s3fb_setcolreg()
952 if (fb->var.green.length == 5) in s3fb_setcolreg()
953 ((u32*)fb->pseudo_palette)[regno] = ((red & 0xF800) >> 1) | in s3fb_setcolreg()
955 else if (fb->var.green.length == 6) in s3fb_setcolreg()
956 ((u32*)fb->pseudo_palette)[regno] = (red & 0xF800) | in s3fb_setcolreg()
958 else return -EINVAL; in s3fb_setcolreg()
965 ((u32*)fb->pseudo_palette)[regno] = ((red & 0xFF00) << 8) | in s3fb_setcolreg()
969 return -EINVAL; in s3fb_setcolreg()
980 struct s3fb_info *par = info->par; in s3fb_blank()
985 svga_wcrt_mask(par->state.vgabase, 0x56, 0x00, 0x06); in s3fb_blank()
986 svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20); in s3fb_blank()
990 svga_wcrt_mask(par->state.vgabase, 0x56, 0x00, 0x06); in s3fb_blank()
991 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); in s3fb_blank()
995 svga_wcrt_mask(par->state.vgabase, 0x56, 0x02, 0x06); in s3fb_blank()
996 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); in s3fb_blank()
1000 svga_wcrt_mask(par->state.vgabase, 0x56, 0x04, 0x06); in s3fb_blank()
1001 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); in s3fb_blank()
1005 svga_wcrt_mask(par->state.vgabase, 0x56, 0x06, 0x06); in s3fb_blank()
1006 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); in s3fb_blank()
1018 struct s3fb_info *par = info->par; in s3fb_pan_display()
1022 if (info->var.bits_per_pixel == 0) { in s3fb_pan_display()
1023 offset = (var->yoffset / 16) * (info->var.xres_virtual / 2) in s3fb_pan_display()
1024 + (var->xoffset / 2); in s3fb_pan_display()
1027 offset = (var->yoffset * info->fix.line_length) + in s3fb_pan_display()
1028 (var->xoffset * info->var.bits_per_pixel / 8); in s3fb_pan_display()
1033 svga_wcrt_multi(par->state.vgabase, s3_start_address_regs, offset); in s3fb_pan_display()
1038 /* ------------------------------------------------------------------------- */
1057 /* ------------------------------------------------------------------------- */
1061 int chip = par->chip; in s3_identification()
1064 u8 cr30 = vga_rcrt(par->state.vgabase, 0x30); in s3_identification()
1065 u8 cr2e = vga_rcrt(par->state.vgabase, 0x2e); in s3_identification()
1066 u8 cr2f = vga_rcrt(par->state.vgabase, 0x2f); in s3_identification()
1081 u8 cr6f = vga_rcrt(par->state.vgabase, 0x6f); in s3_identification()
1090 u8 cr6f = vga_rcrt(par->state.vgabase, 0x6f); in s3_identification()
1099 switch (vga_rcrt(par->state.vgabase, 0x2f)) { in s3_identification()
1127 dev_info(&(dev->dev), "ignoring secondary device\n"); in s3_pci_probe()
1128 return -ENODEV; in s3_pci_probe()
1132 info = framebuffer_alloc(sizeof(struct s3fb_info), &(dev->dev)); in s3_pci_probe()
1134 return -ENOMEM; in s3_pci_probe()
1136 par = info->par; in s3_pci_probe()
1137 mutex_init(&par->open_lock); in s3_pci_probe()
1139 info->flags = FBINFO_PARTIAL_PAN_OK | FBINFO_HWACCEL_YPAN; in s3_pci_probe()
1140 info->fbops = &s3fb_ops; in s3_pci_probe()
1145 dev_err(info->device, "cannot enable PCI device\n"); in s3_pci_probe()
1151 dev_err(info->device, "cannot reserve framebuffer region\n"); in s3_pci_probe()
1156 info->fix.smem_start = pci_resource_start(dev, 0); in s3_pci_probe()
1157 info->fix.smem_len = pci_resource_len(dev, 0); in s3_pci_probe()
1159 /* Map physical IO memory address into kernel space */ in s3_pci_probe()
1160 info->screen_base = pci_iomap_wc(dev, 0, 0); in s3_pci_probe()
1161 if (! info->screen_base) { in s3_pci_probe()
1162 rc = -ENOMEM; in s3_pci_probe()
1163 dev_err(info->device, "iomap for framebuffer failed\n"); in s3_pci_probe()
1172 pcibios_bus_to_resource(dev->bus, &vga_res, &bus_reg); in s3_pci_probe()
1174 par->state.vgabase = (void __iomem *) (unsigned long) vga_res.start; in s3_pci_probe()
1177 cr38 = vga_rcrt(par->state.vgabase, 0x38); in s3_pci_probe()
1178 cr39 = vga_rcrt(par->state.vgabase, 0x39); in s3_pci_probe()
1179 vga_wseq(par->state.vgabase, 0x08, 0x06); in s3_pci_probe()
1180 vga_wcrt(par->state.vgabase, 0x38, 0x48); in s3_pci_probe()
1181 vga_wcrt(par->state.vgabase, 0x39, 0xA5); in s3_pci_probe()
1184 par->chip = id->driver_data & CHIP_MASK; in s3_pci_probe()
1185 par->rev = vga_rcrt(par->state.vgabase, 0x2f); in s3_pci_probe()
1186 if (par->chip & CHIP_UNDECIDED_FLAG) in s3_pci_probe()
1187 par->chip = s3_identification(par); in s3_pci_probe()
1191 regval = vga_rcrt(par->state.vgabase, 0x36); in s3_pci_probe()
1192 if (par->chip == CHIP_360_TRIO3D_1X || in s3_pci_probe()
1193 par->chip == CHIP_362_TRIO3D_2X || in s3_pci_probe()
1194 par->chip == CHIP_368_TRIO3D_2X || in s3_pci_probe()
1195 par->chip == CHIP_365_TRIO3D) { in s3_pci_probe()
1197 case 0: /* 8MB -- only 4MB usable for display */ in s3_pci_probe()
1198 case 1: /* 4MB with 32-bit bus */ in s3_pci_probe()
1200 info->screen_size = 4 << 20; in s3_pci_probe()
1204 info->screen_size = 2 << 20; in s3_pci_probe()
1207 } else if (par->chip == CHIP_357_VIRGE_GX2 || in s3_pci_probe()
1208 par->chip == CHIP_359_VIRGE_GX2P || in s3_pci_probe()
1209 par->chip == CHIP_260_VIRGE_MX) { in s3_pci_probe()
1212 info->screen_size = 4 << 20; in s3_pci_probe()
1215 info->screen_size = 2 << 20; in s3_pci_probe()
1218 } else if (par->chip == CHIP_988_VIRGE_VX) { in s3_pci_probe()
1221 info->screen_size = 2 << 20; in s3_pci_probe()
1224 info->screen_size = 4 << 20; in s3_pci_probe()
1227 info->screen_size = 6 << 20; in s3_pci_probe()
1230 info->screen_size = 8 << 20; in s3_pci_probe()
1233 /* off-screen memory */ in s3_pci_probe()
1234 regval = vga_rcrt(par->state.vgabase, 0x37); in s3_pci_probe()
1237 info->screen_size -= 4 << 20; in s3_pci_probe()
1240 info->screen_size -= 2 << 20; in s3_pci_probe()
1244 info->screen_size = s3_memsizes[regval >> 5] << 10; in s3_pci_probe()
1245 info->fix.smem_len = info->screen_size; in s3_pci_probe()
1248 regval = vga_rseq(par->state.vgabase, 0x10); in s3_pci_probe()
1249 par->mclk_freq = ((vga_rseq(par->state.vgabase, 0x11) + 2) * 14318) / ((regval & 0x1F) + 2); in s3_pci_probe()
1250 par->mclk_freq = par->mclk_freq >> (regval >> 5); in s3_pci_probe()
1253 vga_wcrt(par->state.vgabase, 0x38, cr38); in s3_pci_probe()
1254 vga_wcrt(par->state.vgabase, 0x39, cr39); in s3_pci_probe()
1256 strcpy(info->fix.id, s3_names [par->chip]); in s3_pci_probe()
1257 info->fix.mmio_start = 0; in s3_pci_probe()
1258 info->fix.mmio_len = 0; in s3_pci_probe()
1259 info->fix.type = FB_TYPE_PACKED_PIXELS; in s3_pci_probe()
1260 info->fix.visual = FB_VISUAL_PSEUDOCOLOR; in s3_pci_probe()
1261 info->fix.ypanstep = 0; in s3_pci_probe()
1262 info->fix.accel = FB_ACCEL_NONE; in s3_pci_probe()
1263 info->pseudo_palette = (void*) (par->pseudo_palette); in s3_pci_probe()
1264 info->var.bits_per_pixel = 8; in s3_pci_probe()
1268 if (s3fb_ddc_needs_mmio(par->chip)) { in s3_pci_probe()
1269 par->mmio = ioremap(info->fix.smem_start + MMIO_OFFSET, MMIO_SIZE); in s3_pci_probe()
1270 if (par->mmio) in s3_pci_probe()
1271 svga_wcrt_mask(par->state.vgabase, 0x53, 0x08, 0x08); /* enable MMIO */ in s3_pci_probe()
1273 dev_err(info->device, "unable to map MMIO at 0x%lx, disabling DDC", in s3_pci_probe()
1274 info->fix.smem_start + MMIO_OFFSET); in s3_pci_probe()
1276 if (!s3fb_ddc_needs_mmio(par->chip) || par->mmio) in s3_pci_probe()
1278 u8 *edid = fb_ddc_read(&par->ddc_adapter); in s3_pci_probe()
1279 par->ddc_registered = true; in s3_pci_probe()
1281 fb_edid_to_monspecs(edid, &info->monspecs); in s3_pci_probe()
1283 if (!info->monspecs.modedb) in s3_pci_probe()
1284 dev_err(info->device, "error getting mode database\n"); in s3_pci_probe()
1288 fb_videomode_to_modelist(info->monspecs.modedb, in s3_pci_probe()
1289 info->monspecs.modedb_len, in s3_pci_probe()
1290 &info->modelist); in s3_pci_probe()
1291 m = fb_find_best_display(&info->monspecs, &info->modelist); in s3_pci_probe()
1293 fb_videomode_to_var(&info->var, m); in s3_pci_probe()
1294 /* fill all other info->var's fields */ in s3_pci_probe()
1295 if (s3fb_check_var(&info->var, info) == 0) in s3_pci_probe()
1303 mode_option = "640x480-8@60"; in s3_pci_probe()
1307 rc = fb_find_mode(&info->var, info, mode_option, in s3_pci_probe()
1308 info->monspecs.modedb, info->monspecs.modedb_len, in s3_pci_probe()
1309 NULL, info->var.bits_per_pixel); in s3_pci_probe()
1311 rc = -EINVAL; in s3_pci_probe()
1312 dev_err(info->device, "mode %s not found\n", mode_option); in s3_pci_probe()
1313 fb_destroy_modedb(info->monspecs.modedb); in s3_pci_probe()
1314 info->monspecs.modedb = NULL; in s3_pci_probe()
1319 fb_destroy_modedb(info->monspecs.modedb); in s3_pci_probe()
1320 info->monspecs.modedb = NULL; in s3_pci_probe()
1323 info->var.yres_virtual = info->fix.smem_len * 8 / in s3_pci_probe()
1324 (info->var.bits_per_pixel * info->var.xres_virtual); in s3_pci_probe()
1325 if (info->var.yres_virtual < info->var.yres) { in s3_pci_probe()
1326 dev_err(info->device, "virtual vertical size smaller than real\n"); in s3_pci_probe()
1327 rc = -EINVAL; in s3_pci_probe()
1331 rc = fb_alloc_cmap(&info->cmap, 256, 0); in s3_pci_probe()
1333 dev_err(info->device, "cannot allocate colormap\n"); in s3_pci_probe()
1339 dev_err(info->device, "cannot register framebuffer\n"); in s3_pci_probe()
1344 info->fix.id, pci_name(dev), in s3_pci_probe()
1345 info->fix.smem_len >> 20, (par->mclk_freq + 500) / 1000); in s3_pci_probe()
1347 if (par->chip == CHIP_UNKNOWN) in s3_pci_probe()
1349 vga_rcrt(par->state.vgabase, 0x2d), in s3_pci_probe()
1350 vga_rcrt(par->state.vgabase, 0x2e), in s3_pci_probe()
1351 vga_rcrt(par->state.vgabase, 0x2f), in s3_pci_probe()
1352 vga_rcrt(par->state.vgabase, 0x30)); in s3_pci_probe()
1358 par->wc_cookie = arch_phys_wc_add(info->fix.smem_start, in s3_pci_probe()
1359 info->fix.smem_len); in s3_pci_probe()
1365 fb_dealloc_cmap(&info->cmap); in s3_pci_probe()
1369 if (par->ddc_registered) in s3_pci_probe()
1370 i2c_del_adapter(&par->ddc_adapter); in s3_pci_probe()
1371 if (par->mmio) in s3_pci_probe()
1372 iounmap(par->mmio); in s3_pci_probe()
1374 pci_iounmap(dev, info->screen_base); in s3_pci_probe()
1393 par = info->par; in s3_pci_remove()
1394 arch_phys_wc_del(par->wc_cookie); in s3_pci_remove()
1396 fb_dealloc_cmap(&info->cmap); in s3_pci_remove()
1399 if (par->ddc_registered) in s3_pci_remove()
1400 i2c_del_adapter(&par->ddc_adapter); in s3_pci_remove()
1401 if (par->mmio) in s3_pci_remove()
1402 iounmap(par->mmio); in s3_pci_remove()
1405 pci_iounmap(dev, info->screen_base); in s3_pci_remove()
1418 struct s3fb_info *par = info->par; in s3_pci_suspend()
1420 dev_info(info->device, "suspend\n"); in s3_pci_suspend()
1423 mutex_lock(&(par->open_lock)); in s3_pci_suspend()
1425 if (par->ref_count == 0) { in s3_pci_suspend()
1426 mutex_unlock(&(par->open_lock)); in s3_pci_suspend()
1433 mutex_unlock(&(par->open_lock)); in s3_pci_suspend()
1445 struct s3fb_info *par = info->par; in s3_pci_resume()
1447 dev_info(info->device, "resume\n"); in s3_pci_resume()
1450 mutex_lock(&(par->open_lock)); in s3_pci_resume()
1452 if (par->ref_count == 0) { in s3_pci_resume()
1453 mutex_unlock(&(par->open_lock)); in s3_pci_resume()
1461 mutex_unlock(&(par->open_lock)); in s3_pci_resume()
1555 return -ENODEV; in s3fb_init()
1563 /* ------------------------------------------------------------------------- */