Lines Matching +full:pci +full:- +full:ep
1 /* sunxvr500.c: Sun 3DLABS XVR-500 Expert3D fb driver for sparc64 systems
10 #include <linux/pci.h>
16 /* XXX This device has a 'dev-comm' property which apparently is
21 * XXX as the values in the 'dev-comm' area are accurate then
55 static int e3d_get_props(struct e3d_info *ep) in e3d_get_props() argument
57 ep->width = of_getintprop_default(ep->of_node, "width", 0); in e3d_get_props()
58 ep->height = of_getintprop_default(ep->of_node, "height", 0); in e3d_get_props()
59 ep->depth = of_getintprop_default(ep->of_node, "depth", 8); in e3d_get_props()
61 if (!ep->width || !ep->height) { in e3d_get_props()
63 pci_name(ep->pdev)); in e3d_get_props()
64 return -EINVAL; in e3d_get_props()
70 /* My XVR-500 comes up, at 1280x768 and a FB base register value of
84 #define RAMDAC_VID_WH 0x00000070UL /* (height-1)<<16 | (width-1) */
86 #define RAMDAC_VID_32FB_0 0x00000078UL /* PCI base 32bpp FB buffer 0 */
87 #define RAMDAC_VID_32FB_1 0x0000007cUL /* PCI base 32bpp FB buffer 1 */
88 #define RAMDAC_VID_8FB_0 0x00000080UL /* PCI base 8bpp FB buffer 0 */
89 #define RAMDAC_VID_8FB_1 0x00000084UL /* PCI base 8bpp FB buffer 1 */
90 #define RAMDAC_VID_XXXFB 0x00000088UL /* PCI base of XXX FB */
91 #define RAMDAC_VID_YYYFB 0x0000008cUL /* PCI base of YYY FB */
92 #define RAMDAC_VID_ZZZFB 0x00000090UL /* PCI base of ZZZ FB */
98 static void e3d_clut_write(struct e3d_info *ep, int index, u32 val) in e3d_clut_write() argument
100 void __iomem *ramdac = ep->ramdac; in e3d_clut_write()
103 spin_lock_irqsave(&ep->lock, flags); in e3d_clut_write()
108 spin_unlock_irqrestore(&ep->lock, flags); in e3d_clut_write()
115 struct e3d_info *ep = info->par; in e3d_setcolreg() local
129 if (info->fix.visual == FB_VISUAL_TRUECOLOR && regno < 16) in e3d_setcolreg()
130 ((u32 *)info->pseudo_palette)[regno] = value; in e3d_setcolreg()
138 e3d_clut_write(ep, regno, value); in e3d_setcolreg()
152 struct e3d_info *ep = info->par; in e3d_imageblit() local
155 spin_lock_irqsave(&ep->lock, flags); in e3d_imageblit()
157 info->screen_base += ep->fb8_buf_diff; in e3d_imageblit()
159 info->screen_base -= ep->fb8_buf_diff; in e3d_imageblit()
160 spin_unlock_irqrestore(&ep->lock, flags); in e3d_imageblit()
165 struct e3d_info *ep = info->par; in e3d_fillrect() local
168 spin_lock_irqsave(&ep->lock, flags); in e3d_fillrect()
170 info->screen_base += ep->fb8_buf_diff; in e3d_fillrect()
172 info->screen_base -= ep->fb8_buf_diff; in e3d_fillrect()
173 spin_unlock_irqrestore(&ep->lock, flags); in e3d_fillrect()
178 struct e3d_info *ep = info->par; in e3d_copyarea() local
181 spin_lock_irqsave(&ep->lock, flags); in e3d_copyarea()
183 info->screen_base += ep->fb8_buf_diff; in e3d_copyarea()
185 info->screen_base -= ep->fb8_buf_diff; in e3d_copyarea()
186 spin_unlock_irqrestore(&ep->lock, flags); in e3d_copyarea()
197 static int e3d_set_fbinfo(struct e3d_info *ep) in e3d_set_fbinfo() argument
199 struct fb_info *info = ep->info; in e3d_set_fbinfo()
200 struct fb_var_screeninfo *var = &info->var; in e3d_set_fbinfo()
202 info->flags = FBINFO_DEFAULT; in e3d_set_fbinfo()
203 info->fbops = &e3d_ops; in e3d_set_fbinfo()
204 info->screen_base = ep->fb_base; in e3d_set_fbinfo()
205 info->screen_size = ep->fb_size; in e3d_set_fbinfo()
207 info->pseudo_palette = ep->pseudo_palette; in e3d_set_fbinfo()
210 strlcpy(info->fix.id, "e3d", sizeof(info->fix.id)); in e3d_set_fbinfo()
211 info->fix.smem_start = ep->fb_base_phys; in e3d_set_fbinfo()
212 info->fix.smem_len = ep->fb_size; in e3d_set_fbinfo()
213 info->fix.type = FB_TYPE_PACKED_PIXELS; in e3d_set_fbinfo()
214 if (ep->depth == 32 || ep->depth == 24) in e3d_set_fbinfo()
215 info->fix.visual = FB_VISUAL_TRUECOLOR; in e3d_set_fbinfo()
217 info->fix.visual = FB_VISUAL_PSEUDOCOLOR; in e3d_set_fbinfo()
219 var->xres = ep->width; in e3d_set_fbinfo()
220 var->yres = ep->height; in e3d_set_fbinfo()
221 var->xres_virtual = var->xres; in e3d_set_fbinfo()
222 var->yres_virtual = var->yres; in e3d_set_fbinfo()
223 var->bits_per_pixel = ep->depth; in e3d_set_fbinfo()
225 var->red.offset = 8; in e3d_set_fbinfo()
226 var->red.length = 8; in e3d_set_fbinfo()
227 var->green.offset = 16; in e3d_set_fbinfo()
228 var->green.length = 8; in e3d_set_fbinfo()
229 var->blue.offset = 24; in e3d_set_fbinfo()
230 var->blue.length = 8; in e3d_set_fbinfo()
231 var->transp.offset = 0; in e3d_set_fbinfo()
232 var->transp.length = 0; in e3d_set_fbinfo()
234 if (fb_alloc_cmap(&info->cmap, 256, 0)) { in e3d_set_fbinfo()
236 return -ENOMEM; in e3d_set_fbinfo()
248 struct e3d_info *ep; in e3d_pci_register() local
256 return -ENODEV; in e3d_pci_register()
263 return -ENODEV; in e3d_pci_register()
268 printk(KERN_ERR "e3d: Cannot enable PCI device %s\n", in e3d_pci_register()
273 info = framebuffer_alloc(sizeof(struct e3d_info), &pdev->dev); in e3d_pci_register()
275 err = -ENOMEM; in e3d_pci_register()
279 ep = info->par; in e3d_pci_register()
280 ep->info = info; in e3d_pci_register()
281 ep->pdev = pdev; in e3d_pci_register()
282 spin_lock_init(&ep->lock); in e3d_pci_register()
283 ep->of_node = of_node; in e3d_pci_register()
285 /* Read the PCI base register of the frame buffer, which we in e3d_pci_register()
290 &ep->fb_base_reg); in e3d_pci_register()
291 ep->fb_base_reg &= PCI_BASE_ADDRESS_MEM_MASK; in e3d_pci_register()
293 ep->regs_base_phys = pci_resource_start (pdev, 1); in e3d_pci_register()
300 ep->ramdac = ioremap(ep->regs_base_phys + 0x8000, 0x1000); in e3d_pci_register()
301 if (!ep->ramdac) { in e3d_pci_register()
302 err = -ENOMEM; in e3d_pci_register()
306 ep->fb8_0_off = readl(ep->ramdac + RAMDAC_VID_8FB_0); in e3d_pci_register()
307 ep->fb8_0_off -= ep->fb_base_reg; in e3d_pci_register()
309 ep->fb8_1_off = readl(ep->ramdac + RAMDAC_VID_8FB_1); in e3d_pci_register()
310 ep->fb8_1_off -= ep->fb_base_reg; in e3d_pci_register()
312 ep->fb8_buf_diff = ep->fb8_1_off - ep->fb8_0_off; in e3d_pci_register()
314 ep->fb_base_phys = pci_resource_start (pdev, 0); in e3d_pci_register()
315 ep->fb_base_phys += ep->fb8_0_off; in e3d_pci_register()
324 err = e3d_get_props(ep); in e3d_pci_register()
328 line_length = (readl(ep->ramdac + RAMDAC_VID_CFG) >> 16) & 0xff; in e3d_pci_register()
331 switch (ep->depth) { in e3d_pci_register()
333 info->fix.line_length = line_length; in e3d_pci_register()
336 info->fix.line_length = line_length * 2; in e3d_pci_register()
339 info->fix.line_length = line_length * 3; in e3d_pci_register()
342 info->fix.line_length = line_length * 4; in e3d_pci_register()
345 ep->fb_size = info->fix.line_length * ep->height; in e3d_pci_register()
347 ep->fb_base = ioremap(ep->fb_base_phys, ep->fb_size); in e3d_pci_register()
348 if (!ep->fb_base) { in e3d_pci_register()
349 err = -ENOMEM; in e3d_pci_register()
353 err = e3d_set_fbinfo(ep); in e3d_pci_register()
371 fb_dealloc_cmap(&info->cmap); in e3d_pci_register()
374 iounmap(ep->fb_base); in e3d_pci_register()
380 iounmap(ep->ramdac); in e3d_pci_register()
429 return -ENODEV; in e3d_init()