Lines Matching +full:enum +full:- +full:as +full:- +full:flags
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
18 * typedef dma_cookie_t - an opaque DMA cookie
31 * enum dma_status - DMA transaction status
37 enum dma_status {
46 * enum dma_transaction_type - DMA transaction types/indexes
49 * automatically set as dma devices are registered.
51 enum dma_transaction_type {
73 * enum dma_transfer_direction - dma transfer mode and direction indicator
79 enum dma_transfer_direction {
89 * ----------------------------
91 * The gap(in bytes) between two chunks is called inter-chunk-gap(ICG).
96 * it is to be repeated and other per-transfer attributes.
103 * | Frame-1 | Frame-2 | ~ | Frame-'numf' |
111 * struct data_chunk - Element of scatter-gather list that makes a frame.
133 * struct dma_interleaved_template - Template to convey DMAC the transfer pattern
153 enum dma_transfer_direction dir;
164 * enum dma_ctrl_flags - DMA flags to augment operation preparation,
166 * @DMA_PREP_INTERRUPT - trigger an interrupt (callback) upon completion of
168 * @DMA_CTRL_ACK - if clear, the descriptor cannot be reused until the client
171 * @DMA_PREP_PQ_DISABLE_P - prevent generation of P while generating Q
172 * @DMA_PREP_PQ_DISABLE_Q - prevent generation of Q while generating P
173 * @DMA_PREP_CONTINUE - indicate to a driver that it is reusing buffers as
176 * @DMA_PREP_FENCE - tell the driver that subsequent operations depend
188 * active repeated (as indicated by DMA_PREP_REPEAT) transaction when the
194 enum dma_ctrl_flags {
208 * enum sum_check_bits - bit position of pq_check_flags
210 enum sum_check_bits {
216 * enum pq_check_flags - result of async_{xor,pq}_zero_sum operations
217 * @SUM_CHECK_P_RESULT - 1 if xor zero sum error, 0 otherwise
218 * @SUM_CHECK_Q_RESULT - 1 if reed-solomon zero sum error, 0 otherwise
220 enum sum_check_flags {
227 * dma_cap_mask_t - capabilities bitmap modeled after cpumask_t.
233 * struct dma_chan_percpu - the per-CPU part of struct dma_chan
239 * enum dma_desc_metadata_mode - per descriptor metadata mode types supported
240 * @DESC_METADATA_CLIENT - the metadata buffer is allocated/provided by the
245 * - DMA_MEM_TO_DEV / DEV_MEM_TO_MEM:
251 * - DMA_DEV_TO_MEM:
259 * @DESC_METADATA_ENGINE - the metadata buffer is allocated/managed by the DMA
263 * provided as helper functions.
270 * - DMA_MEM_TO_DEV / DEV_MEM_TO_MEM:
278 * - DMA_DEV_TO_MEM:
288 enum dma_desc_metadata_mode {
301 * struct dma_router - DMA router structure
311 * struct dma_chan - devices supply DMA channels, clients use them
322 * @local: per-cpu pointer to a struct dma_chan_percpu
324 * @table_count: number of appearances in the mem-to-mem allocation table
327 * @private: private data for certain client-channel associations
356 * struct dma_chan_dev - relate sysfs device node to backing channel device
368 * enum dma_slave_buswidth - defines bus width of the DMA slave
371 enum dma_slave_buswidth {
384 * struct dma_slave_config - dma slave channel runtime config
400 * @dst_addr_width: same as src_addr_width but for destination
402 * @src_maxburst: the maximum number of words (note: words, as in
407 * @dst_maxburst: same as src_maxburst but for destination target
413 * @dst_port_window_size: same as src_port_window_size but for the destination
419 * slave peripheral will have unique id as dma requester which need to be
420 * pass as slave config.
422 * This struct is passed in as configuration data to a DMA engine
426 * will then be passed in as an argument to the function.
428 * The rationale for adding configuration information to this struct is as
435 enum dma_transfer_direction direction;
438 enum dma_slave_buswidth src_addr_width;
439 enum dma_slave_buswidth dst_addr_width;
449 * enum dma_residue_granularity - Granularity of the reported transfer residue
459 * the hardware supports scatter-gather and the segment descriptor has a field
468 enum dma_residue_granularity {
475 * struct dma_slave_caps - expose capabilities of a slave channel only
481 * Since the enum dma_transfer_direction is not defined as bit flag for
483 * should be checked by controller as well
484 * @min_burst: min burst capability per-transfer
485 * @max_burst: max burst capability per-transfer
507 enum dma_residue_granularity residue_granularity;
513 return dev_name(&chan->dev->device); in dma_chan_name()
519 * typedef dma_filter_fn - callback filter for dma_request_channel
525 * being returned. Where 'suitable' indicates a non-busy channel that
533 enum dmaengine_tx_result {
541 enum dmaengine_tx_result result;
576 * struct dma_async_tx_descriptor - async transaction descriptor
577 * ---dma generic offload fields---
578 * @cookie: tracking cookie for this transaction, set to -EBUSY if
580 * @flags: flags to augment operation preparation, control completion, and
593 * ---async_tx api specific fields---
600 enum dma_ctrl_flags flags; /* not a 'long' to pack with cookie */ member
609 enum dma_desc_metadata_mode desc_metadata_mode;
622 kref_get(&unmap->kref); in dma_set_unmap()
623 tx->unmap = unmap; in dma_set_unmap()
627 dmaengine_get_unmap_data(struct device *dev, int nr, gfp_t flags);
635 dmaengine_get_unmap_data(struct device *dev, int nr, gfp_t flags) in dmaengine_get_unmap_data() argument
646 if (!tx->unmap) in dma_descriptor_unmap()
649 dmaengine_unmap_put(tx->unmap); in dma_descriptor_unmap()
650 tx->unmap = NULL; in dma_descriptor_unmap()
682 spin_lock_bh(&txd->lock); in txd_lock()
686 spin_unlock_bh(&txd->lock); in txd_unlock()
690 txd->next = next; in txd_chain()
691 next->parent = txd; in txd_chain()
695 txd->parent = NULL; in txd_clear_parent()
699 txd->next = NULL; in txd_clear_next()
703 return txd->parent; in txd_parent()
707 return txd->next; in txd_next()
712 * struct dma_tx_state - filled in to report the status of
729 * enum dmaengine_alignment - defines alignment of the DMA async tx
732 enum dmaengine_alignment {
743 * struct dma_slave_map - associates slave device and it's slave channel with
756 * struct dma_filter - information for slave device/channel to filter_fn/param
769 * struct dma_device - info on the entity supplying DMA services
775 * @cap_mask: one or more dma_capability flags
778 * @max_pq: maximum number of PQ sources and PQ-continue capability
791 * Since the enum dma_transfer_direction is not defined as bit flag for
793 * should be checked by controller as well
794 * @min_burst: min burst capability per-transfer
795 * @max_burst: max burst capability per-transfer
819 * with per-channel specific ones
852 enum dma_desc_metadata_mode desc_metadata_modes;
855 enum dmaengine_alignment copy_align;
856 enum dmaengine_alignment xor_align;
857 enum dmaengine_alignment pq_align;
858 enum dmaengine_alignment fill_align;
874 enum dma_residue_granularity residue_granularity;
881 size_t len, unsigned long flags);
884 unsigned int src_cnt, size_t len, unsigned long flags);
887 size_t len, enum sum_check_flags *result, unsigned long flags);
891 size_t len, unsigned long flags);
895 enum sum_check_flags *pqres, unsigned long flags);
898 unsigned long flags);
901 unsigned int nents, int value, unsigned long flags);
903 struct dma_chan *chan, unsigned long flags);
907 unsigned int sg_len, enum dma_transfer_direction direction,
908 unsigned long flags, void *context);
911 size_t period_len, enum dma_transfer_direction direction,
912 unsigned long flags);
915 unsigned long flags);
918 unsigned long flags);
929 enum dma_status (*device_tx_status)(struct dma_chan *chan,
944 if (chan->device->device_config) in dmaengine_slave_config()
945 return chan->device->device_config(chan, config); in dmaengine_slave_config()
947 return -ENOSYS; in dmaengine_slave_config()
950 static inline bool is_slave_direction(enum dma_transfer_direction direction) in is_slave_direction()
958 enum dma_transfer_direction dir, unsigned long flags) in dmaengine_prep_slave_single() argument
965 if (!chan || !chan->device || !chan->device->device_prep_slave_sg) in dmaengine_prep_slave_single()
968 return chan->device->device_prep_slave_sg(chan, &sg, 1, in dmaengine_prep_slave_single()
969 dir, flags, NULL); in dmaengine_prep_slave_single()
974 enum dma_transfer_direction dir, unsigned long flags) in dmaengine_prep_slave_sg() argument
976 if (!chan || !chan->device || !chan->device->device_prep_slave_sg) in dmaengine_prep_slave_sg()
979 return chan->device->device_prep_slave_sg(chan, sgl, sg_len, in dmaengine_prep_slave_sg()
980 dir, flags, NULL); in dmaengine_prep_slave_sg()
987 enum dma_transfer_direction dir, unsigned long flags, in dmaengine_prep_rio_sg() argument
990 if (!chan || !chan->device || !chan->device->device_prep_slave_sg) in dmaengine_prep_rio_sg()
993 return chan->device->device_prep_slave_sg(chan, sgl, sg_len, in dmaengine_prep_rio_sg()
994 dir, flags, rio_ext); in dmaengine_prep_rio_sg()
1000 size_t period_len, enum dma_transfer_direction dir, in dmaengine_prep_dma_cyclic()
1001 unsigned long flags) in dmaengine_prep_dma_cyclic() argument
1003 if (!chan || !chan->device || !chan->device->device_prep_dma_cyclic) in dmaengine_prep_dma_cyclic()
1006 return chan->device->device_prep_dma_cyclic(chan, buf_addr, buf_len, in dmaengine_prep_dma_cyclic()
1007 period_len, dir, flags); in dmaengine_prep_dma_cyclic()
1012 unsigned long flags) in dmaengine_prep_interleaved_dma() argument
1014 if (!chan || !chan->device || !chan->device->device_prep_interleaved_dma) in dmaengine_prep_interleaved_dma()
1016 if (flags & DMA_PREP_REPEAT && in dmaengine_prep_interleaved_dma()
1017 !test_bit(DMA_REPEAT, chan->device->cap_mask.bits)) in dmaengine_prep_interleaved_dma()
1020 return chan->device->device_prep_interleaved_dma(chan, xt, flags); in dmaengine_prep_interleaved_dma()
1025 unsigned long flags) in dmaengine_prep_dma_memset() argument
1027 if (!chan || !chan->device || !chan->device->device_prep_dma_memset) in dmaengine_prep_dma_memset()
1030 return chan->device->device_prep_dma_memset(chan, dest, value, in dmaengine_prep_dma_memset()
1031 len, flags); in dmaengine_prep_dma_memset()
1036 size_t len, unsigned long flags) in dmaengine_prep_dma_memcpy() argument
1038 if (!chan || !chan->device || !chan->device->device_prep_dma_memcpy) in dmaengine_prep_dma_memcpy()
1041 return chan->device->device_prep_dma_memcpy(chan, dest, src, in dmaengine_prep_dma_memcpy()
1042 len, flags); in dmaengine_prep_dma_memcpy()
1046 enum dma_desc_metadata_mode mode) in dmaengine_is_metadata_mode_supported()
1051 return !!(chan->device->desc_metadata_modes & mode); in dmaengine_is_metadata_mode_supported()
1065 return -EINVAL; in dmaengine_desc_attach_metadata()
1076 return -EINVAL; in dmaengine_desc_set_metadata_len()
1081 * dmaengine_terminate_all() - Terminate all active DMA transfers
1089 if (chan->device->device_terminate_all) in dmaengine_terminate_all()
1090 return chan->device->device_terminate_all(chan); in dmaengine_terminate_all()
1092 return -ENOSYS; in dmaengine_terminate_all()
1096 * dmaengine_terminate_async() - Terminate all active DMA transfers
1110 * This function can be called from atomic context as well as from within a
1118 if (chan->device->device_terminate_all) in dmaengine_terminate_async()
1119 return chan->device->device_terminate_all(chan); in dmaengine_terminate_async()
1121 return -EINVAL; in dmaengine_terminate_async()
1125 * dmaengine_synchronize() - Synchronize DMA channel termination
1138 * This function must only be called from non-atomic context and must not be
1146 if (chan->device->device_synchronize) in dmaengine_synchronize()
1147 chan->device->device_synchronize(chan); in dmaengine_synchronize()
1151 * dmaengine_terminate_sync() - Terminate all active DMA transfers
1160 * This function must only be called from non-atomic context and must not be
1179 if (chan->device->device_pause) in dmaengine_pause()
1180 return chan->device->device_pause(chan); in dmaengine_pause()
1182 return -ENOSYS; in dmaengine_pause()
1187 if (chan->device->device_resume) in dmaengine_resume()
1188 return chan->device->device_resume(chan); in dmaengine_resume()
1190 return -ENOSYS; in dmaengine_resume()
1193 static inline enum dma_status dmaengine_tx_status(struct dma_chan *chan, in dmaengine_tx_status()
1196 return chan->device->device_tx_status(chan, cookie, state); in dmaengine_tx_status()
1201 return desc->tx_submit(desc); in dmaengine_submit()
1204 static inline bool dmaengine_check_align(enum dmaengine_alignment align, in dmaengine_check_align()
1207 return !(((1 << align) - 1) & (off1 | off2 | len)); in dmaengine_check_align()
1213 return dmaengine_check_align(dev->copy_align, off1, off2, len); in is_dma_copy_aligned()
1219 return dmaengine_check_align(dev->xor_align, off1, off2, len); in is_dma_xor_aligned()
1225 return dmaengine_check_align(dev->pq_align, off1, off2, len); in is_dma_pq_aligned()
1231 return dmaengine_check_align(dev->fill_align, off1, off2, len); in is_dma_fill_aligned()
1237 dma->max_pq = maxpq; in dma_set_maxpq()
1239 dma->max_pq |= DMA_HAS_PQ_CONTINUE; in dma_set_maxpq()
1242 static inline bool dmaf_continue(enum dma_ctrl_flags flags) in dmaf_continue() argument
1244 return (flags & DMA_PREP_CONTINUE) == DMA_PREP_CONTINUE; in dmaf_continue()
1247 static inline bool dmaf_p_disabled_continue(enum dma_ctrl_flags flags) in dmaf_p_disabled_continue() argument
1249 enum dma_ctrl_flags mask = DMA_PREP_CONTINUE | DMA_PREP_PQ_DISABLE_P; in dmaf_p_disabled_continue()
1251 return (flags & mask) == mask; in dmaf_p_disabled_continue()
1256 return (dma->max_pq & DMA_HAS_PQ_CONTINUE) == DMA_HAS_PQ_CONTINUE; in dma_dev_has_pq_continue()
1261 return dma->max_pq & ~DMA_HAS_PQ_CONTINUE; in dma_dev_to_maxpq()
1264 /* dma_maxpq - reduce maxpq in the face of continued operations
1265 * @dma - dma device with PQ capability
1266 * @flags - to check if DMA_PREP_CONTINUE and DMA_PREP_PQ_DISABLE_P are set
1270 * 1/ {00} * P : remove P from Q', but use it as a source for P'
1277 static inline int dma_maxpq(struct dma_device *dma, enum dma_ctrl_flags flags) in dma_maxpq() argument
1279 if (dma_dev_has_pq_continue(dma) || !dmaf_continue(flags)) in dma_maxpq()
1281 if (dmaf_p_disabled_continue(flags)) in dma_maxpq()
1282 return dma_dev_to_maxpq(dma) - 1; in dma_maxpq()
1283 if (dmaf_continue(flags)) in dma_maxpq()
1284 return dma_dev_to_maxpq(dma) - 3; in dma_maxpq()
1304 return dmaengine_get_icg(xt->dst_inc, xt->dst_sgl, in dmaengine_get_dst_icg()
1305 chunk->icg, chunk->dst_icg); in dmaengine_get_dst_icg()
1311 return dmaengine_get_icg(xt->src_inc, xt->src_sgl, in dmaengine_get_src_icg()
1312 chunk->icg, chunk->src_icg); in dmaengine_get_src_icg()
1315 /* --- public DMA engine API --- */
1345 async_dma_find_channel(enum dma_transaction_type type) in async_dma_find_channel()
1355 tx->flags |= DMA_CTRL_ACK; in async_tx_ack()
1360 tx->flags &= ~DMA_CTRL_ACK; in async_tx_clear_ack()
1365 return (tx->flags & DMA_CTRL_ACK) == DMA_CTRL_ACK; in async_tx_test_ack()
1370 __dma_cap_set(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp) in __dma_cap_set()
1372 set_bit(tx_type, dstp->bits); in __dma_cap_set()
1377 __dma_cap_clear(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp) in __dma_cap_clear()
1379 clear_bit(tx_type, dstp->bits); in __dma_cap_clear()
1385 bitmap_zero(dstp->bits, DMA_TX_TYPE_END); in __dma_cap_zero()
1390 __dma_has_cap(enum dma_transaction_type tx_type, dma_cap_mask_t *srcp) in __dma_has_cap()
1392 return test_bit(tx_type, srcp->bits); in __dma_has_cap()
1399 * dma_async_issue_pending - flush pending transactions to HW
1407 chan->device->device_issue_pending(chan); in dma_async_issue_pending()
1411 * dma_async_is_tx_complete - poll for transaction completion
1419 * the status of multiple cookies without re-checking hardware state.
1421 static inline enum dma_status dma_async_is_tx_complete(struct dma_chan *chan, in dma_async_is_tx_complete()
1425 enum dma_status status; in dma_async_is_tx_complete()
1427 status = chan->device->device_tx_status(chan, cookie, &state); in dma_async_is_tx_complete()
1436 * dma_async_is_complete - test a cookie against chan state
1444 static inline enum dma_status dma_async_is_complete(dma_cookie_t cookie, in dma_async_is_complete()
1463 st->last = last; in dma_set_tx_state()
1464 st->used = used; in dma_set_tx_state()
1465 st->residue = residue; in dma_set_tx_state()
1469 struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type);
1470 enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie);
1471 enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx);
1483 static inline struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type) in dma_find_channel()
1487 static inline enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie) in dma_sync_wait()
1491 static inline enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx) in dma_wait_for_async_tx()
1508 return ERR_PTR(-ENODEV); in dma_request_chan()
1513 return ERR_PTR(-ENODEV); in dma_request_chan_by_mask()
1521 return -ENXIO; in dma_get_slave_caps()
1530 ret = dma_get_slave_caps(tx->chan, &caps); in dmaengine_desc_set_reuse()
1535 return -EPERM; in dmaengine_desc_set_reuse()
1537 tx->flags |= DMA_CTRL_REUSE; in dmaengine_desc_set_reuse()
1543 tx->flags &= ~DMA_CTRL_REUSE; in dmaengine_desc_clear_reuse()
1548 return (tx->flags & DMA_CTRL_REUSE) == DMA_CTRL_REUSE; in dmaengine_desc_test_reuse()
1555 return -EPERM; in dmaengine_desc_free()
1557 return desc->desc_free(desc); in dmaengine_desc_free()
1560 /* --- DMA device --- */
1600 dmaengine_get_direction_text(enum dma_transfer_direction dir) in dmaengine_get_direction_text()