Lines Matching +full:tile +full:- +full:cache
39 * further describe the buffer's format - for example tiling or compression.
42 * ----------------
56 * vendor-namespaced, and as such the relationship between a fourcc code and a
58 * may preserve meaning - such as number of planes - from the fourcc code,
149 * IEEE 754-2008 binary16 half-precision float
167 …010 fourcc_code('V', 'U', '3', '0') /* Y followed by U then V, 10:10:10. Non-linear modifier only …
171 * 16-xx padding occupy lsb
179 * 16-xx padding occupy lsb except Y410
191 * first 64 bits will contain Y,Cb,Cr components for a 2x2 tile
204 * 1-plane YUV 4:2:0
207 * These formats can only be used with a non-Linear modifier.
237 #define DRM_FORMAT_NV24 fourcc_code('N', 'V', '2', '4') /* non-subsampled Cr:Cb plane */
238 #define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */
281 /* 3 plane non-subsampled (444) YCbCr
289 /* 3 plane non-subsampled (444) YCrCb
314 #define DRM_FORMAT_YUV444 fourcc_code('Y', 'U', '2', '4') /* non-subsampled Cb (1) and Cr (2) plane…
315 #define DRM_FORMAT_YVU444 fourcc_code('Y', 'V', '2', '4') /* non-subsampled Cr (1) and Cb (2) plane…
321 * Format modifiers describe, typically, a re-ordering or modification
325 * The upper 8 bits of the format modifier are a vendor-id as assigned
345 #define DRM_FORMAT_RESERVED ((1ULL << 56) - 1)
359 * DRM_FORMAT_MOD_GENERIC_* definitions are used to provide vendor-neutral names
361 * compatibility, in cases where a vendor-specific definition already exists and
366 * generic layouts (such as pixel re-ordering), which may have
367 * independently-developed support across multiple vendors.
370 * vendor-specific modifier, a new 'GENERIC' vendor or modifier using vendor
397 * which tells the driver to also take driver-internal information into account
405 * Intel X-tiling layout
408 * in row-major layout. Within the tile bytes are laid out row-major, with
409 * a platform-dependent stride. On top of that the memory can apply
410 * platform-depending swizzling of some higher address bits into bit6.
414 * cross-driver sharing. It exists since on a given platform it does uniquely
415 * identify the layout in a simple way for i915-specific userspace, which
422 * Intel Y-tiling layout
425 * in row-major layout. Within the tile bytes are laid out in OWORD (16 bytes)
426 * chunks column-major, with a platform-dependent height. On top of that the
427 * memory can apply platform-depending swizzling of some higher address bits
432 * cross-driver sharing. It exists since on a given platform it does uniquely
433 * identify the layout in a simple way for i915-specific userspace, which
440 * Intel Yf-tiling layout
442 * This is a tiled layout using 4Kb tiles in row-major layout.
443 * Within the tile pixels are laid out in 16 256 byte units / sub-tiles which
444 * are arranged in four groups (two wide, two high) with column-major layout.
446 * out as 2x2 column-major.
458 * The main surface will be plane index 0 and must be Y/Yf-tiled,
461 * Each CCS tile matches a 1024x512 pixel area of the main surface.
466 * In reality the CCS tile appears to be a 64Bx64 Y tile, composed
475 * Intel color control surfaces (CCS) for Gen-12 render compression.
477 * The main surface is Y-tiled and at plane index 0, the CCS is linear and
478 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
479 * main surface. In other words, 4 bits in CCS map to a main surface cache
481 * Y-tile widths.
486 * Intel color control surfaces (CCS) for Gen-12 media compression
488 * The main surface is Y-tiled and at plane index 0, the CCS is linear and
489 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
490 * main surface. In other words, 4 bits in CCS map to a main surface cache
492 * Y-tile widths. For semi-planar formats like NV12, CCS planes follow the
499 * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
501 * Macroblocks are laid in a Z-shape, and each pixel data is following the
506 * - multiple of 128 pixels for the width
507 * - multiple of 32 pixels for the height
509 * For more information: see https://linuxtv.org/downloads/v4l-dvb-apis/re32.html
514 * Tiled, 16 (pixels) x 16 (lines) - sized macroblocks
516 * This is a simple tiled layout using tiles of 16x16 pixels in a row-major
526 * Implementation may be platform and base-format specific.
540 * This is a simple tiled layout using tiles of 4x4 pixels in a row-major
546 * Vivante 64x64 super-tiling layout
548 * This is a tiled layout using 64x64 pixel super-tiles, where each super-tile
549 * contains 8x4 groups of 2x4 tiles of 4x4 pixels (like above) each, all in row-
553 * https://github.com/etnaviv/etna_viv/blob/master/doc/hardware.md#texture-tiling
558 * Vivante 4x4 tiling layout for dual-pipe
560 * Same as the 4x4 tiling layout, except every second 4x4 pixel tile starts at a
562 * compared to the non-split tiled layout.
567 * Vivante 64x64 super-tiling layout for dual-pipe
569 * Same as the 64x64 super-tiling layout, except every second 4x4 pixel tile
571 * therefore halved compared to the non-split super-tiled layout.
599 * ---- ----- -----------------------------------------------------------------
603 * DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK()-based modifiers.
605 * 4:4 - Must be 1, to indicate block-linear layout. Necessary for
607 * DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK()-based modifiers.
609 * 8:5 - Reserved (To support 3D-surfaces with variable log2(depth) block
617 * 11:9 - Reserved (To support 2D-array textures with variable array stride
618 * in blocks, specified via log2(tile width in blocks)). Must be
638 * 0 = Gob Height 8, Fermi - Volta, Tegra K1+ Page Kind mapping
639 * 1 = Gob Height 4, G80 - GT2XX Page Kind mapping
649 * 0 = Tegra K1 - Tegra Parker/TX2 Layout.
665 * 55:25 - Reserved for future use. Must be zero.
677 * with block-linear layouts, is remapped within drivers to the value 0xfe,
678 * which corresponds to the "generic" kind used for simple single-sample
679 * uncompressed color formats on Fermi - Volta GPUs.
696 * Within a GOB, data is ordered as 16B x 2 lines sectors laid in Z-shape.
739 ((1ULL << __fourcc_mod_broadcom_param_bits) - 1)))
741 ((m) & ~(((1ULL << __fourcc_mod_broadcom_param_bits) - 1) << \
750 * - 64b utiles of pixels in a raster-order grid according to cpp. It's 4x4
753 * - 1k subtiles made of a 4x4 raster-order grid of 64b utiles (so usually
756 * - 4k tiles made of a 2x2 grid of 1k subtiles (so usually 32x32 pixels). On
757 * even 4k tile rows, they're arranged as (BL, TL, TR, BR), and on odd rows
760 * - an image made of 4k tiles in rows either left-to-right (even rows of 4k
761 * tiles) or right-to-left (odd rows of 4k tiles).
784 * and UV. Some SAND-using hardware stores UV in a separate tiled
828 * the assumption is that a no-XOR tiling modifier will be created.
836 * It provides fine-grained random access and minimizes the amount of data
841 * and different devices or use-cases may support different combinations.
873 * Multiple superblock sizes are only valid for multi-plane YCbCr formats.
890 * AFBC block-split
911 * AFBC copy-block restrict
913 * Buffers with this flag must obey the copy-block restriction. The restriction
914 * is such that there are no copy-blocks referring across the border of 8x8
923 * superblocks inside a tile are stored together in memory. 8x8 tiles are used
927 * to the tile size.
934 * Indicates that the buffer makes use of solid-color blocks, whereby bandwidth
940 * AFBC double-buffer
942 * Indicates that the buffer is allocated in a layout safe for front-buffer
950 * Indicates that the buffer includes per-superblock content hints.
967 * Arm 16x16 Block U-Interleaved modifier
985 * The pixel order in each tile is linear and the tiles are disposed linearly,
986 * both in row-major order.
1000 * The underlying storage is considered to be 3 components, 8bit or 10-bit
1002 * - DRM_FORMAT_YUV420_8BIT
1003 * - DRM_FORMAT_YUV420_10BIT
1027 * - a body content organized in 64x32 superblocks with 4096 bytes per
1029 * - a 32 bytes per 128x64 header block
1047 * be accessible by the user-space clients, but only accessible by the
1050 * The user-space clients should expect a failure while trying to mmap
1051 * the DMA-BUF handle returned by the producer.