Lines Matching full:tiles

407  * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
424  * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
442  * This is a tiled layout using 4Kb tiles in row-major layout.
443  * Within the tile pixels are laid out in 16 256 byte units / sub-tiles which
463  * considered to be made up of normal 128Bx32 Y tiles, Thus
478  * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
489  * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
516  * This is a simple tiled layout using tiles of 16x16 pixels in a row-major
528  * Each macrotile consists of m x n (mostly 4 x 4) tiles.
540  * This is a simple tiled layout using tiles of 4x4 pixels in a row-major
548  * This is a tiled layout using 64x64 pixel super-tiles, where each super-tile
549  * contains 8x4 groups of 2x4 tiles of 4x4 pixels (like above) each, all in row-
580  * Pixels are arranged in simple tiles of 16 x 16 bytes.
756  * - 4k tiles made of a 2x2 grid of 1k subtiles (so usually 32x32 pixels).  On
760  * - an image made of 4k tiles in rows either left-to-right (even rows of 4k
761  *   tiles) or right-to-left (odd rows of 4k tiles).
922  * The tiled layout groups superblocks in 8x8 or 4x4 tiles, where all
923  * superblocks inside a tile are stored together in memory. 8x8 tiles are used
924  * for pixel formats up to and including 32 bpp while 4x4 tiles are used for
925  * larger bpp formats. The order between the tiles is scan line.
983  * With this tiling, the luminance samples are disposed in tiles representing
984  * 32x32 pixels and the chrominance samples in tiles representing 32x64 pixels.
985  * The pixel order in each tile is linear and the tiles are disposed linearly,