Lines Matching +full:0 +full:x3f
46 { 6, 0xF1 }, /* r06 - Power Ctl 1 */
47 { 7, 0xDF }, /* r07 - Power Ctl 2 */
48 { 8, 0x3F }, /* r08 - Power Ctl 3 */
49 { 9, 0x50 }, /* r09 - Charge Pump Freq */
50 { 10, 0x53 }, /* r0A - Output Load MicBias Short Detect */
51 { 11, 0x00 }, /* r0B - DMIC Master Clock Ctl */
52 { 12, 0x00 }, /* r0C - Aux PCM Ctl */
53 { 13, 0x15 }, /* r0D - Aux PCM Master Clock Ctl */
54 { 14, 0x00 }, /* r0E - Audio PCM Ctl */
55 { 15, 0x15 }, /* r0F - Audio PCM Master Clock Ctl */
56 { 16, 0x00 }, /* r10 - Voice PCM Ctl */
57 { 17, 0x15 }, /* r11 - Voice PCM Master Clock Ctl */
58 { 18, 0x00 }, /* r12 - Voice/Aux Sample Rate */
59 { 19, 0x06 }, /* r13 - Misc I/O Path Ctl */
60 { 20, 0x00 }, /* r14 - ADC Input Path Ctl */
61 { 21, 0x00 }, /* r15 - MICA Preamp, PGA Volume */
62 { 22, 0x00 }, /* r16 - MICB Preamp, PGA Volume */
63 { 23, 0x00 }, /* r17 - Input Path A Digital Volume */
64 { 24, 0x00 }, /* r18 - Input Path B Digital Volume */
65 { 25, 0x00 }, /* r19 - Playback Digital Ctl */
66 { 26, 0x00 }, /* r1A - HP/LO Left Digital Volume */
67 { 27, 0x00 }, /* r1B - HP/LO Right Digital Volume */
68 { 28, 0x00 }, /* r1C - Speakerphone Digital Volume */
69 { 29, 0x00 }, /* r1D - Ear/SPKLO Digital Volume */
70 { 30, 0x00 }, /* r1E - HP Left Analog Volume */
71 { 31, 0x00 }, /* r1F - HP Right Analog Volume */
72 { 32, 0x00 }, /* r20 - LO Left Analog Volume */
73 { 33, 0x00 }, /* r21 - LO Right Analog Volume */
74 { 34, 0x00 }, /* r22 - Stereo Input Path Advisory Volume */
75 { 35, 0x00 }, /* r23 - Aux PCM Input Advisory Volume */
76 { 36, 0x00 }, /* r24 - Audio PCM Input Advisory Volume */
77 { 37, 0x00 }, /* r25 - Voice PCM Input Advisory Volume */
78 { 38, 0x00 }, /* r26 - Limiter Attack Rate HP/LO */
79 { 39, 0x7F }, /* r27 - Limter Ctl, Release Rate HP/LO */
80 { 40, 0x00 }, /* r28 - Limter Threshold HP/LO */
81 { 41, 0x00 }, /* r29 - Limiter Attack Rate Speakerphone */
82 { 42, 0x3F }, /* r2A - Limter Ctl, Release Rate Speakerphone */
83 { 43, 0x00 }, /* r2B - Limter Threshold Speakerphone */
84 { 44, 0x00 }, /* r2C - Limiter Attack Rate Ear/SPKLO */
85 { 45, 0x3F }, /* r2D - Limter Ctl, Release Rate Ear/SPKLO */
86 { 46, 0x00 }, /* r2E - Limter Threshold Ear/SPKLO */
87 { 47, 0x00 }, /* r2F - ALC Enable, Attack Rate Left/Right */
88 { 48, 0x3F }, /* r30 - ALC Release Rate Left/Right */
89 { 49, 0x00 }, /* r31 - ALC Threshold Left/Right */
90 { 50, 0x00 }, /* r32 - Noise Gate Ctl Left/Right */
91 { 51, 0x00 }, /* r33 - ALC/NG Misc Ctl */
92 { 52, 0x18 }, /* r34 - Mixer Ctl */
93 { 53, 0x3F }, /* r35 - HP/LO Left Mixer Input Path Volume */
94 { 54, 0x3F }, /* r36 - HP/LO Right Mixer Input Path Volume */
95 { 55, 0x3F }, /* r37 - HP/LO Left Mixer Aux PCM Volume */
96 { 56, 0x3F }, /* r38 - HP/LO Right Mixer Aux PCM Volume */
97 { 57, 0x3F }, /* r39 - HP/LO Left Mixer Audio PCM Volume */
98 { 58, 0x3F }, /* r3A - HP/LO Right Mixer Audio PCM Volume */
99 { 59, 0x3F }, /* r3B - HP/LO Left Mixer Voice PCM Mono Volume */
100 { 60, 0x3F }, /* r3C - HP/LO Right Mixer Voice PCM Mono Volume */
101 { 61, 0x3F }, /* r3D - Aux PCM Left Mixer Input Path Volume */
102 { 62, 0x3F }, /* r3E - Aux PCM Right Mixer Input Path Volume */
103 { 63, 0x3F }, /* r3F - Aux PCM Left Mixer Volume */
104 { 64, 0x3F }, /* r40 - Aux PCM Left Mixer Volume */
105 { 65, 0x3F }, /* r41 - Aux PCM Left Mixer Audio PCM L Volume */
106 { 66, 0x3F }, /* r42 - Aux PCM Right Mixer Audio PCM R Volume */
107 { 67, 0x3F }, /* r43 - Aux PCM Left Mixer Voice PCM Volume */
108 { 68, 0x3F }, /* r44 - Aux PCM Right Mixer Voice PCM Volume */
109 { 69, 0x3F }, /* r45 - Audio PCM Left Input Path Volume */
110 { 70, 0x3F }, /* r46 - Audio PCM Right Input Path Volume */
111 { 71, 0x3F }, /* r47 - Audio PCM Left Mixer Aux PCM L Volume */
112 { 72, 0x3F }, /* r48 - Audio PCM Right Mixer Aux PCM R Volume */
113 { 73, 0x3F }, /* r49 - Audio PCM Left Mixer Volume */
114 { 74, 0x3F }, /* r4A - Audio PCM Right Mixer Volume */
115 { 75, 0x3F }, /* r4B - Audio PCM Left Mixer Voice PCM Volume */
116 { 76, 0x3F }, /* r4C - Audio PCM Right Mixer Voice PCM Volume */
117 { 77, 0x3F }, /* r4D - Voice PCM Left Input Path Volume */
118 { 78, 0x3F }, /* r4E - Voice PCM Right Input Path Volume */
119 { 79, 0x3F }, /* r4F - Voice PCM Left Mixer Aux PCM L Volume */
120 { 80, 0x3F }, /* r50 - Voice PCM Right Mixer Aux PCM R Volume */
121 { 81, 0x3F }, /* r51 - Voice PCM Left Mixer Audio PCM L Volume */
122 { 82, 0x3F }, /* r52 - Voice PCM Right Mixer Audio PCM R Volume */
123 { 83, 0x3F }, /* r53 - Voice PCM Left Mixer Voice PCM Volume */
124 { 84, 0x3F }, /* r54 - Voice PCM Right Mixer Voice PCM Volume */
125 { 85, 0xAA }, /* r55 - Mono Mixer Ctl */
126 { 86, 0x3F }, /* r56 - SPK Mono Mixer Input Path Volume */
127 { 87, 0x3F }, /* r57 - SPK Mono Mixer Aux PCM Mono/L/R Volume */
128 { 88, 0x3F }, /* r58 - SPK Mono Mixer Audio PCM Mono/L/R Volume */
129 { 89, 0x3F }, /* r59 - SPK Mono Mixer Voice PCM Mono Volume */
130 { 90, 0x3F }, /* r5A - SPKLO Mono Mixer Input Path Mono Volume */
131 { 91, 0x3F }, /* r5B - SPKLO Mono Mixer Aux Mono/L/R Volume */
132 { 92, 0x3F }, /* r5C - SPKLO Mono Mixer Audio Mono/L/R Volume */
133 { 93, 0x3F }, /* r5D - SPKLO Mono Mixer Voice Mono Volume */
134 { 94, 0x00 }, /* r5E - Interrupt Mask 1 */
135 { 95, 0x00 }, /* r5F - Interrupt Mask 2 */
161 0, 13, TLV_DB_SCALE_ITEM(-7600, 200, 0),
162 14, 75, TLV_DB_SCALE_ITEM(-4900, 100, 0)
165 static DECLARE_TLV_DB_SCALE(adc_boost_tlv, 0, 2500, 0);
167 static DECLARE_TLV_DB_SCALE(hl_tlv, -10200, 50, 0);
169 static DECLARE_TLV_DB_SCALE(ipd_tlv, -9600, 100, 0);
171 static DECLARE_TLV_DB_SCALE(micpga_tlv, -600, 50, 0);
174 0, 2, TLV_DB_SCALE_ITEM(-3000, 600, 0),
175 3, 7, TLV_DB_SCALE_ITEM(-1200, 300, 0)
215 CS42L73_NGCAB, 0,
221 static const unsigned int cs42l73_mono_mix_values[] = { 0, 1, 2 };
251 SOC_VALUE_ENUM_SINGLE(CS42L73_MMIXCTL, 0, 3,
277 SOC_DAPM_SINGLE("Switch", CS42L73_PWRCTL3, 0, 1, 1);
293 CS42L73_HPAAVOL, CS42L73_HPBAVOL, 0,
294 0x41, 0x4B, hpaloa_tlv),
297 CS42L73_LOBAVOL, 0, 0x41, 0x4B, hpaloa_tlv),
300 CS42L73_MICBPREPGABVOL, 0, 0x34,
301 0x24, micpga_tlv),
307 CS42L73_IPBDVOL, 0, 0xA0, 0x6C, ipd_tlv),
311 0, 0x34, 0xE4, hl_tlv),
314 CS42L73_ADCIPC, 2, 0x01, 1, adc_boost_tlv),
317 CS42L73_ADCIPC, 6, 0x01, 1, adc_boost_tlv),
320 CS42L73_SPKDVOL, 0, 0x34, 0xE4, hl_tlv),
323 CS42L73_ESLDVOL, 0, 0x34, 0xE4, hl_tlv),
330 SOC_DOUBLE("Input Path Digital Switch", CS42L73_ADCIPC, 0, 4, 1, 1),
331 SOC_DOUBLE("HL Digital Playback Switch", CS42L73_PBDC, 0,
338 SOC_SINGLE("PGA Soft-Ramp Switch", CS42L73_MIOPC, 3, 1, 0),
339 SOC_SINGLE("Analog Zero Cross Switch", CS42L73_MIOPC, 2, 1, 0),
340 SOC_SINGLE("Digital Soft-Ramp Switch", CS42L73_MIOPC, 1, 1, 0),
341 SOC_SINGLE("Analog Output Soft-Ramp Switch", CS42L73_MIOPC, 0, 1, 0),
344 0),
346 SOC_SINGLE("HL Limiter Attack Rate", CS42L73_LIMARATEHL, 0, 0x3F,
347 0),
348 SOC_SINGLE("HL Limiter Release Rate", CS42L73_LIMRRATEHL, 0,
349 0x3F, 0),
352 SOC_SINGLE("HL Limiter Switch", CS42L73_LIMRRATEHL, 7, 1, 0),
354 0),
362 SOC_SINGLE("SPK Limiter Attack Rate Volume", CS42L73_LIMARATESPK, 0,
363 0x3F, 0),
364 SOC_SINGLE("SPK Limiter Release Rate Volume", CS42L73_LIMRRATESPK, 0,
365 0x3F, 0),
366 SOC_SINGLE("SPK Limiter Switch", CS42L73_LIMRRATESPK, 7, 1, 0),
368 6, 1, 0),
375 SOC_SINGLE("ESL Limiter Attack Rate Volume", CS42L73_LIMARATEESL, 0,
376 0x3F, 0),
377 SOC_SINGLE("ESL Limiter Release Rate Volume", CS42L73_LIMRRATEESL, 0,
378 0x3F, 0),
379 SOC_SINGLE("ESL Limiter Switch", CS42L73_LIMRRATEESL, 7, 1, 0),
386 SOC_SINGLE("ALC Attack Rate Volume", CS42L73_ALCARATE, 0, 0x3F, 0),
387 SOC_SINGLE("ALC Release Rate Volume", CS42L73_ALCRRATE, 0, 0x3F, 0),
388 SOC_DOUBLE("ALC Switch", CS42L73_ALCARATE, 6, 7, 1, 0),
389 SOC_SINGLE_TLV("ALC Max Threshold Volume", CS42L73_ALCMINMAX, 5, 7, 0,
391 SOC_SINGLE_TLV("ALC Min Threshold Volume", CS42L73_ALCMINMAX, 2, 7, 0,
394 SOC_DOUBLE("NG Enable Switch", CS42L73_NGCAB, 6, 7, 1, 0),
395 SOC_SINGLE("NG Boost Switch", CS42L73_NGCAB, 5, 1, 0),
401 SOC_SINGLE("NG Threshold", CS42L73_NGCAB, 2, 7, 0),
405 CS42L73_XSPAIPAA, CS42L73_XSPBIPBA, 0, 0x3F, 1,
408 CS42L73_XSPAXSPAA, CS42L73_XSPBXSPBA, 0, 0x3F, 1,
411 CS42L73_XSPAASPAA, CS42L73_XSPAASPBA, 0, 0x3F, 1,
414 CS42L73_XSPAVSPMA, CS42L73_XSPBVSPMA, 0, 0x3F, 1,
418 CS42L73_ASPAIPAA, CS42L73_ASPBIPBA, 0, 0x3F, 1,
421 CS42L73_ASPAXSPAA, CS42L73_ASPBXSPBA, 0, 0x3F, 1,
424 CS42L73_ASPAASPAA, CS42L73_ASPBASPBA, 0, 0x3F, 1,
427 CS42L73_ASPAVSPMA, CS42L73_ASPBVSPMA, 0, 0x3F, 1,
431 CS42L73_VSPAIPAA, CS42L73_VSPBIPBA, 0, 0x3F, 1,
434 CS42L73_VSPAXSPAA, CS42L73_VSPBXSPBA, 0, 0x3F, 1,
437 CS42L73_VSPAASPAA, CS42L73_VSPBASPBA, 0, 0x3F, 1,
440 CS42L73_VSPAVSPMA, CS42L73_VSPBVSPMA, 0, 0x3F, 1,
444 CS42L73_HLAIPAA, CS42L73_HLBIPBA, 0, 0x3F, 1,
447 CS42L73_HLAXSPAA, CS42L73_HLBXSPBA, 0, 0x3F, 1,
450 CS42L73_HLAASPAA, CS42L73_HLBASPBA, 0, 0x3F, 1,
453 CS42L73_HLAVSPMA, CS42L73_HLBVSPMA, 0, 0x3F, 1,
457 CS42L73_SPKMIPMA, 0, 0x3F, 1, attn_tlv),
459 CS42L73_SPKMXSPA, 0, 0x3F, 1, attn_tlv),
461 CS42L73_SPKMASPA, 0, 0x3F, 1, attn_tlv),
463 CS42L73_SPKMVSPMA, 0, 0x3F, 1, attn_tlv),
466 CS42L73_ESLMIPMA, 0, 0x3F, 1, attn_tlv),
468 CS42L73_ESLMXSPA, 0, 0x3F, 1, attn_tlv),
470 CS42L73_ESLMASPA, 0, 0x3F, 1, attn_tlv),
472 CS42L73_ESLMVSPMA, 0, 0x3F, 1, attn_tlv),
491 pr_err("Invalid event = 0x%x\n", event); in cs42l73_spklo_spk_amp_event()
493 return 0; in cs42l73_spklo_spk_amp_event()
508 pr_err("Invalid event = 0x%x\n", event); in cs42l73_ear_amp_event()
510 return 0; in cs42l73_ear_amp_event()
526 pr_err("Invalid event = 0x%x\n", event); in cs42l73_hp_amp_event()
528 return 0; in cs42l73_hp_amp_event()
537 SND_SOC_DAPM_SUPPLY("MIC1 Bias", CS42L73_PWRCTL2, 6, 1, NULL, 0),
539 SND_SOC_DAPM_SUPPLY("MIC2 Bias", CS42L73_PWRCTL2, 7, 1, NULL, 0),
541 SND_SOC_DAPM_AIF_OUT("XSPOUTL", NULL, 0,
543 SND_SOC_DAPM_AIF_OUT("XSPOUTR", NULL, 0,
545 SND_SOC_DAPM_AIF_OUT("ASPOUTL", NULL, 0,
547 SND_SOC_DAPM_AIF_OUT("ASPOUTR", NULL, 0,
549 SND_SOC_DAPM_AIF_OUT("VSPINOUT", NULL, 0,
552 SND_SOC_DAPM_PGA("PGA Left", SND_SOC_NOPM, 0, 0, NULL, 0),
553 SND_SOC_DAPM_PGA("PGA Right", SND_SOC_NOPM, 0, 0, NULL, 0),
555 SND_SOC_DAPM_MUX("PGA Left Mux", SND_SOC_NOPM, 0, 0, &pgaa_mux),
556 SND_SOC_DAPM_MUX("PGA Right Mux", SND_SOC_NOPM, 0, 0, &pgab_mux),
564 0, 0, input_left_mixer,
568 0, 0, input_right_mixer,
571 SND_SOC_DAPM_MIXER("ASPL Output Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
572 SND_SOC_DAPM_MIXER("ASPR Output Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
573 SND_SOC_DAPM_MIXER("XSPL Output Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
574 SND_SOC_DAPM_MIXER("XSPR Output Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
575 SND_SOC_DAPM_MIXER("VSP Output Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
577 SND_SOC_DAPM_AIF_IN("XSPINL", NULL, 0,
578 CS42L73_PWRCTL2, 0, 1),
579 SND_SOC_DAPM_AIF_IN("XSPINR", NULL, 0,
580 CS42L73_PWRCTL2, 0, 1),
581 SND_SOC_DAPM_AIF_IN("XSPINM", NULL, 0,
582 CS42L73_PWRCTL2, 0, 1),
584 SND_SOC_DAPM_AIF_IN("ASPINL", NULL, 0,
586 SND_SOC_DAPM_AIF_IN("ASPINR", NULL, 0,
588 SND_SOC_DAPM_AIF_IN("ASPINM", NULL, 0,
591 SND_SOC_DAPM_AIF_IN("VSPINOUT", NULL, 0,
594 SND_SOC_DAPM_MIXER("HL Left Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
595 SND_SOC_DAPM_MIXER("HL Right Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
596 SND_SOC_DAPM_MIXER("SPK Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
597 SND_SOC_DAPM_MIXER("ESL Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
600 0, 0, &esl_xsp_mixer),
603 0, 0, &esl_asp_mixer),
606 0, 0, &spk_asp_mixer),
609 0, 0, &spk_xsp_mixer),
611 SND_SOC_DAPM_PGA("HL Left DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
612 SND_SOC_DAPM_PGA("HL Right DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
613 SND_SOC_DAPM_PGA("SPK DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
614 SND_SOC_DAPM_PGA("ESL DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
616 SND_SOC_DAPM_SWITCH_E("HP Amp", CS42L73_PWRCTL3, 0, 1,
788 /* MCLK, Sample Rate, xMMCC[5:0] */
789 {5644800, 11025, 0x30},
790 {5644800, 22050, 0x20},
791 {5644800, 44100, 0x10},
793 {6000000, 8000, 0x39},
794 {6000000, 11025, 0x33},
795 {6000000, 12000, 0x31},
796 {6000000, 16000, 0x29},
797 {6000000, 22050, 0x23},
798 {6000000, 24000, 0x21},
799 {6000000, 32000, 0x19},
800 {6000000, 44100, 0x13},
801 {6000000, 48000, 0x11},
803 {6144000, 8000, 0x38},
804 {6144000, 12000, 0x30},
805 {6144000, 16000, 0x28},
806 {6144000, 24000, 0x20},
807 {6144000, 32000, 0x18},
808 {6144000, 48000, 0x10},
810 {6500000, 8000, 0x3C},
811 {6500000, 11025, 0x35},
812 {6500000, 12000, 0x34},
813 {6500000, 16000, 0x2C},
814 {6500000, 22050, 0x25},
815 {6500000, 24000, 0x24},
816 {6500000, 32000, 0x1C},
817 {6500000, 44100, 0x15},
818 {6500000, 48000, 0x14},
820 {6400000, 8000, 0x3E},
821 {6400000, 11025, 0x37},
822 {6400000, 12000, 0x36},
823 {6400000, 16000, 0x2E},
824 {6400000, 22050, 0x27},
825 {6400000, 24000, 0x26},
826 {6400000, 32000, 0x1E},
827 {6400000, 44100, 0x17},
828 {6400000, 48000, 0x16},
838 {5644800, 1, 0}, /* 5644800 */
839 {6000000, 1, 0}, /* 6000000 */
840 {6144000, 1, 0}, /* 6144000 */
855 for (i = 0; i < ARRAY_SIZE(cs42l73_mclkx_coeffs); i++) { in cs42l73_get_mclkx_coeff()
866 for (i = 0; i < ARRAY_SIZE(cs42l73_mclk_coeffs); i++) { in cs42l73_get_mclk_coeff()
881 u32 mclk = 0; in cs42l73_set_mclk()
882 u8 dmmcc = 0; in cs42l73_set_mclk()
886 if (mclkx_coeff < 0) in cs42l73_set_mclk()
904 return 0; in cs42l73_set_mclk()
922 if ((cs42l73_set_mclk(dai, freq)) < 0) { in cs42l73_set_sysclk()
930 return 0; in cs42l73_set_sysclk()
1004 return 0; in cs42l73_set_dai_fmt()
1015 for (i = 0; i < ARRAY_SIZE(cs42l73_asrc_rates); i++) { in cs42l73_get_xspfs_coeff()
1019 return 0; /* 0 = Don't know */ in cs42l73_get_xspfs_coeff()
1024 u8 spfs = 0; in cs42l73_update_asrc()
1026 if (srate > 0) in cs42l73_update_asrc()
1031 snd_soc_component_update_bits(component, CS42L73_VXSPFS, 0x0f, spfs); in cs42l73_update_asrc()
1034 snd_soc_component_update_bits(component, CS42L73_ASPC, 0x3c, spfs << 2); in cs42l73_update_asrc()
1037 snd_soc_component_update_bits(component, CS42L73_VXSPFS, 0xf0, spfs << 4); in cs42l73_update_asrc()
1060 if (mclk_coeff < 0) in cs42l73_pcm_hw_params()
1064 "DAI[%d]: MCLK %u, srate %u, MMCC[5:0] = %x\n", in cs42l73_pcm_hw_params()
1068 priv->config[id].mmcc &= 0xC0; in cs42l73_pcm_hw_params()
1070 priv->config[id].spc &= 0xFC; in cs42l73_pcm_hw_params()
1078 priv->config[id].spc &= 0xFC; in cs42l73_pcm_hw_params()
1089 return 0; in cs42l73_pcm_hw_params()
1099 snd_soc_component_update_bits(component, CS42L73_DMMCC, CS42L73_MCLKDIS, 0); in cs42l73_set_bias_level()
1100 snd_soc_component_update_bits(component, CS42L73_PWRCTL1, CS42L73_PDN, 0); in cs42l73_set_bias_level()
1116 if (cs42l73->shutdwn_delay > 0) { in cs42l73_set_bias_level()
1118 cs42l73->shutdwn_delay = 0; in cs42l73_set_bias_level()
1127 return 0; in cs42l73_set_bias_level()
1147 snd_pcm_hw_constraint_list(substream->runtime, 0, in cs42l73_pcm_startup()
1150 return 0; in cs42l73_pcm_startup()
1240 cs42l73->mclk = 0; in cs42l73_probe()
1242 return 0; in cs42l73_probe()
1279 unsigned int devid = 0; in cs42l73_i2c_probe()
1304 "chgfreq", &val32) >= 0) in cs42l73_i2c_probe()
1308 "reset-gpio", 0); in cs42l73_i2c_probe()
1319 if (ret < 0) { in cs42l73_i2c_probe()
1324 gpio_set_value_cansleep(cs42l73->pdata.reset_gpio, 0); in cs42l73_i2c_probe()
1330 devid = (reg & 0xFF) << 12; in cs42l73_i2c_probe()
1333 devid |= (reg & 0xFF) << 4; in cs42l73_i2c_probe()
1336 devid |= (reg & 0xF0) >> 4; in cs42l73_i2c_probe()
1347 if (ret < 0) { in cs42l73_i2c_probe()
1353 "Cirrus Logic CS42L73, Revision: %02X\n", reg & 0xFF); in cs42l73_i2c_probe()
1358 if (ret < 0) in cs42l73_i2c_probe()
1360 return 0; in cs42l73_i2c_probe()
1370 {"cs42l73", 0},