Lines Matching +full:0 +full:x2500
74 CH_L = 0,
108 return 0; in mt6358_set_mtkaif_protocol()
116 0x01f8, 0x01f8); in playback_gpio_set()
118 0xffff, 0x0249); in playback_gpio_set()
120 0xffff, 0x0249); in playback_gpio_set()
131 0x01f8, 0x01f8); in playback_gpio_reset()
133 0x01f8, 0x0000); in playback_gpio_reset()
135 0xf << 8, 0x0); in playback_gpio_reset()
142 0xffff, 0xffff); in capture_gpio_set()
144 0xffff, 0x0249); in capture_gpio_set()
146 0xffff, 0x0249); in capture_gpio_set()
158 0xffff, 0xffff); in capture_gpio_reset()
160 0xffff, 0x0000); in capture_gpio_reset()
162 0xf << 12, 0x0); in capture_gpio_reset()
169 0x1 << RG_XO_AUDIO_EN_M_SFT, in mt6358_set_dcxo()
170 (enable ? 1 : 0) << RG_XO_AUDIO_EN_M_SFT); in mt6358_set_dcxo()
171 return 0; in mt6358_set_dcxo()
180 0x0); in mt6358_set_clksq()
185 (enable ? 1 : 0) << RG_CLKSQ_EN_SFT); in mt6358_set_clksq()
186 return 0; in mt6358_set_clksq()
194 (enable ? 0 : 1) << RG_AUDGLB_PWRDN_VA28_SFT); in mt6358_set_aud_global_bias()
195 return 0; in mt6358_set_aud_global_bias()
202 0x0066, enable ? 0x0 : 0x66); in mt6358_set_topck()
203 return 0; in mt6358_set_topck()
213 0xffff, 0x0010); in mt6358_mtkaif_tx_enable()
217 0xff00, 0x3800); in mt6358_mtkaif_tx_enable()
220 0xff00, 0x3900); in mt6358_mtkaif_tx_enable()
226 0xffff, 0x0010); in mt6358_mtkaif_tx_enable()
230 0xff00, 0x3100); in mt6358_mtkaif_tx_enable()
237 0xffff, 0x0000); in mt6358_mtkaif_tx_enable()
241 0xff00, 0x3100); in mt6358_mtkaif_tx_enable()
244 return 0; in mt6358_mtkaif_tx_enable()
251 0xff00, 0x3000); in mt6358_mtkaif_tx_disable()
252 return 0; in mt6358_mtkaif_tx_disable()
275 return 0; in mt6358_mtkaif_calibration_enable()
286 0 << RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_SFT); in mt6358_mtkaif_calibration_disable()
289 0 << RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_SFT); in mt6358_mtkaif_calibration_disable()
299 return 0; in mt6358_mtkaif_calibration_disable()
314 return 0; in mt6358_set_mtkaif_calibration_phase()
320 DL_GAIN_8DB = 0,
324 DL_GAIN_N_40DB = 0x1f,
329 #define DL_GAIN_REG_MASK 0x0f9f
333 regmap_write(priv->regmap, MT6358_ZCD_CON0, 0x0000); in hp_zcd_disable()
338 int i = 0, stage = 0; in hp_main_output_ramp()
342 for (i = 0; i <= target; i++) { in hp_main_output_ramp()
345 0x7 << 8, stage << 8); in hp_main_output_ramp()
347 0x7 << 11, stage << 11); in hp_main_output_ramp()
354 int i = 0, stage = 0; in hp_aux_feedback_loop_gain_ramp()
357 for (i = 0; i <= 0xf; i++) { in hp_aux_feedback_loop_gain_ramp()
358 stage = up ? i : 0xf - i; in hp_aux_feedback_loop_gain_ramp()
360 0xf << 12, stage << 12); in hp_aux_feedback_loop_gain_ramp()
370 for (i = 0x0; i <= 0x6; i++) { in hp_pull_down()
372 0x7, i); in hp_pull_down()
376 for (i = 0x6; i >= 0x1; i--) { in hp_pull_down()
378 0x7, i); in hp_pull_down()
392 int offset = 0, count = 0, reg_idx; in headset_volume_ramp()
406 while (offset >= 0) { in headset_volume_ramp()
436 if (ret < 0) in mt6358_put_volsw()
481 0xffff, 0x0000); in mt6358_enable_wov_phase2()
482 regmap_update_bits(priv->regmap, MT6358_DCXO_CW14, 0xffff, 0xa2b5); in mt6358_enable_wov_phase2()
484 0xffff, 0x0800); in mt6358_enable_wov_phase2()
487 regmap_update_bits(priv->regmap, MT6358_DCXO_CW13, 0xffff, 0x9929); in mt6358_enable_wov_phase2()
489 0xffff, 0x0025); in mt6358_enable_wov_phase2()
491 0xffff, 0x0005); in mt6358_enable_wov_phase2()
495 0xffff, 0x0000); in mt6358_enable_wov_phase2()
496 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3, 0xffff, 0x0120); in mt6358_enable_wov_phase2()
497 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG0, 0xffff, 0xffff); in mt6358_enable_wov_phase2()
498 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG1, 0xffff, 0x0200); in mt6358_enable_wov_phase2()
499 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG2, 0xffff, 0x2424); in mt6358_enable_wov_phase2()
500 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG3, 0xffff, 0xdbac); in mt6358_enable_wov_phase2()
501 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG4, 0xffff, 0x029e); in mt6358_enable_wov_phase2()
502 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG5, 0xffff, 0x0000); in mt6358_enable_wov_phase2()
504 0xffff, 0x0000); in mt6358_enable_wov_phase2()
506 0xffff, 0x0451); in mt6358_enable_wov_phase2()
507 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_TOP, 0xffff, 0x68d1); in mt6358_enable_wov_phase2()
509 return 0; in mt6358_enable_wov_phase2()
515 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_TOP, 0xffff, 0xc000); in mt6358_disable_wov_phase2()
517 0xffff, 0x0450); in mt6358_disable_wov_phase2()
519 0xffff, 0x0c00); in mt6358_disable_wov_phase2()
520 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG5, 0xffff, 0x0100); in mt6358_disable_wov_phase2()
521 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG4, 0xffff, 0x006c); in mt6358_disable_wov_phase2()
522 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG3, 0xffff, 0xa879); in mt6358_disable_wov_phase2()
523 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG2, 0xffff, 0x2323); in mt6358_disable_wov_phase2()
524 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG1, 0xffff, 0x0400); in mt6358_disable_wov_phase2()
525 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG0, 0xffff, 0x0000); in mt6358_disable_wov_phase2()
526 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3, 0xffff, 0x02d8); in mt6358_disable_wov_phase2()
528 0xffff, 0x0000); in mt6358_disable_wov_phase2()
532 0xffff, 0x0004); in mt6358_disable_wov_phase2()
534 0xffff, 0x0000); in mt6358_disable_wov_phase2()
535 regmap_update_bits(priv->regmap, MT6358_DCXO_CW13, 0xffff, 0x9829); in mt6358_disable_wov_phase2()
537 0xffff, 0x0000); in mt6358_disable_wov_phase2()
539 regmap_update_bits(priv->regmap, MT6358_DCXO_CW14, 0xffff, 0xa2b5); in mt6358_disable_wov_phase2()
541 0xffff, 0x0010); in mt6358_disable_wov_phase2()
543 return 0; in mt6358_disable_wov_phase2()
552 ucontrol->value.integer.value[0] = priv->wov_enabled; in mt6358_get_wov()
553 return 0; in mt6358_get_wov()
561 int enabled = ucontrol->value.integer.value[0]; in mt6358_put_wov()
572 return 0; in mt6358_put_wov()
575 static const DECLARE_TLV_DB_SCALE(playback_tlv, -1000, 100, 0);
576 static const DECLARE_TLV_DB_SCALE(pga_tlv, 0, 600, 0);
581 MT6358_ZCD_CON2, 0, 7, 0x12, 1,
584 MT6358_ZCD_CON1, 0, 7, 0x12, 1,
587 MT6358_ZCD_CON3, 0, 0x12, 1,
592 8, 4, 0,
595 SOC_SINGLE_BOOL_EXT("Wake-on-Voice Phase2 Switch", 0,
606 0x0, 0x1, 0x2, 0x3,
621 HP_MUX_OPEN = 0,
626 HP_MUX_MASK = 0x7,
653 0,
663 0,
673 RCV_MUX_OPEN = 0,
677 RCV_MUX_MASK = 0x3,
693 0,
707 0x0, 0x1,
733 MIC_TYPE_MUX_IDLE = 0,
739 MIC_TYPE_MUX_MASK = 0x7,
766 0,
776 ADC_MUX_IDLE = 0,
780 ADC_MUX_MASK = 0x3,
796 0,
811 0,
821 PGA_MUX_NONE = 0,
825 PGA_MUX_MASK = 0x3,
841 0,
852 0,
867 dev_dbg(priv->dev, "%s(), event = 0x%x\n", __func__, event); in mt_clksq_event()
874 0x0); in mt_clksq_event()
880 return 0; in mt_clksq_event()
890 dev_dbg(priv->dev, "%s(), event = 0x%x\n", __func__, event); in mt_sgen_event()
895 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0006); in mt_sgen_event()
897 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON0, 0xCBA1); in mt_sgen_event()
899 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0003); in mt_sgen_event()
901 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x000B); in mt_sgen_event()
904 0xff3f, in mt_sgen_event()
905 0x0000); in mt_sgen_event()
907 0xffff, in mt_sgen_event()
908 0x0001); in mt_sgen_event()
912 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0000); in mt_sgen_event()
913 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON0, 0xcba0); in mt_sgen_event()
919 return 0; in mt_sgen_event()
929 dev_info(priv->dev, "%s(), event 0x%x, rate %d\n", in mt_aif_in_event()
937 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0006); in mt_aif_in_event()
939 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON0, 0xCBA1); in mt_aif_in_event()
941 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0003); in mt_aif_in_event()
943 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x000B); in mt_aif_in_event()
947 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0000); in mt_aif_in_event()
948 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON0, 0xcba0); in mt_aif_in_event()
956 return 0; in mt_aif_in_event()
965 0x1 << 6, 0x1 << 6); in mtk_hp_enable()
968 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON2, 0x4000); in mtk_hp_enable()
974 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON1, 0x0001); in mtk_hp_enable()
976 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON2, 0x002c); in mtk_hp_enable()
978 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON0, 0x0001); in mtk_hp_enable()
980 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON4, 0x0003); in mtk_hp_enable()
982 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3, 0x0000); in mtk_hp_enable()
987 0x1055, 0x1055); in mtk_hp_enable()
989 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON15, 0x0001); in mtk_hp_enable()
996 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x3000); in mtk_hp_enable()
999 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055); in mtk_hp_enable()
1002 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON11, 0x4900); in mtk_hp_enable()
1005 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055); in mtk_hp_enable()
1007 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON2, 0x4033); in mtk_hp_enable()
1010 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x000c); in mtk_hp_enable()
1012 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x003c); in mtk_hp_enable()
1014 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0c00); in mtk_hp_enable()
1016 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30c0); in mtk_hp_enable()
1018 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30f0); in mtk_hp_enable()
1020 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x00fc); in mtk_hp_enable()
1023 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0e00); in mtk_hp_enable()
1025 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0200); in mtk_hp_enable()
1029 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON10, 0x0000); in mtk_hp_enable()
1032 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x00ff); in mtk_hp_enable()
1039 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fcf); in mtk_hp_enable()
1047 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fc3); in mtk_hp_enable()
1049 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3f03); in mtk_hp_enable()
1053 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, 0x1, 0x1); in mtk_hp_enable()
1055 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30ff); in mtk_hp_enable()
1057 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0xf201); in mtk_hp_enable()
1061 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x32ff); in mtk_hp_enable()
1063 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x3aff); in mtk_hp_enable()
1068 return 0; in mtk_hp_enable()
1078 0x0f00, 0x0000); in mtk_hp_disable()
1082 0x0001, 0x0000); in mtk_hp_disable()
1086 0x000f, 0x0000); in mtk_hp_disable()
1089 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, 0x1, 0x0); in mtk_hp_disable()
1092 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fc3); in mtk_hp_disable()
1094 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fcf); in mtk_hp_disable()
1102 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fff); in mtk_hp_disable()
1111 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3, 0x0); in mtk_hp_disable()
1114 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0e00); in mtk_hp_disable()
1117 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0c00); in mtk_hp_disable()
1121 0x3 << 6, 0x0); in mtk_hp_disable()
1125 0x3 << 4, 0x0); in mtk_hp_disable()
1129 0x3 << 6, 0x0); in mtk_hp_disable()
1132 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0000); in mtk_hp_disable()
1136 0x3 << 4, 0x0); in mtk_hp_disable()
1140 0x3 << 2, 0x0); in mtk_hp_disable()
1144 0x1 << 8, 0x1 << 8); in mtk_hp_disable()
1147 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON15, 0x1, 0x0); in mtk_hp_disable()
1150 0x1055, 0x0); in mtk_hp_disable()
1153 0x1, 0x1); in mtk_hp_disable()
1157 0x1 << 14, 0x0); in mtk_hp_disable()
1161 0x1 << 6, 0x0); in mtk_hp_disable()
1165 return 0; in mtk_hp_disable()
1174 0x1 << 6, 0x1 << 6); in mtk_hp_spk_enable()
1177 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON2, 0x4000); in mtk_hp_spk_enable()
1183 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON1, 0x0001); in mtk_hp_spk_enable()
1185 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON2, 0x002c); in mtk_hp_spk_enable()
1187 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON0, 0x0001); in mtk_hp_spk_enable()
1189 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON4, 0x0003); in mtk_hp_spk_enable()
1191 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3, 0x0000); in mtk_hp_spk_enable()
1196 0x1055, 0x1055); in mtk_hp_spk_enable()
1198 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON15, 0x0001); in mtk_hp_spk_enable()
1205 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x3000); in mtk_hp_spk_enable()
1208 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055); in mtk_hp_spk_enable()
1211 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON11, 0x4900); in mtk_hp_spk_enable()
1214 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055); in mtk_hp_spk_enable()
1216 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON2, 0x4033); in mtk_hp_spk_enable()
1222 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30c0); in mtk_hp_spk_enable()
1224 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30f0); in mtk_hp_spk_enable()
1226 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0200); in mtk_hp_spk_enable()
1230 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON10, 0x0000); in mtk_hp_spk_enable()
1233 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x0003); in mtk_hp_spk_enable()
1245 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON7, 0x0110); in mtk_hp_spk_enable()
1247 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON7, 0x0112); in mtk_hp_spk_enable()
1249 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON7, 0x0113); in mtk_hp_spk_enable()
1262 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, 0x1, 0x1); in mtk_hp_spk_enable()
1264 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30f9); in mtk_hp_spk_enable()
1266 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0201); in mtk_hp_spk_enable()
1268 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON7, 0x011b); in mtk_hp_spk_enable()
1270 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x35f9); in mtk_hp_spk_enable()
1272 return 0; in mtk_hp_spk_enable()
1279 0x0f00, 0x0000); in mtk_hp_spk_disable()
1282 0x3 << 2, 0x0000); in mtk_hp_spk_disable()
1286 0x000f, 0x0000); in mtk_hp_spk_disable()
1289 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, 0x1, 0x0); in mtk_hp_spk_disable()
1304 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3, 0x0); in mtk_hp_spk_disable()
1307 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fc3); in mtk_hp_spk_disable()
1309 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fcf); in mtk_hp_spk_disable()
1312 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fff); in mtk_hp_spk_disable()
1319 0x3 << 4, 0x0); in mtk_hp_spk_disable()
1322 0x1, 0x0); in mtk_hp_spk_disable()
1326 0x3 << 6, 0x0); in mtk_hp_spk_disable()
1329 0x1 << 1, 0x0); in mtk_hp_spk_disable()
1333 0xff << 8, 0x0000); in mtk_hp_spk_disable()
1337 0x1 << 8, 0x1 << 8); in mtk_hp_spk_disable()
1339 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON15, 0x1, 0x0); in mtk_hp_spk_disable()
1341 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14, 0x1055, 0x0); in mtk_hp_spk_disable()
1343 regmap_update_bits(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3, 0x1, 0x1); in mtk_hp_spk_disable()
1347 0x1 << 6, 0x0); in mtk_hp_spk_disable()
1351 return 0; in mtk_hp_spk_disable()
1360 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]); in mt_hp_event()
1363 dev_info(priv->dev, "%s(), event 0x%x, dev_counter[DEV_HP] %d, mux %u\n", in mt_hp_event()
1374 else if (priv->dev_counter[device] <= 0) in mt_hp_event()
1375 dev_warn(priv->dev, "%s(), dev_counter[DEV_HP] %d <= 0\n", in mt_hp_event()
1388 if (priv->dev_counter[device] > 0) { in mt_hp_event()
1390 } else if (priv->dev_counter[device] < 0) { in mt_hp_event()
1391 dev_warn(priv->dev, "%s(), dev_counter[DEV_HP] %d < 0\n", in mt_hp_event()
1394 priv->dev_counter[device] = 0; in mt_hp_event()
1409 return 0; in mt_hp_event()
1419 dev_info(priv->dev, "%s(), event 0x%x, mux %u\n", in mt_rcv_event()
1422 dapm_kcontrol_get_value(w->kcontrols[0])); in mt_rcv_event()
1427 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON2, 0x4000); in mt_rcv_event()
1430 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON1, 0x0001); in mt_rcv_event()
1432 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON2, 0x002c); in mt_rcv_event()
1434 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON0, 0x0001); in mt_rcv_event()
1436 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON4, 0x0003); in mt_rcv_event()
1438 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3, 0x0000); in mt_rcv_event()
1443 0x1055, 0x1055); in mt_rcv_event()
1445 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON15, 0x0001); in mt_rcv_event()
1452 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON6, 0x0010); in mt_rcv_event()
1455 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055); in mt_rcv_event()
1457 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON11, 0x4900); in mt_rcv_event()
1460 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055); in mt_rcv_event()
1462 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON6, 0x0090); in mt_rcv_event()
1465 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0000); in mt_rcv_event()
1468 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON10, 0x0000); in mt_rcv_event()
1471 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON6, 0x0092); in mt_rcv_event()
1473 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON6, 0x0093); in mt_rcv_event()
1477 0x1, 0x1); in mt_rcv_event()
1480 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x0009); in mt_rcv_event()
1482 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0001); in mt_rcv_event()
1484 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON6, 0x009b); in mt_rcv_event()
1494 0x000f, 0x0000); in mt_rcv_event()
1498 0x1, 0x0); in mt_rcv_event()
1505 0x1, 0x0); in mt_rcv_event()
1509 0x1 << 1, 0x0000); in mt_rcv_event()
1513 0xff << 8, 0x0); in mt_rcv_event()
1517 0xff << 8, 0x2 << 8); in mt_rcv_event()
1521 0x1 << 8, 0x1 << 8); in mt_rcv_event()
1525 0x1, 0x0); in mt_rcv_event()
1528 0x1055, 0x0); in mt_rcv_event()
1531 0x1, 0x1); in mt_rcv_event()
1537 return 0; in mt_rcv_event()
1547 dev_dbg(priv->dev, "%s(), event 0x%x, rate %d\n", in mt_aif_out_event()
1561 return 0; in mt_aif_out_event()
1571 dev_dbg(priv->dev, "%s(), event 0x%x\n", in mt_adc_supply_event()
1578 0x1 << 5, 0x1 << 5); in mt_adc_supply_event()
1581 0x0000); in mt_adc_supply_event()
1584 0x2500, 0x0100); in mt_adc_supply_event()
1587 0x2500, 0x2500); in mt_adc_supply_event()
1592 0x2500, 0x0100); in mt_adc_supply_event()
1595 0x2500, 0x0000); in mt_adc_supply_event()
1598 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON3, 0x0000); in mt_adc_supply_event()
1601 0x1 << 5, 0x0 << 5); in mt_adc_supply_event()
1607 return 0; in mt_adc_supply_event()
1621 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2062); in mt6358_amic_enable()
1622 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2062); in mt6358_amic_enable()
1623 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2060); in mt6358_amic_enable()
1624 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2061); in mt6358_amic_enable()
1625 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG1, 0x0100); in mt6358_amic_enable()
1628 /* mic bias 0 */ in mt6358_amic_enable()
1634 0xff00, 0x7700); in mt6358_amic_enable()
1638 0xff00, 0x1100); in mt6358_amic_enable()
1642 0xff00, 0x0000); in mt6358_amic_enable()
1647 0xff, 0x21); in mt6358_amic_enable()
1655 MT6358_AUDENC_ANA_CON10, 0x0161); in mt6358_amic_enable()
1658 MT6358_AUDENC_ANA_CON10, 0x0061); in mt6358_amic_enable()
1664 0xf8ff, 0x0004); in mt6358_amic_enable()
1666 0xf8ff, 0x0004); in mt6358_amic_enable()
1670 0xf8ff, 0x0000); in mt6358_amic_enable()
1672 0xf8ff, 0x0000); in mt6358_amic_enable()
1684 0x1 << RG_AUDPREAMPLON_SFT); in mt6358_amic_enable()
1690 0x1 << RG_AUDPREAMPLDCCEN_SFT); in mt6358_amic_enable()
1700 0x1 << RG_AUDADCLPWRUP_SFT); in mt6358_amic_enable()
1712 0x1 << RG_AUDPREAMPRON_SFT); in mt6358_amic_enable()
1718 0x1 << RG_AUDPREAMPRDCCEN_SFT); in mt6358_amic_enable()
1728 0x1 << RG_AUDADCRPWRUP_SFT); in mt6358_amic_enable()
1735 RG_AUDPREAMPLDCPRECHARGE_MASK_SFT, 0x0); in mt6358_amic_enable()
1738 RG_AUDPREAMPRDCPRECHARGE_MASK_SFT, 0x0); in mt6358_amic_enable()
1742 0x1 << 12, 0x0); in mt6358_amic_enable()
1749 regmap_write(priv->regmap, MT6358_AFE_UL_SRC_CON0_H, 0x0000); in mt6358_amic_enable()
1752 regmap_write(priv->regmap, MT6358_AFE_UL_SRC_CON0_L, 0x0001); in mt6358_amic_enable()
1754 return 0; in mt6358_amic_enable()
1768 0x0001, 0x0000); in mt6358_amic_disable()
1775 0xf000, 0x0000); in mt6358_amic_disable()
1778 0x1 << 1, 0x0); in mt6358_amic_disable()
1779 /* L preamplifier input sel : off, L PGA 0 dB gain */ in mt6358_amic_disable()
1781 0xfffb, 0x0000); in mt6358_amic_disable()
1785 0x1 << 2, 0x0); in mt6358_amic_disable()
1789 0xf000, 0x0000); in mt6358_amic_disable()
1792 0x1 << 1, 0x0); in mt6358_amic_disable()
1793 /* R preamplifier input sel : off, R PGA 0 dB gain */ in mt6358_amic_disable()
1795 0x0ffb, 0x0000); in mt6358_amic_disable()
1799 0x1 << 2, 0x0); in mt6358_amic_disable()
1803 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON9, 0x0000); in mt6358_amic_disable()
1807 0x0001, 0x0000); in mt6358_amic_disable()
1811 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2060); in mt6358_amic_disable()
1813 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2062); in mt6358_amic_disable()
1815 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2062); in mt6358_amic_disable()
1817 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2062); in mt6358_amic_disable()
1827 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON9, 0x0021); in mt6358_dmic_enable()
1831 0x1 << 12, 0x0); in mt6358_dmic_enable()
1834 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON8, 0x0005); in mt6358_dmic_enable()
1841 regmap_write(priv->regmap, MT6358_AFE_UL_SRC_CON0_H, 0x0400); in mt6358_dmic_enable()
1843 regmap_write(priv->regmap, MT6358_AFE_UL_SRC_CON0_H, 0x0080); in mt6358_dmic_enable()
1846 regmap_write(priv->regmap, MT6358_AFE_UL_SRC_CON0_L, 0x0003); in mt6358_dmic_enable()
1851 return 0; in mt6358_dmic_enable()
1860 0x0003, 0x0000); in mt6358_dmic_disable()
1866 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON8, 0x0000); in mt6358_dmic_disable()
1870 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON9, 0x0001); in mt6358_dmic_disable()
1874 0x1 << 12, 0x0); in mt6358_dmic_disable()
1877 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON9, 0x0000); in mt6358_dmic_disable()
1901 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]); in mt_mic_type_event()
1903 dev_dbg(priv->dev, "%s(), event 0x%x, mux %u\n", in mt_mic_type_event()
1938 return 0; in mt_mic_type_event()
1947 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]); in mt_adc_l_event()
1949 dev_dbg(priv->dev, "%s(), event = 0x%x, mux %u\n", in mt_adc_l_event()
1954 return 0; in mt_adc_l_event()
1963 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]); in mt_adc_r_event()
1965 dev_dbg(priv->dev, "%s(), event = 0x%x, mux %u\n", in mt_adc_r_event()
1970 return 0; in mt_adc_r_event()
1979 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]); in mt_pga_left_event()
1981 dev_dbg(priv->dev, "%s(), event = 0x%x, mux %u\n", in mt_pga_left_event()
1986 return 0; in mt_pga_left_event()
1995 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]); in mt_pga_right_event()
1997 dev_dbg(priv->dev, "%s(), event = 0x%x, mux %u\n", in mt_pga_right_event()
2002 return 0; in mt_pga_right_event()
2020 return 0; in mt_delay_250_event()
2028 RG_XO_AUDIO_EN_M_SFT, 0, NULL, 0),
2031 RG_AUDGLB_PWRDN_VA28_SFT, 1, NULL, 0),
2034 RG_CLKSQ_EN_SFT, 0,
2039 RG_AUDNCP_CK_PDN_SFT, 1, NULL, 0),
2042 RG_ZCD13M_CK_PDN_SFT, 1, NULL, 0),
2050 RG_AUDIF_CK_PDN_SFT, 1, NULL, 0),
2060 PDN_DAC_CTL_SFT, 1, NULL, 0),
2063 PDN_ADC_CTL_SFT, 1, NULL, 0),
2066 PDN_I2S_DL_CTL_SFT, 1, NULL, 0),
2069 PWR_CLK_DIS_CTL_SFT, 1, NULL, 0),
2072 PDN_AFE_TESTMODEL_CTL_SFT, 1, NULL, 0),
2075 PDN_RESERVED_SFT, 1, NULL, 0),
2078 0, 0, NULL, 0),
2082 MT6358_AFE_UL_DL_CON0, AFE_ON_SFT, 0,
2083 NULL, 0),
2086 SND_SOC_DAPM_AIF_IN_E("AIF_RX", "AIF1 Playback", 0,
2088 DL_2_SRC_ON_TMP_CTL_PRE_SFT, 0,
2094 0, 0, NULL, 0),
2097 SND_SOC_DAPM_MUX("DAC In Mux", SND_SOC_NOPM, 0, 0, &dac_in_mux_control),
2099 SND_SOC_DAPM_DAC("DACL", NULL, SND_SOC_NOPM, 0, 0),
2101 SND_SOC_DAPM_DAC("DACR", NULL, SND_SOC_NOPM, 0, 0),
2104 SND_SOC_DAPM_MUX("LOL Mux", SND_SOC_NOPM, 0, 0, &lo_in_mux_control),
2107 RG_LOOUTPUTSTBENH_VAUDP15_SFT, 0, NULL, 0),
2110 RG_AUDLOLPWRUP_VAUDP15_SFT, 0, NULL, 0),
2113 SND_SOC_DAPM_MUX_E("HPL Mux", SND_SOC_NOPM, 0, 0,
2119 SND_SOC_DAPM_MUX_E("HPR Mux", SND_SOC_NOPM, 0, 0,
2126 SND_SOC_DAPM_MUX_E("RCV Mux", SND_SOC_NOPM, 0, 0,
2143 SGEN_DAC_EN_CTL_SFT, 0, NULL, 0),
2149 DL_2_SRC_ON_TMP_CTL_PRE_SFT, 0, NULL, 0),
2154 SND_SOC_DAPM_AIF_OUT_E("AIF1TX", "AIF1 Capture", 0,
2155 SND_SOC_NOPM, 0, 0,
2160 SND_SOC_NOPM, 0, 0,
2165 SND_SOC_DAPM_MUX("AIF Out Mux", SND_SOC_NOPM, 0, 0,
2168 SND_SOC_DAPM_MUX_E("Mic Type Mux", SND_SOC_NOPM, 0, 0,
2174 SND_SOC_DAPM_MUX_E("ADC L Mux", SND_SOC_NOPM, 0, 0,
2178 SND_SOC_DAPM_MUX_E("ADC R Mux", SND_SOC_NOPM, 0, 0,
2183 SND_SOC_DAPM_ADC("ADC L", NULL, SND_SOC_NOPM, 0, 0),
2184 SND_SOC_DAPM_ADC("ADC R", NULL, SND_SOC_NOPM, 0, 0),
2186 SND_SOC_DAPM_MUX_E("PGA L Mux", SND_SOC_NOPM, 0, 0,
2190 SND_SOC_DAPM_MUX_E("PGA R Mux", SND_SOC_NOPM, 0, 0,
2195 SND_SOC_DAPM_PGA("PGA L", SND_SOC_NOPM, 0, 0, NULL, 0),
2196 SND_SOC_DAPM_PGA("PGA R", SND_SOC_NOPM, 0, 0, NULL, 0),
2336 return 0; in mt6358_codec_dai_hw_params()
2381 0x1 << RG_AUDHPLSCDISABLE_VAUDP15_SFT); in mt6358_codec_init_reg()
2384 0x1 << RG_AUDHPRSCDISABLE_VAUDP15_SFT); in mt6358_codec_init_reg()
2388 0x1 << RG_AUDHSSCDISABLE_VAUDP15_SFT); in mt6358_codec_init_reg()
2392 0x1 << RG_AUDLOLSCDISABLE_VAUDP15_SFT); in mt6358_codec_init_reg()
2396 0xFFFF, 0x700E); in mt6358_codec_init_reg()
2399 regmap_write(priv->regmap, MT6358_DRV_CON3, 0x8888); in mt6358_codec_init_reg()
2425 return 0; in mt6358_codec_probe()
2448 priv->dmic_one_wire_mode = 0; in mt6358_parse_dt()