Lines Matching +full:0 +full:xfff7
24 regmap_write(priv->regmap, MT6359_GPIO_MODE2_CLR, 0x0ffe); in mt6359_set_playback_gpio()
25 regmap_write(priv->regmap, MT6359_GPIO_MODE2_SET, 0x0249); in mt6359_set_playback_gpio()
28 regmap_write(priv->regmap, MT6359_GPIO_MODE3_CLR, 0x6); in mt6359_set_playback_gpio()
29 regmap_write(priv->regmap, MT6359_GPIO_MODE3_SET, 0x1); in mt6359_set_playback_gpio()
39 regmap_write(priv->regmap, MT6359_GPIO_MODE2_CLR, 0x0ff8); in mt6359_reset_playback_gpio()
40 regmap_update_bits(priv->regmap, MT6359_GPIO_DIR0, 0x7 << 9, 0x0); in mt6359_reset_playback_gpio()
46 regmap_write(priv->regmap, MT6359_GPIO_MODE3_CLR, 0x0e00); in mt6359_set_capture_gpio()
47 regmap_write(priv->regmap, MT6359_GPIO_MODE3_SET, 0x0200); in mt6359_set_capture_gpio()
49 regmap_write(priv->regmap, MT6359_GPIO_MODE4_CLR, 0x003f); in mt6359_set_capture_gpio()
50 regmap_write(priv->regmap, MT6359_GPIO_MODE4_SET, 0x0009); in mt6359_set_capture_gpio()
61 regmap_write(priv->regmap, MT6359_GPIO_MODE3_CLR, 0x0e00); in mt6359_reset_capture_gpio()
63 regmap_write(priv->regmap, MT6359_GPIO_MODE4_CLR, 0x003f); in mt6359_reset_capture_gpio()
66 0x7 << 13, 0x0); in mt6359_reset_capture_gpio()
68 0x3 << 0, 0x0); in mt6359_reset_capture_gpio()
75 (enable ? 1 : 0) << RG_RSTB_DECODER_VA32_SFT); in mt6359_set_decoder_clk()
85 0xffff, 0x0210); in mt6359_mtkaif_tx_enable()
89 0xff00, 0x3800); in mt6359_mtkaif_tx_enable()
92 0xff00, 0x3900); in mt6359_mtkaif_tx_enable()
98 0xffff, 0x0210); in mt6359_mtkaif_tx_enable()
102 0xff00, 0x3100); in mt6359_mtkaif_tx_enable()
109 0xffff, 0x0000); in mt6359_mtkaif_tx_enable()
113 0xff00, 0x3100); in mt6359_mtkaif_tx_enable()
122 0xff00, 0x3000); in mt6359_mtkaif_tx_disable()
127 regmap_write(priv->regmap, MT6359_ZCD_CON0, 0x0000); in zcd_disable()
132 int i = 0, stage = 0; in hp_main_output_ramp()
136 for (i = 0; i <= target; i++) { in hp_main_output_ramp()
150 int i = 0, stage = 0; in hp_aux_feedback_loop_gain_ramp()
151 int target = 0xf; in hp_aux_feedback_loop_gain_ramp()
154 for (i = 0; i <= target; i++) { in hp_aux_feedback_loop_gain_ramp()
157 0xf << 12, stage << 12); in hp_aux_feedback_loop_gain_ramp()
164 int i = 0, stage = 0; in hp_in_pair_current()
165 int target = 0x3; in hp_in_pair_current()
170 for (i = 0; i <= target; i++) { in hp_in_pair_current()
174 0x3 << 3, stage << 3); in hp_in_pair_current()
185 for (i = 0x0; i <= 0x7; i++) { in hp_pull_down()
192 for (i = 0x7; i >= 0x0; i--) { in hp_pull_down()
210 int offset = 0, count = 1, reg_idx; in headset_volume_ramp()
225 while (offset > 0) { in headset_volume_ramp()
252 int index = ucontrol->value.integer.value[0]; in mt6359_put_volsw()
256 if (ret < 0) in mt6359_put_volsw()
296 dev_dbg(priv->dev, "%s(), name %s, reg(0x%x) = 0x%x, set index = %x\n", in mt6359_put_volsw()
309 static SOC_ENUM_SINGLE_DECL(lo_in_mux_map_enum, SND_SOC_NOPM, 0, lo_in_mux_map);
325 0,
338 0,
350 0x0, 0x1,
624 dev_dbg(priv->dev, "%s(), event = 0x%x\n", __func__, event); in mt_sgen_event()
629 regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON2, 0x0006); in mt_sgen_event()
631 regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON0, 0xcba1); in mt_sgen_event()
633 regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON2, 0x0003); in mt_sgen_event()
635 regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON2, 0x000b); in mt_sgen_event()
638 0xff3f, in mt_sgen_event()
639 0x0000); in mt_sgen_event()
641 0xffff, in mt_sgen_event()
642 0x0001); in mt_sgen_event()
646 regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON2, 0x0000); in mt_sgen_event()
647 regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON0, 0xcba0); in mt_sgen_event()
653 return 0; in mt_sgen_event()
688 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON10, 0x0087); in mtk_hp_enable()
696 0x1 << RG_AUDHPHFCOMPBUFGAINSEL_VAUDP32_SFT); in mtk_hp_enable()
698 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON4, 0x0000); in mtk_hp_enable()
701 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON2, 0xf133); in mtk_hp_enable()
704 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON1, 0x000c); in mtk_hp_enable()
706 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON1, 0x003c); in mtk_hp_enable()
708 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON9, 0x0c00); in mtk_hp_enable()
710 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON0, 0x30c0); in mtk_hp_enable()
712 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON0, 0x30f0); in mtk_hp_enable()
714 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON1, 0x00fc); in mtk_hp_enable()
720 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON9, 0x0e00); in mtk_hp_enable()
722 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON9, 0x0200); in mtk_hp_enable()
725 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON1, 0x00ff); in mtk_hp_enable()
732 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON1, 0x77cf); in mtk_hp_enable()
740 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON1, 0x77c3); in mtk_hp_enable()
742 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON1, 0x7703); in mtk_hp_enable()
749 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON0, 0x30ff); in mtk_hp_enable()
752 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON9, 0xf201); in mtk_hp_enable()
755 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON9, 0xf200); in mtk_hp_enable()
760 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON0, 0x32ff); in mtk_hp_enable()
762 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON0, 0x3aff); in mtk_hp_enable()
775 0x0f00, 0x0000); in mtk_hp_disable()
779 0x0001, 0x0000); in mtk_hp_disable()
783 0x000f, 0x0000); in mtk_hp_disable()
789 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON1, 0x77c3); in mtk_hp_disable()
791 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON1, 0x77cf); in mtk_hp_disable()
799 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON1, 0x77ff); in mtk_hp_disable()
808 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON1, 0x3, 0x0); in mtk_hp_disable()
811 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON9, 0x0e01); in mtk_hp_disable()
814 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON9, 0x0c01); in mtk_hp_disable()
821 0x3 << 6, 0x0); in mtk_hp_disable()
825 0x3 << 4, 0x0); in mtk_hp_disable()
829 0x3 << 6, 0x0); in mtk_hp_disable()
832 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON9, 0x201); in mtk_hp_disable()
836 0x3 << 4, 0x0); in mtk_hp_disable()
840 0x3 << 2, 0x0); in mtk_hp_disable()
849 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]); in mt_hp_event()
852 dev_dbg(priv->dev, "%s(), event 0x%x, dev_counter[DEV_HP] %d, mux %u\n", in mt_hp_event()
870 return 0; in mt_hp_event()
880 dev_dbg(priv->dev, "%s(), event 0x%x, mux %u\n", in mt_rcv_event()
881 __func__, event, dapm_kcontrol_get_value(w->kcontrols[0])); in mt_rcv_event()
886 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON6, 0x0010); in mt_rcv_event()
902 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON6, 0x0090); in mt_rcv_event()
905 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON10, 0x7000); in mt_rcv_event()
908 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON6, 0x0092); in mt_rcv_event()
910 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON6, 0x0093); in mt_rcv_event()
920 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON0, 0x0009); in mt_rcv_event()
922 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON9, 0x0001); in mt_rcv_event()
924 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON6, 0x009b); in mt_rcv_event()
934 0x000f, 0x0000); in mt_rcv_event()
944 RG_AUDHSPWRUP_VAUDP32_MASK_SFT, 0x0); in mt_rcv_event()
948 RG_AUDHSPWRUP_IBIAS_VAUDP32_MASK_SFT, 0x0); in mt_rcv_event()
954 return 0; in mt_rcv_event()
964 dev_dbg(priv->dev, "%s(), event 0x%x, mux %u\n", in mt_lo_event()
965 __func__, event, dapm_kcontrol_get_value(w->kcontrols[0])); in mt_lo_event()
970 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON7, 0x0010); in mt_lo_event()
978 if (priv->dev_counter[DEVICE_HP] == 0) in mt_lo_event()
989 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON7, 0x0110); in mt_lo_event()
992 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON7, 0x0112); in mt_lo_event()
994 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON7, 0x0113); in mt_lo_event()
1004 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON7, 0x3113); in mt_lo_event()
1006 if (priv->dev_counter[DEVICE_HP] == 0) in mt_lo_event()
1008 MT6359_AUDDEC_ANA_CON9, 0x0001); in mt_lo_event()
1010 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON7, 0x311b); in mt_lo_event()
1020 0x000f, 0x0000); in mt_lo_event()
1030 RG_AUDLOLPWRUP_VAUDP32_MASK_SFT, 0x0); in mt_lo_event()
1034 RG_AUDLOLPWRUP_IBIAS_VAUDP32_MASK_SFT, 0x0); in mt_lo_event()
1040 return 0; in mt_lo_event()
1050 dev_dbg(priv->dev, "%s(), event 0x%x\n", __func__, event); in mt_adc_clk_gen_event()
1057 0x1 << RG_AUDADCCLKRSTB_SFT); in mt_adc_clk_gen_event()
1059 RG_AUDADCCLKSOURCE_MASK_SFT, 0x0); in mt_adc_clk_gen_event()
1061 RG_AUDADCCLKSEL_MASK_SFT, 0x0); in mt_adc_clk_gen_event()
1064 0x1 << RG_AUDADCCLKGENMODE_SFT); in mt_adc_clk_gen_event()
1068 RG_AUDADCCLKSOURCE_MASK_SFT, 0x0); in mt_adc_clk_gen_event()
1070 RG_AUDADCCLKSEL_MASK_SFT, 0x0); in mt_adc_clk_gen_event()
1072 RG_AUDADCCLKGENMODE_MASK_SFT, 0x0); in mt_adc_clk_gen_event()
1074 RG_AUDADCCLKRSTB_MASK_SFT, 0x0); in mt_adc_clk_gen_event()
1080 return 0; in mt_adc_clk_gen_event()
1090 dev_dbg(priv->dev, "%s(), event 0x%x\n", __func__, event); in mt_dcc_clk_event()
1097 0xfff7, 0x2062); in mt_dcc_clk_event()
1099 0xfff7, 0x2060); in mt_dcc_clk_event()
1101 0xfff7, 0x2061); in mt_dcc_clk_event()
1103 regmap_write(priv->regmap, MT6359_AFE_DCCLK_CFG1, 0x0100); in mt_dcc_clk_event()
1107 0xfff7, 0x2060); in mt_dcc_clk_event()
1109 0xfff7, 0x2062); in mt_dcc_clk_event()
1115 return 0; in mt_dcc_clk_event()
1126 dev_dbg(priv->dev, "%s(), event 0x%x, mic_type %d\n", in mt_mic_bias_0_event()
1135 0xff00, 0x7700); in mt_mic_bias_0_event()
1140 0xff00, 0x1100); in mt_mic_bias_0_event()
1145 0xff00, 0x0000); in mt_mic_bias_0_event()
1151 MT6359_AUDENC_ANA_CON14, 0x0004); in mt_mic_bias_0_event()
1159 0 << RG_AUDMICBIAS0LOWPEN_SFT); in mt_mic_bias_0_event()
1163 regmap_write(priv->regmap, MT6359_AUDENC_ANA_CON15, 0x0000); in mt_mic_bias_0_event()
1169 return 0; in mt_mic_bias_0_event()
1180 dev_dbg(priv->dev, "%s(), event 0x%x, mic_type %d\n", in mt_mic_bias_1_event()
1188 MT6359_AUDENC_ANA_CON16, 0x0160); in mt_mic_bias_1_event()
1191 MT6359_AUDENC_ANA_CON16, 0x0060); in mt_mic_bias_1_event()
1196 0 << RG_AUDMICBIAS1LOWPEN_SFT); in mt_mic_bias_1_event()
1202 return 0; in mt_mic_bias_1_event()
1213 dev_dbg(priv->dev, "%s(), event 0x%x, mic_type %d\n", in mt_mic_bias_2_event()
1222 0xff00, 0x7700); in mt_mic_bias_2_event()
1227 0xff00, 0x1100); in mt_mic_bias_2_event()
1232 0xff00, 0x0000); in mt_mic_bias_2_event()
1243 0 << RG_AUDMICBIAS2LOWPEN_SFT); in mt_mic_bias_2_event()
1247 regmap_write(priv->regmap, MT6359_AUDENC_ANA_CON17, 0x0000); in mt_mic_bias_2_event()
1253 return 0; in mt_mic_bias_2_event()
1263 dev_dbg(priv->dev, "%s(), event = 0x%x\n", __func__, event); in mt_mtkaif_tx_event()
1276 return 0; in mt_mtkaif_tx_event()
1286 dev_dbg(priv->dev, "%s(), event = 0x%x\n", __func__, event); in mt_ul_src_dmic_event()
1293 0x0400); in mt_ul_src_dmic_event()
1296 0x0080); in mt_ul_src_dmic_event()
1299 0xfffc, 0x0000); in mt_ul_src_dmic_event()
1303 MT6359_AFE_UL_SRC_CON0_H, 0x0000); in mt_ul_src_dmic_event()
1309 return 0; in mt_ul_src_dmic_event()
1319 dev_dbg(priv->dev, "%s(), event = 0x%x\n", __func__, event); in mt_ul_src_34_dmic_event()
1325 MT6359_AFE_ADDA6_L_SRC_CON0_H, 0x0080); in mt_ul_src_34_dmic_event()
1327 0xfffc, 0x0000); in mt_ul_src_34_dmic_event()
1331 MT6359_AFE_ADDA6_L_SRC_CON0_H, 0x0000); in mt_ul_src_34_dmic_event()
1337 return 0; in mt_ul_src_34_dmic_event()
1347 dev_dbg(priv->dev, "%s(), event = 0x%x\n", __func__, event); in mt_adc_l_event()
1355 0x0); in mt_adc_l_event()
1361 return 0; in mt_adc_l_event()
1371 dev_dbg(priv->dev, "%s(), event = 0x%x\n", __func__, event); in mt_adc_r_event()
1379 0x0); in mt_adc_r_event()
1385 return 0; in mt_adc_r_event()
1395 dev_dbg(priv->dev, "%s(), event = 0x%x\n", __func__, event); in mt_adc_3_event()
1403 0x0); in mt_adc_3_event()
1409 return 0; in mt_adc_3_event()
1418 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]); in mt_pga_l_mux_event()
1422 return 0; in mt_pga_l_mux_event()
1431 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]); in mt_pga_r_mux_event()
1435 return 0; in mt_pga_r_mux_event()
1444 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]); in mt_pga_3_mux_event()
1448 return 0; in mt_pga_3_mux_event()
1480 0x1 << RG_AUDPREAMPLDCPRECHARGE_SFT); in mt_pga_l_event()
1493 0x1 << RG_AUDPREAMPLDCCEN_SFT); in mt_pga_l_event()
1500 0x0 << RG_AUDPREAMPLDCCEN_SFT); in mt_pga_l_event()
1506 return 0; in mt_pga_l_event()
1539 0x1 << RG_AUDPREAMPRDCPRECHARGE_SFT); in mt_pga_r_event()
1552 0x1 << RG_AUDPREAMPRDCCEN_SFT); in mt_pga_r_event()
1559 0x0 << RG_AUDPREAMPRDCCEN_SFT); in mt_pga_r_event()
1565 return 0; in mt_pga_r_event()
1595 0x1 << RG_AUDPREAMP3DCPRECHARGE_SFT); in mt_pga_3_event()
1608 0x1 << RG_AUDPREAMP3DCCEN_SFT); in mt_pga_3_event()
1615 0x0 << RG_AUDPREAMP3DCCEN_SFT); in mt_pga_3_event()
1621 return 0; in mt_pga_3_event()
1638 return 0; in mt_delay_250_event()
1654 return 0; in mt_delay_100_event()
1675 return 0; in mt_hp_pull_down_event()
1698 return 0; in mt_hp_mute_event()
1712 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON10, 0x0000); in mt_hp_damp_event()
1718 return 0; in mt_hp_damp_event()
1733 0x1 << RG_AUDREFN_DERES_EN_VAUDP32_SFT); in mt_esd_resist_event()
1739 RG_AUDREFN_DERES_EN_VAUDP32_MASK_SFT, 0x0); in mt_esd_resist_event()
1745 return 0; in mt_esd_resist_event()
1759 0xfffd, 0x0006); in mt_sdm_event()
1761 regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON0, 0xcba1); in mt_sdm_event()
1764 0xfffd, 0x0003); in mt_sdm_event()
1767 0xfffd, 0x000B); in mt_sdm_event()
1772 0xfffd, 0x0000); in mt_sdm_event()
1773 regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON0, 0xcba0); in mt_sdm_event()
1779 return 0; in mt_sdm_event()
1792 regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON11, 0x0006); in mt_sdm_3rd_event()
1794 regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON9, 0xcba1); in mt_sdm_3rd_event()
1796 regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON11, 0x0003); in mt_sdm_3rd_event()
1798 regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON11, 0x000b); in mt_sdm_3rd_event()
1802 regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON11, 0x0000); in mt_sdm_3rd_event()
1803 regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON9, 0xcba0); in mt_sdm_3rd_event()
1809 return 0; in mt_sdm_3rd_event()
1821 regmap_write(priv->regmap, MT6359_AFE_NCP_CFG0, 0xc800); in mt_ncp_event()
1827 return 0; in mt_ncp_event()
1835 RG_XO_AUDIO_EN_M_SFT, 0, NULL, 0),
1838 RG_LDO_VAUD18_EN_SFT, 0, NULL, 0),
1841 RG_AUDGLB_PWRDN_VA32_SFT, 1, NULL, 0),
1844 RG_CLKSQ_EN_SFT, 0, NULL, SND_SOC_DAPM_PRE_PMU),
1847 RG_AUDNCP_CK_PDN_SFT, 1, NULL, 0),
1850 RG_ZCD13M_CK_PDN_SFT, 1, NULL, 0),
1857 RG_AUDIF_CK_PDN_SFT, 1, NULL, 0),
1866 PDN_DAC_CTL_SFT, 1, NULL, 0),
1869 PDN_ADC_CTL_SFT, 1, NULL, 0),
1872 PDN_ADDA6_ADC_CTL_SFT, 1, NULL, 0),
1875 PDN_I2S_DL_CTL_SFT, 1, NULL, 0),
1878 PWR_CLK_DIS_CTL_SFT, 1, NULL, 0),
1881 PDN_AFE_TESTMODEL_CTL_SFT, 1, NULL, 0),
1884 PDN_RESERVED_SFT, 1, NULL, 0),
1887 SND_SOC_NOPM, 0, 0,
1891 SND_SOC_NOPM, 0, 0,
1898 CCI_AFIFO_CLK_PWDB_SFT, 0,
1899 NULL, 0),
1903 RG_NCP_ON_SFT, 0,
1908 0, 0, NULL, 0),
1910 0, 0, NULL, 0),
1912 0, 0, NULL, 0),
1916 MT6359_AFE_UL_DL_CON0, AFE_ON_SFT, 0,
1917 NULL, 0),
1920 SND_SOC_DAPM_AIF_IN("AIF_RX", "AIF1 Playback", 0,
1921 SND_SOC_NOPM, 0, 0),
1923 SND_SOC_DAPM_AIF_IN("AIF2_RX", "AIF2 Playback", 0,
1924 SND_SOC_NOPM, 0, 0),
1928 DL_2_SRC_ON_TMP_CTL_PRE_SFT, 0,
1929 NULL, 0),
1933 0, 0, NULL, 0),
1937 0, 0,
1942 RG_LCLDO_DEC_EN_VA32_SFT, 0,
1943 NULL, 0),
1946 RG_LCLDO_DEC_REMOTE_SENSE_VA18_SFT, 0,
1947 NULL, 0),
1950 RG_NVREG_EN_VAUDP32_SFT, 0,
1955 NULL, 0),
1958 SND_SOC_DAPM_MUX("DAC In Mux", SND_SOC_NOPM, 0, 0, &dac_in_mux_control),
1960 SND_SOC_DAPM_DAC("DACL", NULL, SND_SOC_NOPM, 0, 0),
1962 SND_SOC_DAPM_DAC("DACR", NULL, SND_SOC_NOPM, 0, 0),
1964 SND_SOC_DAPM_DAC("DAC_3RD", NULL, SND_SOC_NOPM, 0, 0),
1967 SND_SOC_DAPM_MUX_E("HP Mux", SND_SOC_NOPM, 0, 0,
1973 0, 0, NULL, 0),
1976 0, 0,
1981 0, 0,
1986 0, 0,
1991 SND_SOC_DAPM_MUX_E("RCV Mux", SND_SOC_NOPM, 0, 0,
1997 SND_SOC_DAPM_MUX_E("LOL Mux", SND_SOC_NOPM, 0, 0,
2012 SGEN_DAC_EN_CTL_SFT, 0, NULL, 0),
2018 DL_2_SRC_ON_TMP_CTL_PRE_SFT, 0, NULL, 0),
2023 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0,
2024 SND_SOC_NOPM, 0, 0),
2025 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0,
2026 SND_SOC_NOPM, 0, 0),
2029 SND_SOC_NOPM, 0, 0,
2034 SND_SOC_NOPM, 0, 0,
2039 SND_SOC_DAPM_MUX("AIF Out Mux", SND_SOC_NOPM, 0, 0,
2042 SND_SOC_DAPM_MUX("AIF2 Out Mux", SND_SOC_NOPM, 0, 0,
2045 SND_SOC_DAPM_SUPPLY("AIFTX_Supply", SND_SOC_NOPM, 0, 0, NULL, 0),
2048 SND_SOC_NOPM, 0, 0,
2054 UL_SRC_ON_TMP_CTL_SFT, 0,
2055 NULL, 0),
2058 SND_SOC_NOPM, 0, 0,
2064 ADDA6_UL_SRC_ON_TMP_CTL_SFT, 0,
2065 NULL, 0),
2068 SND_SOC_NOPM, 0, 0,
2072 SND_SOC_DAPM_MUX("MISO0_MUX", SND_SOC_NOPM, 0, 0, &miso0_mux_control),
2073 SND_SOC_DAPM_MUX("MISO1_MUX", SND_SOC_NOPM, 0, 0, &miso1_mux_control),
2074 SND_SOC_DAPM_MUX("MISO2_MUX", SND_SOC_NOPM, 0, 0, &miso2_mux_control),
2076 SND_SOC_DAPM_MUX("UL_SRC_MUX", SND_SOC_NOPM, 0, 0,
2078 SND_SOC_DAPM_MUX("UL2_SRC_MUX", SND_SOC_NOPM, 0, 0,
2081 SND_SOC_DAPM_MUX("DMIC0_MUX", SND_SOC_NOPM, 0, 0, &dmic0_mux_control),
2082 SND_SOC_DAPM_MUX("DMIC1_MUX", SND_SOC_NOPM, 0, 0, &dmic1_mux_control),
2083 SND_SOC_DAPM_MUX("DMIC2_MUX", SND_SOC_NOPM, 0, 0, &dmic2_mux_control),
2085 SND_SOC_DAPM_MUX_E("ADC_L_Mux", SND_SOC_NOPM, 0, 0,
2086 &adc_left_mux_control, NULL, 0),
2087 SND_SOC_DAPM_MUX_E("ADC_R_Mux", SND_SOC_NOPM, 0, 0,
2088 &adc_right_mux_control, NULL, 0),
2089 SND_SOC_DAPM_MUX_E("ADC_3_Mux", SND_SOC_NOPM, 0, 0,
2090 &adc_3_mux_control, NULL, 0),
2092 SND_SOC_DAPM_ADC("ADC_L", NULL, SND_SOC_NOPM, 0, 0),
2093 SND_SOC_DAPM_ADC("ADC_R", NULL, SND_SOC_NOPM, 0, 0),
2094 SND_SOC_DAPM_ADC("ADC_3", NULL, SND_SOC_NOPM, 0, 0),
2098 RG_AUDADCLPWRUP_SFT, 0,
2103 RG_AUDADCRPWRUP_SFT, 0,
2108 RG_AUDADC3PWRUP_SFT, 0,
2112 SND_SOC_DAPM_MUX_E("PGA_L_Mux", SND_SOC_NOPM, 0, 0,
2116 SND_SOC_DAPM_MUX_E("PGA_R_Mux", SND_SOC_NOPM, 0, 0,
2120 SND_SOC_DAPM_MUX_E("PGA_3_Mux", SND_SOC_NOPM, 0, 0,
2125 SND_SOC_DAPM_PGA("PGA_L", SND_SOC_NOPM, 0, 0, NULL, 0),
2126 SND_SOC_DAPM_PGA("PGA_R", SND_SOC_NOPM, 0, 0, NULL, 0),
2127 SND_SOC_DAPM_PGA("PGA_3", SND_SOC_NOPM, 0, 0, NULL, 0),
2131 RG_AUDPREAMPLON_SFT, 0,
2138 RG_AUDPREAMPRON_SFT, 0,
2145 RG_AUDPREAMP3ON_SFT, 0,
2164 RG_AUDPWDBMICBIAS0_SFT, 0,
2169 RG_AUDPWDBMICBIAS1_SFT, 0,
2174 RG_AUDPWDBMICBIAS2_SFT, 0,
2181 RG_AUDDIGMICEN_SFT, 0,
2182 NULL, 0),
2185 RG_AUDDIGMIC1EN_SFT, 0,
2186 NULL, 0),
2201 return 0; in mt_dcc_clk_connect()
2433 return 0; in mt6359_codec_dai_hw_params()
2448 return 0; in mt6359_codec_dai_startup()
2536 0x1 << RG_XO_AUDIO_EN_M_SFT, in mt6359_codec_init_reg()
2537 0x1 << RG_XO_AUDIO_EN_M_SFT); in mt6359_codec_init_reg()
2544 0x0); in mt6359_codec_init_reg()
2549 0x1 << RG_AUDHPLSCDISABLE_VAUDP32_SFT); in mt6359_codec_init_reg()
2552 0x1 << RG_AUDHPRSCDISABLE_VAUDP32_SFT); in mt6359_codec_init_reg()
2556 0x1 << RG_AUDHSSCDISABLE_VAUDP32_SFT); in mt6359_codec_init_reg()
2560 0x1 << RG_AUDLOLSCDISABLE_VAUDP32_SFT); in mt6359_codec_init_reg()
2567 priv->hp_hifi_mode = 0; in mt6359_codec_init_reg()
2574 0x1 << RG_XO_AUDIO_EN_M_SFT, in mt6359_codec_init_reg()
2575 0x0 << RG_XO_AUDIO_EN_M_SFT); in mt6359_codec_init_reg()
2577 return 0; in mt6359_codec_init_reg()
2594 static const DECLARE_TLV_DB_SCALE(hp_playback_tlv, -2200, 100, 0);
2595 static const DECLARE_TLV_DB_SCALE(playback_tlv, -1000, 100, 0);
2596 static const DECLARE_TLV_DB_SCALE(capture_tlv, 0, 600, 0);
2601 MT6359_ZCD_CON2, 0, 7, 0x1E, 0,
2605 MT6359_ZCD_CON1, 0, 7, 0x12, 0,
2608 MT6359_ZCD_CON3, 0, 0x12, 0,
2613 MT6359_AUDENC_ANA_CON0, RG_AUDPREAMPLGAIN_SFT, 4, 0,
2616 MT6359_AUDENC_ANA_CON1, RG_AUDPREAMPRGAIN_SFT, 4, 0,
2619 MT6359_AUDENC_ANA_CON2, RG_AUDPREAMP3GAIN_SFT, 4, 0,
2650 priv->dmic_one_wire_mode = 0; in mt6359_parse_dt()
2653 ret = of_property_read_u32(np, "mediatek,mic-type-0", in mt6359_parse_dt()
2656 dev_warn(priv->dev, "%s() failed to read mic-type-0\n", in mt6359_parse_dt()
2677 return 0; in mt6359_parse_dt()
2741 return 0; in mt6359_platform_driver_remove()