Lines Matching +full:10 +full:- +full:14
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * rt5640.h -- RT5640 ALSA SoC audio driver
14 #include <dt-bindings/sound/rt5640.h>
21 /* I/O - Output */
26 /* I/O - Input */
30 /* I/O - ADC/DAC/DMIC */
37 /* Mixer - D-D */
47 /* Mixer - ADC */
52 /* Mixer - DAC */
77 /* Format - ADC/DAC */
83 /* Function - Analog */
101 /* Function - Digital */
184 #define RT5640_VOL_L_MUTE (0x1 << 14)
185 #define RT5640_VOL_L_SFT 14
256 #define RT5640_ADC_L_BST_MASK (0x3 << 14)
257 #define RT5640_ADC_L_BST_SFT 14
260 #define RT5640_ADC_COMP_MASK (0x3 << 10)
261 #define RT5640_ADC_COMP_SFT 10
264 #define RT5640_M_ADC_L1 (0x1 << 14)
265 #define RT5640_M_ADC_L1_SFT 14
272 #define RT5640_ADC_2_SRC_MASK (0x3 << 10)
273 #define RT5640_ADC_2_SRC_SFT 10
274 #define RT5640_ADC_2_SRC_DMIC1 (0x0 << 10)
275 #define RT5640_ADC_2_SRC_DMIC2 (0x1 << 10)
276 #define RT5640_ADC_2_SRC_DACMIX (0x2 << 10)
283 #define RT5640_M_MONO_ADC_L1 (0x1 << 14)
284 #define RT5640_M_MONO_ADC_L1_SFT 14
291 #define RT5640_MONO_ADC_L2_SRC_MASK (0x3 << 10)
292 #define RT5640_MONO_ADC_L2_SRC_SFT 10
293 #define RT5640_MONO_ADC_L2_SRC_DMIC_L1 (0x0 << 10)
294 #define RT5640_MONO_ADC_L2_SRC_DMIC_L2 (0x1 << 10)
295 #define RT5640_MONO_ADC_L2_SRC_DACMIXL (0x2 << 10)
313 #define RT5640_M_IF1_DAC_L (0x1 << 14)
314 #define RT5640_M_IF1_DAC_L_SFT 14
321 #define RT5640_M_DAC_L1 (0x1 << 14)
322 #define RT5640_M_DAC_L1_SFT 14
329 #define RT5640_M_ANC_DAC_L (0x1 << 10)
330 #define RT5640_M_ANC_DAC_L_SFT 10
343 #define RT5640_M_DAC_L1_MONO_L (0x1 << 14)
344 #define RT5640_M_DAC_L1_MONO_L_SFT 14
351 #define RT5640_M_DAC_R2_MONO_L (0x1 << 10)
352 #define RT5640_M_DAC_R2_MONO_L_SFT 10
371 #define RT5640_STO_L_DAC_L_VOL_MASK (0x1 << 14)
372 #define RT5640_STO_L_DAC_L_VOL_SFT 14
379 #define RT5640_STO_R_DAC_R_VOL_MASK (0x1 << 10)
380 #define RT5640_STO_R_DAC_R_VOL_SFT 10
391 #define RT5640_TXDP_SRC_MASK (0x1 << 14)
392 #define RT5640_TXDP_SRC_SFT 14
393 #define RT5640_TXDP_SRC_NOR (0x0 << 14)
394 #define RT5640_TXDP_SRC_DIV3 (0x1 << 14)
397 #define RT5640_DAC_L2_SEL_MASK (0x3 << 14)
398 #define RT5640_DAC_L2_SEL_SFT 14
399 #define RT5640_DAC_L2_SEL_IF2 (0x0 << 14)
400 #define RT5640_DAC_L2_SEL_IF3 (0x1 << 14)
401 #define RT5640_DAC_L2_SEL_TXDC (0x2 << 14)
402 #define RT5640_DAC_L2_SEL_BASS (0x3 << 14)
412 #define RT5640_IF2_ADC_R_SEL_MASK (0x1 << 10)
413 #define RT5640_IF2_ADC_R_SEL_SFT 10
414 #define RT5640_IF2_ADC_R_SEL_TXDP (0x0 << 10)
415 #define RT5640_IF2_ADC_R_SEL_PASS (0x1 << 10)
442 #define RT5640_IF1_DAC_SEL_MASK (0x3 << 14)
443 #define RT5640_IF1_DAC_SEL_SFT 14
444 #define RT5640_IF1_DAC_SEL_NOR (0x0 << 14)
445 #define RT5640_IF1_DAC_SEL_SWAP (0x1 << 14)
446 #define RT5640_IF1_DAC_SEL_L2R (0x2 << 14)
447 #define RT5640_IF1_DAC_SEL_R2L (0x3 << 14)
454 #define RT5640_IF2_DAC_SEL_MASK (0x3 << 10)
455 #define RT5640_IF2_DAC_SEL_SFT 10
456 #define RT5640_IF2_DAC_SEL_NOR (0x0 << 10)
457 #define RT5640_IF2_DAC_SEL_SWAP (0x1 << 10)
458 #define RT5640_IF2_DAC_SEL_L2R (0x2 << 10)
459 #define RT5640_IF2_DAC_SEL_R2L (0x3 << 10)
482 #define RT5640_G_IN_L_RM_L_MASK (0x7 << 10)
483 #define RT5640_G_IN_L_RM_L_SFT 10
494 #define RT5640_G_OM_L_RM_L_MASK (0x7 << 10)
495 #define RT5640_G_OM_L_RM_L_SFT 10
514 #define RT5640_G_IN_R_RM_R_MASK (0x7 << 10)
515 #define RT5640_G_IN_R_RM_R_SFT 10
526 #define RT5640_G_OM_R_RM_R_MASK (0x7 << 10)
527 #define RT5640_G_OM_R_RM_R_SFT 10
546 #define RT5640_M_DAC1_HM (0x1 << 14)
547 #define RT5640_M_DAC1_HM_SFT 14
554 #define RT5640_G_RM_L_SM_L_MASK (0x3 << 14)
555 #define RT5640_G_RM_L_SM_L_SFT 14
558 #define RT5640_G_DAC_L1_SM_L_MASK (0x3 << 10)
559 #define RT5640_G_DAC_L1_SM_L_SFT 10
576 #define RT5640_G_RM_R_SM_R_MASK (0x3 << 14)
577 #define RT5640_G_RM_R_SM_R_SFT 14
580 #define RT5640_G_DAC_R1_SM_R_MASK (0x3 << 10)
581 #define RT5640_G_DAC_R1_SM_R_SFT 10
600 #define RT5640_M_DAC_L1_SPM_L (0x1 << 14)
601 #define RT5640_M_DAC_L1_SPM_L_SFT 14
624 #define RT5640_M_DAC_L2_MM (0x1 << 14)
625 #define RT5640_M_DAC_L2_MM_SFT 14
632 #define RT5640_G_MONOMIX_MASK (0x1 << 10)
633 #define RT5640_G_MONOMIX_SFT 10
638 #define RT5640_G_BST2_OM_L_MASK (0x7 << 10)
639 #define RT5640_G_BST2_OM_L_SFT 10
650 #define RT5640_G_DAC_L2_OM_L_MASK (0x7 << 10)
651 #define RT5640_G_DAC_L2_OM_L_SFT 10
678 #define RT5640_G_BST2_OM_R_MASK (0x7 << 10)
679 #define RT5640_G_BST2_OM_R_SFT 10
690 #define RT5640_G_DAC_R2_OM_R_MASK (0x7 << 10)
691 #define RT5640_G_DAC_R2_OM_R_SFT 10
718 #define RT5640_M_DAC_R1_LM (0x1 << 14)
719 #define RT5640_M_DAC_R1_LM_SFT 14
730 #define RT5640_PWR_I2S2 (0x1 << 14)
731 #define RT5640_PWR_I2S2_BIT 14
750 #define RT5640_PWR_ADC_MF_L (0x1 << 14)
751 #define RT5640_PWR_ADC_MF_L_BIT 14
760 #define RT5640_PWR_FV1 (0x1 << 14)
761 #define RT5640_PWR_FV1_BIT 14
768 #define RT5640_PWR_MM (0x1 << 10)
769 #define RT5640_PWR_MM_BIT 10
788 #define RT5640_PWR_BST2 (0x1 << 14)
789 #define RT5640_PWR_BST2_BIT 14
802 #define RT5640_PWR_OM_R (0x1 << 14)
803 #define RT5640_PWR_OM_R_BIT 14
810 #define RT5640_PWR_RM_R (0x1 << 10)
811 #define RT5640_PWR_RM_R_BIT 10
816 #define RT5640_PWR_SV_R (0x1 << 14)
817 #define RT5640_PWR_SV_R_BIT 14
824 #define RT5640_PWR_HV_R (0x1 << 10)
825 #define RT5640_PWR_HV_R_BIT 10
838 #define RT5640_I2S_O_CP_MASK (0x3 << 10)
839 #define RT5640_I2S_O_CP_SFT 10
840 #define RT5640_I2S_O_CP_OFF (0x0 << 10)
841 #define RT5640_I2S_O_CP_U_LAW (0x1 << 10)
842 #define RT5640_I2S_O_CP_A_LAW (0x2 << 10)
928 #define RT5640_DAC_L_OSR_MASK (0x3 << 14)
929 #define RT5640_DAC_L_OSR_SFT 14
930 #define RT5640_DAC_L_OSR_128 (0x0 << 14)
931 #define RT5640_DAC_L_OSR_64 (0x1 << 14)
932 #define RT5640_DAC_L_OSR_32 (0x2 << 14)
933 #define RT5640_DAC_L_OSR_16 (0x3 << 14)
942 #define RT5640_ADHPF_EN (0x1 << 10)
943 #define RT5640_ADHPF_EN_SFT 10
950 #define RT5640_DMIC_2_EN_MASK (0x1 << 14)
951 #define RT5640_DMIC_2_EN_SFT 14
952 #define RT5640_DMIC_2_DIS (0x0 << 14)
953 #define RT5640_DMIC_2_EN (0x1 << 14)
966 #define RT5640_DMIC_2_DP_MASK (0x1 << 10)
967 #define RT5640_DMIC_2_DP_SFT 10
968 #define RT5640_DMIC_2_DP_GPIO4 (0x0 << 10)
969 #define RT5640_DMIC_2_DP_IN1N (0x1 << 10)
982 #define RT5640_SCLK_SRC_MASK (0x3 << 14)
983 #define RT5640_SCLK_SRC_SFT 14
984 #define RT5640_SCLK_SRC_MCLK (0x0 << 14)
985 #define RT5640_SCLK_SRC_PLL1 (0x1 << 14)
986 #define RT5640_SCLK_SRC_RCCLK (0x2 << 14)
1020 #define RT5640_M1_T_MASK (0x1 << 14)
1021 #define RT5640_M1_T_SFT 14
1022 #define RT5640_M1_T_I2S2 (0x0 << 14)
1023 #define RT5640_M1_T_I2S2_D3 (0x1 << 14)
1046 #define RT5640_MDA_R_M_MASK (0x1 << 14)
1047 #define RT5640_MDA_R_M_SFT 14
1048 #define RT5640_MDA_R_M_NOR (0x0 << 14)
1049 #define RT5640_MDA_R_M_ASYN (0x1 << 14)
1093 #define RT5640_HP_OVCD_MASK (0x1 << 10)
1094 #define RT5640_HP_OVCD_SFT 10
1095 #define RT5640_HP_OVCD_DIS (0x0 << 10)
1096 #define RT5640_HP_OVCD_EN (0x1 << 10)
1123 #define RT5640_CLSD_SCH_MASK (0x1 << 10)
1124 #define RT5640_CLSD_SCH_SFT 10
1125 #define RT5640_CLSD_SCH_L (0x0 << 10)
1126 #define RT5640_CLSD_SCH_S (0x1 << 10)
1187 #define RT5640_FAST_UPDN_MASK (0x1 << 10)
1188 #define RT5640_FAST_UPDN_SFT 10
1189 #define RT5640_FAST_UPDN_DIS (0x0 << 10)
1190 #define RT5640_FAST_UPDN_EN (0x1 << 10)
1231 #define RT5640_OSW_R_MASK (0x1 << 10)
1232 #define RT5640_OSW_R_SFT 10
1233 #define RT5640_OSW_R_DIS (0x0 << 10)
1234 #define RT5640_OSW_R_EN (0x1 << 10)
1252 #define RT5640_SPK_AG_MASK (0x1 << 14)
1253 #define RT5640_SPK_AG_SFT 14
1254 #define RT5640_SPK_AG_DIS (0x0 << 14)
1255 #define RT5640_SPK_AG_EN (0x1 << 14)
1262 #define RT5640_MIC2_BS_MASK (0x1 << 14)
1263 #define RT5640_MIC2_BS_SFT 14
1264 #define RT5640_MIC2_BS_9AV (0x0 << 14)
1265 #define RT5640_MIC2_BS_75AV (0x1 << 14)
1306 #define RT5640_EQ_UPD (0x1 << 14)
1307 #define RT5640_EQ_UPD_BIT 14
1368 #define RT5640_DRC_AGC_MASK (0x1 << 14)
1369 #define RT5640_DRC_AGC_SFT 14
1370 #define RT5640_DRC_AGC_DIS (0x0 << 14)
1371 #define RT5640_DRC_AGC_EN (0x1 << 14)
1424 #define RT5640_ANC_MASK (0x1 << 14)
1425 #define RT5640_ANC_SFT 14
1426 #define RT5640_ANC_DIS (0x0 << 14)
1427 #define RT5640_ANC_EN (0x1 << 14)
1438 #define RT5640_ANC_CLK_MASK (0x1 << 10)
1439 #define RT5640_ANC_CLK_SFT 10
1440 #define RT5640_ANC_CLK_ANC (0x0 << 10)
1441 #define RT5640_ANC_CLK_REG (0x1 << 10)
1491 #define RT5640_JD_HP_TRG_MASK (0x1 << 10)
1492 #define RT5640_JD_HP_TRG_SFT 10
1493 #define RT5640_JD_HP_TRG_LO (0x0 << 10)
1494 #define RT5640_JD_HP_TRG_HI (0x1 << 10)
1563 #define RT5640_IRQ_OT_MASK (0x1 << 14)
1564 #define RT5640_IRQ_OT_SFT 14
1565 #define RT5640_IRQ_OT_BP (0x0 << 14)
1566 #define RT5640_IRQ_OT_NOR (0x1 << 14)
1579 #define RT5640_OT_P_MASK (0x1 << 10)
1580 #define RT5640_OT_P_SFT 10
1581 #define RT5640_OT_P_NOR (0x0 << 10)
1582 #define RT5640_OT_P_INV (0x1 << 10)
1589 #define RT5640_IRQ_MB2_OC_MASK (0x1 << 14)
1590 #define RT5640_IRQ_MB2_OC_SFT 14
1591 #define RT5640_IRQ_MB2_OC_BP (0x0 << 14)
1592 #define RT5640_IRQ_MB2_OC_NOR (0x1 << 14)
1597 #define RT5640_MB2_OC_STKY_MASK (0x1 << 10)
1598 #define RT5640_MB2_OC_STKY_SFT 10
1599 #define RT5640_MB2_OC_STKY_DIS (0x0 << 10)
1600 #define RT5640_MB2_OC_STKY_EN (0x1 << 10)
1626 #define RT5640_GP2_PIN_MASK (0x1 << 14)
1627 #define RT5640_GP2_PIN_SFT 14
1628 #define RT5640_GP2_PIN_GPIO2 (0x0 << 14)
1629 #define RT5640_GP2_PIN_DMIC1_SCL (0x1 << 14)
1639 #define RT5640_DP_SIG_MASK (0x1 << 10)
1640 #define RT5640_DP_SIG_SFT 10
1641 #define RT5640_DP_SIG_TEST (0x0 << 10)
1642 #define RT5640_DP_SIG_AP (0x1 << 10)
1653 #define RT5640_GP4_OUT_MASK (0x1 << 10)
1654 #define RT5640_GP4_OUT_SFT 10
1655 #define RT5640_GP4_OUT_LO (0x0 << 10)
1656 #define RT5640_GP4_OUT_HI (0x1 << 10)
1698 /* FM34-500 Register Control 1 (0xc4) */
1701 /* FM34-500 Register Control 2 (0xc5) */
1704 /* FM34-500 Register Control 3 (0xc6) */
1707 #define RT5640_DSP_DS_MASK (0x1 << 14)
1708 #define RT5640_DSP_DS_SFT 14
1709 #define RT5640_DSP_DS_FM3010 (0x1 << 14)
1710 #define RT5640_DSP_DS_TEMP (0x1 << 14)
1721 #define RT5640_DSP_RST_PIN_MASK (0x1 << 10)
1722 #define RT5640_DSP_RST_PIN_SFT 10
1723 #define RT5640_DSP_RST_PIN_LO (0x0 << 10)
1724 #define RT5640_DSP_RST_PIN_HI (0x1 << 10)
1743 #define RT5640_SEQ2_ST_MASK (0x1 << 10) /*RO*/
1744 #define RT5640_SEQ2_ST_SFT 10
1745 #define RT5640_SEQ2_ST_RUN (0x0 << 10)
1746 #define RT5640_SEQ2_ST_FIN (0x1 << 10)
1793 #define RT5640_SCB_MASK (0x1 << 14)
1794 #define RT5640_SCB_SFT 14
1795 #define RT5640_SCB_DIS (0x0 << 14)
1796 #define RT5640_SCB_EN (0x1 << 14)
1823 #define RT5640_M_MP3_R_MASK (0x1 << 14)
1824 #define RT5640_M_MP3_R_SFT 14
1855 #define RT5640_3D_HP_MASK (0x1 << 14)
1856 #define RT5640_3D_HP_SFT 14
1857 #define RT5640_3D_HP_DIS (0x0 << 14)
1858 #define RT5640_3D_HP_EN (0x1 << 14)
1865 #define RT5640_3D_HP_M_MASK (0x1 << 10)
1866 #define RT5640_3D_HP_M_SFT 10
1867 #define RT5640_3D_HP_M_SUR (0x0 << 10)
1868 #define RT5640_3D_HP_M_FRO (0x1 << 10)
1905 #define RT5640_DC_CAL_M_MASK (0x1 << 10)
1906 #define RT5640_DC_CAL_M_SFT 10
1907 #define RT5640_DC_CAL_M_CAL (0x0 << 10)
1908 #define RT5640_DC_CAL_M_NOR (0x1 << 10)
1942 #define RT5640_SPO_SV_MASK (0x1 << 14)
1943 #define RT5640_SPO_SV_SFT 14
1944 #define RT5640_SPO_SV_DIS (0x0 << 14)
1945 #define RT5640_SPO_SV_EN (0x1 << 14)
1958 #define RT5640_ZCD_MASK (0x1 << 10)
1959 #define RT5640_ZCD_SFT 10
1960 #define RT5640_ZCD_PD (0x0 << 10)
1961 #define RT5640_ZCD_PU (0x1 << 10)
2015 #define RT5640_WND_FC_NW_MASK (0x3f << 10)
2016 #define RT5640_WND_FC_NW_SFT 10
2035 #define RT5640_WND_WIND_MASK (0x1 << 13) /* Read-Only */
2037 #define RT5640_WND_STRONG_MASK (0x1 << 12) /* Read-Only */
2046 #define RT5640_DP_ATT_MASK (0x3 << 14)
2047 #define RT5640_DP_ATT_SFT 14
2048 #define RT5640_DP_SPK_MASK (0x1 << 10)
2049 #define RT5640_DP_SPK_SFT 10
2050 #define RT5640_DP_SPK_DIS (0x0 << 10)
2051 #define RT5640_DP_SPK_EN (0x1 << 10)