Lines Matching +full:10 +full:- +full:14
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * rt5645.h -- RT5645 ALSA SoC audio driver
19 /* I/O - Output */
24 /* I/O - Input */
32 /* I/O - ADC/DAC/DMIC */
40 /* Mixer - D-D */
49 /* Mixer - PDM */
51 /* Mixer - ADC */
56 /* Mixer - DAC */
94 /* Format - ADC/DAC */
101 /* Format - TDM Control */
107 /* Function - Analog */
123 /* Function - Digital */
221 #define RT5645_VOL_L_MUTE (0x1 << 14)
222 #define RT5645_VOL_L_SFT 14
250 #define RT5645_CBJ_TIE_G_R (0x1 << 14)
309 #define RT5645_STO1_ADC_L_BST_MASK (0x3 << 14)
310 #define RT5645_STO1_ADC_L_BST_SFT 14
313 #define RT5645_STO1_ADC_COMP_MASK (0x3 << 10)
314 #define RT5645_STO1_ADC_COMP_SFT 10
317 #define RT5645_MONO_ADC_L_BST_MASK (0x3 << 14)
318 #define RT5645_MONO_ADC_L_BST_SFT 14
321 #define RT5645_MONO_ADC_COMP_MASK (0x3 << 10)
322 #define RT5645_MONO_ADC_COMP_SFT 10
329 #define RT5645_M_ADC_L1 (0x1 << 14)
330 #define RT5645_M_ADC_L1_SFT 14
349 #define RT5645_M_MONO_ADC_L1 (0x1 << 14)
350 #define RT5645_M_MONO_ADC_L1_SFT 14
377 #define RT5645_M_DAC1_L (0x1 << 14)
378 #define RT5645_M_DAC1_L_SFT 14
379 #define RT5645_DAC1_R_SEL_MASK (0x3 << 10)
380 #define RT5645_DAC1_R_SEL_SFT 10
381 #define RT5645_DAC1_R_SEL_IF1 (0x0 << 10)
382 #define RT5645_DAC1_R_SEL_IF2 (0x1 << 10)
383 #define RT5645_DAC1_R_SEL_IF3 (0x2 << 10)
384 #define RT5645_DAC1_R_SEL_IF4 (0x3 << 10)
397 #define RT5645_M_DAC_L1 (0x1 << 14)
398 #define RT5645_M_DAC_L1_SFT 14
405 #define RT5645_M_ANC_DAC_L (0x1 << 10)
406 #define RT5645_M_ANC_DAC_L_SFT 10
427 #define RT5645_M_DAC_L1_MONO_L (0x1 << 14)
428 #define RT5645_M_DAC_L1_MONO_L_SFT 14
435 #define RT5645_M_DAC_R2_MONO_L (0x1 << 10)
436 #define RT5645_M_DAC_R2_MONO_L_SFT 10
455 #define RT5645_STO_L_DAC_L_VOL_MASK (0x1 << 14)
456 #define RT5645_STO_L_DAC_L_VOL_SFT 14
463 #define RT5645_STO_R_DAC_R_VOL_MASK (0x1 << 10)
464 #define RT5645_STO_R_DAC_R_VOL_SFT 10
489 #define RT5645_IF2_DAC_SEL_MASK (0x3 << 10)
490 #define RT5645_IF2_DAC_SEL_SFT 10
503 #define RT5645_M_PDM1_L (0x1 << 14)
504 #define RT5645_M_PDM1_L_SFT 14
511 #define RT5645_M_PDM2_L (0x1 << 10)
512 #define RT5645_M_PDM2_L_SFT 10
526 #define RT5645_G_IN_L_RM_L_MASK (0x7 << 10)
527 #define RT5645_G_IN_L_RM_L_SFT 10
538 #define RT5645_G_OM_L_RM_L_MASK (0x7 << 10)
539 #define RT5645_G_OM_L_RM_L_SFT 10
558 #define RT5645_G_IN_R_RM_R_MASK (0x7 << 10)
559 #define RT5645_G_IN_R_RM_R_SFT 10
570 #define RT5645_G_OM_R_RM_R_MASK (0x7 << 10)
571 #define RT5645_G_OM_R_RM_R_SFT 10
602 #define RT5645_M_DAC1_HM (0x1 << 14)
603 #define RT5645_M_DAC1_HM_SFT 14
609 #define RT5645_G_RM_L_SM_L_MASK (0x3 << 14)
610 #define RT5645_G_RM_L_SM_L_SFT 14
613 #define RT5645_G_DAC_L1_SM_L_MASK (0x3 << 10)
614 #define RT5645_G_DAC_L1_SM_L_SFT 10
631 #define RT5645_G_RM_R_SM_R_MASK (0x3 << 14)
632 #define RT5645_G_RM_R_SM_R_SFT 14
635 #define RT5645_G_DAC_R1_SM_R_MASK (0x3 << 10)
636 #define RT5645_G_DAC_R1_SM_R_SFT 10
655 #define RT5645_M_DAC_R1_SPM_L (0x1 << 14)
656 #define RT5645_M_DAC_R1_SPM_L_SFT 14
675 #define RT5645_G_MONOMIX_MASK (0x1 << 10)
676 #define RT5645_G_MONOMIX_SFT 10
695 #define RT5645_G_BST2_OM_L_MASK (0x7 << 10)
696 #define RT5645_G_BST2_OM_L_SFT 10
707 #define RT5645_G_DAC_L2_OM_L_MASK (0x7 << 10)
708 #define RT5645_G_DAC_L2_OM_L_SFT 10
727 #define RT5645_G_BST2_OM_R_MASK (0x7 << 10)
728 #define RT5645_G_BST2_OM_R_SFT 10
739 #define RT5645_G_DAC_R2_OM_R_MASK (0x7 << 10)
740 #define RT5645_G_DAC_R2_OM_R_SFT 10
759 #define RT5645_M_DAC_R1_LM (0x1 << 14)
760 #define RT5645_M_DAC_R1_LM_SFT 14
771 #define RT5645_PWR_I2S2 (0x1 << 14)
772 #define RT5645_PWR_I2S2_BIT 14
797 #define RT5645_PWR_ADC_MF_L (0x1 << 14)
798 #define RT5645_PWR_ADC_MF_L_BIT 14
805 #define RT5645_PWR_DAC_MF_L (0x1 << 10)
806 #define RT5645_PWR_DAC_MF_L_BIT 10
821 #define RT5645_PWR_FV1 (0x1 << 14)
822 #define RT5645_PWR_FV1_BIT 14
829 #define RT5645_PWR_MA (0x1 << 10)
830 #define RT5645_PWR_MA_BIT 10
847 #define RT5645_PWR_BST2 (0x1 << 14)
848 #define RT5645_PWR_BST2_BIT 14
855 #define RT5645_PWR_MB2 (0x1 << 10)
856 #define RT5645_PWR_MB2_BIT 10
873 #define RT5645_PWR_OM_R (0x1 << 14)
874 #define RT5645_PWR_OM_R_BIT 14
881 #define RT5645_PWR_RM_R (0x1 << 10)
882 #define RT5645_PWR_RM_R_BIT 10
895 #define RT5645_PWR_SV_R (0x1 << 14)
896 #define RT5645_PWR_SV_R_BIT 14
899 #define RT5645_PWR_HV_R (0x1 << 10)
900 #define RT5645_PWR_HV_R_BIT 10
913 #define RT5645_I2S_O_CP_MASK (0x3 << 10)
914 #define RT5645_I2S_O_CP_SFT 10
915 #define RT5645_I2S_O_CP_OFF (0x0 << 10)
916 #define RT5645_I2S_O_CP_U_LAW (0x1 << 10)
917 #define RT5645_I2S_O_CP_A_LAW (0x2 << 10)
999 #define RT5645_DAC_L_OSR_MASK (0x3 << 14)
1000 #define RT5645_DAC_L_OSR_SFT 14
1001 #define RT5645_DAC_L_OSR_128 (0x0 << 14)
1002 #define RT5645_DAC_L_OSR_64 (0x1 << 14)
1003 #define RT5645_DAC_L_OSR_32 (0x2 << 14)
1004 #define RT5645_DAC_L_OSR_16 (0x3 << 14)
1013 #define RT5645_ADHPF_EN (0x1 << 10)
1014 #define RT5645_ADHPF_EN_SFT 10
1021 #define RT5645_DMIC_2_EN_MASK (0x1 << 14)
1022 #define RT5645_DMIC_2_EN_SFT 14
1023 #define RT5645_DMIC_2_DIS (0x0 << 14)
1024 #define RT5645_DMIC_2_EN (0x1 << 14)
1033 #define RT5645_DMIC_2_DP_MASK (0x3 << 10)
1034 #define RT5645_DMIC_2_DP_SFT 10
1035 #define RT5645_DMIC_2_DP_GPIO6 (0x0 << 10)
1036 #define RT5645_DMIC_2_DP_GPIO10 (0x1 << 10)
1037 #define RT5645_DMIC_2_DP_GPIO12 (0x2 << 10)
1038 #define RT5645_DMIC_2_DP_IN2P (0x3 << 10)
1064 #define RT5645_SCLK_SRC_MASK (0x3 << 14)
1065 #define RT5645_SCLK_SRC_SFT 14
1066 #define RT5645_SCLK_SRC_MCLK (0x0 << 14)
1067 #define RT5645_SCLK_SRC_PLL1 (0x1 << 14)
1068 #define RT5645_SCLK_SRC_RCCLK (0x2 << 14)
1103 #define RT5645_M1_T_MASK (0x1 << 14)
1104 #define RT5645_M1_T_SFT 14
1105 #define RT5645_M1_T_I2S2 (0x0 << 14)
1106 #define RT5645_M1_T_I2S2_D3 (0x1 << 14)
1149 #define RT5645_HP_OVCD_MASK (0x1 << 10)
1150 #define RT5645_HP_OVCD_SFT 10
1151 #define RT5645_HP_OVCD_DIS (0x0 << 10)
1152 #define RT5645_HP_OVCD_EN (0x1 << 10)
1179 #define RT5645_CLSD_SCH_MASK (0x1 << 10)
1180 #define RT5645_CLSD_SCH_SFT 10
1181 #define RT5645_CLSD_SCH_L (0x0 << 10)
1182 #define RT5645_CLSD_SCH_S (0x1 << 10)
1243 #define RT5645_FAST_UPDN_MASK (0x1 << 10)
1244 #define RT5645_FAST_UPDN_SFT 10
1245 #define RT5645_FAST_UPDN_DIS (0x0 << 10)
1246 #define RT5645_FAST_UPDN_EN (0x1 << 10)
1287 #define RT5645_SPK_AG_MASK (0x1 << 14)
1288 #define RT5645_SPK_AG_SFT 14
1289 #define RT5645_SPK_AG_DIS (0x0 << 14)
1290 #define RT5645_SPK_AG_EN (0x1 << 14)
1297 #define RT5645_MIC2_BS_MASK (0x1 << 14)
1298 #define RT5645_MIC2_BS_SFT 14
1299 #define RT5645_MIC2_BS_9AV (0x0 << 14)
1300 #define RT5645_MIC2_BS_75AV (0x1 << 14)
1351 #define RT5645_EQ_UPD (0x1 << 14)
1352 #define RT5645_EQ_UPD_BIT 14
1414 #define RT5645_DRC_AGC_MASK (0x1 << 14)
1415 #define RT5645_DRC_AGC_SFT 14
1416 #define RT5645_DRC_AGC_DIS (0x0 << 14)
1417 #define RT5645_DRC_AGC_EN (0x1 << 14)
1470 #define RT5645_ANC_MASK (0x1 << 14)
1471 #define RT5645_ANC_SFT 14
1472 #define RT5645_ANC_DIS (0x0 << 14)
1473 #define RT5645_ANC_EN (0x1 << 14)
1484 #define RT5645_ANC_CLK_MASK (0x1 << 10)
1485 #define RT5645_ANC_CLK_SFT 10
1486 #define RT5645_ANC_CLK_ANC (0x0 << 10)
1487 #define RT5645_ANC_CLK_REG (0x1 << 10)
1537 #define RT5645_JD_HP_TRG_MASK (0x1 << 10)
1538 #define RT5645_JD_HP_TRG_SFT 10
1539 #define RT5645_JD_HP_TRG_LO (0x0 << 10)
1540 #define RT5645_JD_HP_TRG_HI (0x1 << 10)
1609 #define RT5645_IRQ_OT_MASK (0x1 << 14)
1610 #define RT5645_IRQ_OT_SFT 14
1611 #define RT5645_IRQ_OT_BP (0x0 << 14)
1612 #define RT5645_IRQ_OT_NOR (0x1 << 14)
1625 #define RT5645_OT_P_MASK (0x1 << 10)
1626 #define RT5645_OT_P_SFT 10
1627 #define RT5645_OT_P_NOR (0x0 << 10)
1628 #define RT5645_OT_P_INV (0x1 << 10)
1640 #define RT5645_IRQ_MB2_OC_MASK (0x1 << 14)
1641 #define RT5645_IRQ_MB2_OC_SFT 14
1642 #define RT5645_IRQ_MB2_OC_BP (0x0 << 14)
1643 #define RT5645_IRQ_MB2_OC_NOR (0x1 << 14)
1670 #define RT5645_GP2_PIN_MASK (0x1 << 14)
1671 #define RT5645_GP2_PIN_SFT 14
1672 #define RT5645_GP2_PIN_GPIO2 (0x0 << 14)
1673 #define RT5645_GP2_PIN_DMIC1_SCL (0x1 << 14)
1683 #define RT5645_DP_SIG_MASK (0x1 << 10)
1684 #define RT5645_DP_SIG_SFT 10
1685 #define RT5645_DP_SIG_TEST (0x0 << 10)
1686 #define RT5645_DP_SIG_AP (0x1 << 10)
1727 #define RT5645_GP4_OUT_MASK (0x1 << 10)
1728 #define RT5645_GP4_OUT_SFT 10
1729 #define RT5645_GP4_OUT_LO (0x0 << 10)
1730 #define RT5645_GP4_OUT_HI (0x1 << 10)
1779 #define RT5645_SEQ2_ST_MASK (0x1 << 10) /*RO*/
1780 #define RT5645_SEQ2_ST_SFT 10
1781 #define RT5645_SEQ2_ST_RUN (0x0 << 10)
1782 #define RT5645_SEQ2_ST_FIN (0x1 << 10)
1829 #define RT5645_SCB_MASK (0x1 << 14)
1830 #define RT5645_SCB_SFT 14
1831 #define RT5645_SCB_DIS (0x0 << 14)
1832 #define RT5645_SCB_EN (0x1 << 14)
1860 #define RT5645_M_MP3_R_MASK (0x1 << 14)
1861 #define RT5645_M_MP3_R_SFT 14
1892 #define RT5645_3D_HP_MASK (0x1 << 14)
1893 #define RT5645_3D_HP_SFT 14
1894 #define RT5645_3D_HP_DIS (0x0 << 14)
1895 #define RT5645_3D_HP_EN (0x1 << 14)
1902 #define RT5645_3D_HP_M_MASK (0x1 << 10)
1903 #define RT5645_3D_HP_M_SFT 10
1904 #define RT5645_3D_HP_M_SUR (0x0 << 10)
1905 #define RT5645_3D_HP_M_FRO (0x1 << 10)
1942 #define RT5645_DC_CAL_M_MASK (0x1 << 10)
1943 #define RT5645_DC_CAL_M_SFT 10
1944 #define RT5645_DC_CAL_M_CAL (0x0 << 10)
1945 #define RT5645_DC_CAL_M_NOR (0x1 << 10)
1979 #define RT5645_SPO_SV_MASK (0x1 << 14)
1980 #define RT5645_SPO_SV_SFT 14
1981 #define RT5645_SPO_SV_DIS (0x0 << 14)
1982 #define RT5645_SPO_SV_EN (0x1 << 14)
1995 #define RT5645_ZCD_MASK (0x1 << 10)
1996 #define RT5645_ZCD_SFT 10
1997 #define RT5645_ZCD_PD (0x0 << 10)
1998 #define RT5645_ZCD_PU (0x1 << 10)
2040 #define RT5645_WND_FC_NW_MASK (0x3f << 10)
2041 #define RT5645_WND_FC_NW_SFT 10
2060 #define RT5645_WND_WIND_MASK (0x1 << 13) /* Read-Only */
2062 #define RT5645_WND_STRONG_MASK (0x1 << 12) /* Read-Only */
2071 #define RT5645_DP_ATT_MASK (0x3 << 14)
2072 #define RT5645_DP_ATT_SFT 14
2073 #define RT5645_DP_SPK_MASK (0x1 << 10)
2074 #define RT5645_DP_SPK_SFT 10
2075 #define RT5645_DP_SPK_DIS (0x0 << 10)
2076 #define RT5645_DP_SPK_EN (0x1 << 10)
2108 #define RT5645_IF1_ADC2_IN1_SEL (0x1 << 10)
2109 #define RT5645_IF1_ADC2_IN1_SFT 10