Lines Matching +full:imx7ulp +full:- +full:edma
1 // SPDX-License-Identifier: GPL-2.0+
5 // Copyright 2012-2015 Freescale Semiconductor, Inc.
21 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
24 #include "imx-pcm.h"
41 * fsl_sai_dir_is_synced - Check if stream is synced by the opposite stream
55 return !sai->synchronous[dir] && sai->synchronous[adir]; in fsl_sai_dir_is_synced()
61 unsigned int ofs = sai->soc_data->reg_offset; in fsl_sai_isr()
62 struct device *dev = &sai->pdev->dev; in fsl_sai_isr()
74 regmap_read(sai->regmap, FSL_SAI_TCSR(ofs), &xcsr); in fsl_sai_isr()
104 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), flags | xcsr); in fsl_sai_isr()
108 regmap_read(sai->regmap, FSL_SAI_RCSR(ofs), &xcsr); in fsl_sai_isr()
138 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), flags | xcsr); in fsl_sai_isr()
152 sai->slots = slots; in fsl_sai_set_dai_tdm_slot()
153 sai->slot_width = slot_width; in fsl_sai_set_dai_tdm_slot()
163 sai->bclk_ratio = ratio; in fsl_sai_set_dai_bclk_ratio()
172 unsigned int ofs = sai->soc_data->reg_offset; in fsl_sai_set_dai_sysclk_tr()
190 return -EINVAL; in fsl_sai_set_dai_sysclk_tr()
193 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs), in fsl_sai_set_dai_sysclk_tr()
210 dev_err(cpu_dai->dev, "Cannot set tx sysclk: %d\n", ret); in fsl_sai_set_dai_sysclk()
217 dev_err(cpu_dai->dev, "Cannot set rx sysclk: %d\n", ret); in fsl_sai_set_dai_sysclk()
226 unsigned int ofs = sai->soc_data->reg_offset; in fsl_sai_set_dai_fmt_tr()
230 if (!sai->is_lsb_first) in fsl_sai_set_dai_fmt_tr()
233 sai->is_dsp_mode = false; in fsl_sai_set_dai_fmt_tr()
262 sai->is_dsp_mode = true; in fsl_sai_set_dai_fmt_tr()
270 sai->is_dsp_mode = true; in fsl_sai_set_dai_fmt_tr()
275 return -EINVAL; in fsl_sai_set_dai_fmt_tr()
297 return -EINVAL; in fsl_sai_set_dai_fmt_tr()
305 sai->is_slave_mode = false; in fsl_sai_set_dai_fmt_tr()
308 sai->is_slave_mode = true; in fsl_sai_set_dai_fmt_tr()
312 sai->is_slave_mode = false; in fsl_sai_set_dai_fmt_tr()
316 sai->is_slave_mode = true; in fsl_sai_set_dai_fmt_tr()
319 return -EINVAL; in fsl_sai_set_dai_fmt_tr()
322 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs), in fsl_sai_set_dai_fmt_tr()
324 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs), in fsl_sai_set_dai_fmt_tr()
337 dev_err(cpu_dai->dev, "Cannot set tx format: %d\n", ret); in fsl_sai_set_dai_fmt()
343 dev_err(cpu_dai->dev, "Cannot set rx format: %d\n", ret); in fsl_sai_set_dai_fmt()
351 unsigned int ofs = sai->soc_data->reg_offset; in fsl_sai_set_bclk()
360 if (sai->is_slave_mode) in fsl_sai_set_bclk()
364 clk_rate = clk_get_rate(sai->mclk_clk[id]); in fsl_sai_set_bclk()
370 ret = clk_rate - ratio * freq; in fsl_sai_set_bclk()
379 dev_dbg(dai->dev, in fsl_sai_set_bclk()
390 sai->mclk_id[tx] = id; in fsl_sai_set_bclk()
399 dev_err(dai->dev, "failed to derive required %cx rate: %d\n", in fsl_sai_set_bclk()
401 return -EINVAL; in fsl_sai_set_bclk()
415 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(!tx, ofs), in fsl_sai_set_bclk()
417 FSL_SAI_CR2_MSEL(sai->mclk_id[tx])); in fsl_sai_set_bclk()
418 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(!tx, ofs), in fsl_sai_set_bclk()
419 FSL_SAI_CR2_DIV_MASK, savediv - 1); in fsl_sai_set_bclk()
420 } else if (!sai->synchronous[dir]) { in fsl_sai_set_bclk()
421 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs), in fsl_sai_set_bclk()
423 FSL_SAI_CR2_MSEL(sai->mclk_id[tx])); in fsl_sai_set_bclk()
424 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs), in fsl_sai_set_bclk()
425 FSL_SAI_CR2_DIV_MASK, savediv - 1); in fsl_sai_set_bclk()
428 dev_dbg(dai->dev, "best fit: clock id=%d, div=%d, deviation =%d\n", in fsl_sai_set_bclk()
429 sai->mclk_id[tx], savediv, savesub); in fsl_sai_set_bclk()
439 unsigned int ofs = sai->soc_data->reg_offset; in fsl_sai_hw_params()
440 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; in fsl_sai_hw_params()
450 if (sai->slots) in fsl_sai_hw_params()
451 slots = sai->slots; in fsl_sai_hw_params()
453 if (sai->slot_width) in fsl_sai_hw_params()
454 slot_width = sai->slot_width; in fsl_sai_hw_params()
458 if (!sai->is_slave_mode) { in fsl_sai_hw_params()
459 if (sai->bclk_ratio) in fsl_sai_hw_params()
461 sai->bclk_ratio * in fsl_sai_hw_params()
471 if (!(sai->mclk_streams & BIT(substream->stream))) { in fsl_sai_hw_params()
472 ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[tx]]); in fsl_sai_hw_params()
476 sai->mclk_streams |= BIT(substream->stream); in fsl_sai_hw_params()
480 if (!sai->is_dsp_mode) in fsl_sai_hw_params()
486 if (sai->is_lsb_first) in fsl_sai_hw_params()
489 val_cr5 |= FSL_SAI_CR5_FBT(word_width - 1); in fsl_sai_hw_params()
493 /* Set to output mode to avoid tri-stated data pins */ in fsl_sai_hw_params()
503 if (!sai->is_slave_mode && fsl_sai_dir_is_synced(sai, adir)) { in fsl_sai_hw_params()
504 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(!tx, ofs), in fsl_sai_hw_params()
508 regmap_update_bits(sai->regmap, FSL_SAI_xCR5(!tx, ofs), in fsl_sai_hw_params()
513 regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx, ofs), in fsl_sai_hw_params()
515 FSL_SAI_CR3_TRCE((1 << pins) - 1)); in fsl_sai_hw_params()
516 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs), in fsl_sai_hw_params()
520 regmap_update_bits(sai->regmap, FSL_SAI_xCR5(tx, ofs), in fsl_sai_hw_params()
523 regmap_write(sai->regmap, FSL_SAI_xMR(tx), in fsl_sai_hw_params()
524 ~0UL - ((1 << min(channels, slots)) - 1)); in fsl_sai_hw_params()
533 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; in fsl_sai_hw_free()
534 unsigned int ofs = sai->soc_data->reg_offset; in fsl_sai_hw_free()
536 regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx, ofs), in fsl_sai_hw_free()
539 if (!sai->is_slave_mode && in fsl_sai_hw_free()
540 sai->mclk_streams & BIT(substream->stream)) { in fsl_sai_hw_free()
541 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[tx]]); in fsl_sai_hw_free()
542 sai->mclk_streams &= ~BIT(substream->stream); in fsl_sai_hw_free()
550 unsigned int ofs = sai->soc_data->reg_offset; in fsl_sai_config_disable()
554 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), in fsl_sai_config_disable()
560 regmap_read(sai->regmap, FSL_SAI_xCSR(tx, ofs), &xcsr); in fsl_sai_config_disable()
561 } while (--count && xcsr & FSL_SAI_CSR_TERE); in fsl_sai_config_disable()
563 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), in fsl_sai_config_disable()
573 if (!sai->is_slave_mode) { in fsl_sai_config_disable()
575 regmap_write(sai->regmap, FSL_SAI_xCSR(tx, ofs), FSL_SAI_CSR_SR); in fsl_sai_config_disable()
577 regmap_write(sai->regmap, FSL_SAI_xCSR(tx, ofs), 0); in fsl_sai_config_disable()
585 unsigned int ofs = sai->soc_data->reg_offset; in fsl_sai_trigger()
587 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; in fsl_sai_trigger()
597 regmap_update_bits(sai->regmap, FSL_SAI_TCR2(ofs), FSL_SAI_CR2_SYNC, in fsl_sai_trigger()
598 sai->synchronous[TX] ? FSL_SAI_CR2_SYNC : 0); in fsl_sai_trigger()
599 regmap_update_bits(sai->regmap, FSL_SAI_RCR2(ofs), FSL_SAI_CR2_SYNC, in fsl_sai_trigger()
600 sai->synchronous[RX] ? FSL_SAI_CR2_SYNC : 0); in fsl_sai_trigger()
610 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), in fsl_sai_trigger()
613 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), in fsl_sai_trigger()
627 regmap_update_bits(sai->regmap, FSL_SAI_xCSR((!tx), ofs), in fsl_sai_trigger()
630 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), in fsl_sai_trigger()
636 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), in fsl_sai_trigger()
638 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), in fsl_sai_trigger()
642 regmap_read(sai->regmap, FSL_SAI_xCSR(!tx, ofs), &xcsr); in fsl_sai_trigger()
662 return -EINVAL; in fsl_sai_trigger()
672 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; in fsl_sai_startup()
676 * EDMA controller needs period size to be a multiple of in fsl_sai_startup()
679 if (sai->soc_data->use_edma) in fsl_sai_startup()
680 snd_pcm_hw_constraint_step(substream->runtime, 0, in fsl_sai_startup()
682 tx ? sai->dma_params_tx.maxburst : in fsl_sai_startup()
683 sai->dma_params_rx.maxburst); in fsl_sai_startup()
685 ret = snd_pcm_hw_constraint_list(substream->runtime, 0, in fsl_sai_startup()
704 struct fsl_sai *sai = dev_get_drvdata(cpu_dai->dev); in fsl_sai_dai_probe()
705 unsigned int ofs = sai->soc_data->reg_offset; in fsl_sai_dai_probe()
708 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), FSL_SAI_CSR_SR); in fsl_sai_dai_probe()
709 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), FSL_SAI_CSR_SR); in fsl_sai_dai_probe()
711 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), 0); in fsl_sai_dai_probe()
712 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), 0); in fsl_sai_dai_probe()
714 regmap_update_bits(sai->regmap, FSL_SAI_TCR1(ofs), in fsl_sai_dai_probe()
715 FSL_SAI_CR1_RFW_MASK(sai->soc_data->fifo_depth), in fsl_sai_dai_probe()
716 sai->soc_data->fifo_depth - FSL_SAI_MAXBURST_TX); in fsl_sai_dai_probe()
717 regmap_update_bits(sai->regmap, FSL_SAI_RCR1(ofs), in fsl_sai_dai_probe()
718 FSL_SAI_CR1_RFW_MASK(sai->soc_data->fifo_depth), in fsl_sai_dai_probe()
719 FSL_SAI_MAXBURST_RX - 1); in fsl_sai_dai_probe()
721 snd_soc_dai_init_dma_data(cpu_dai, &sai->dma_params_tx, in fsl_sai_dai_probe()
722 &sai->dma_params_rx); in fsl_sai_dai_probe()
732 .stream_name = "CPU-Playback",
741 .stream_name = "CPU-Capture",
753 .name = "fsl-sai",
807 unsigned int ofs = sai->soc_data->reg_offset; in fsl_sai_readable_reg()
863 unsigned int ofs = sai->soc_data->reg_offset; in fsl_sai_volatile_reg()
906 unsigned int ofs = sai->soc_data->reg_offset; in fsl_sai_writeable_reg()
953 unsigned char ofs = sai->soc_data->reg_offset; in fsl_sai_check_version()
960 ret = regmap_read(sai->regmap, FSL_SAI_VERID, &val); in fsl_sai_check_version()
966 sai->verid.major = (val & FSL_SAI_VERID_MAJOR_MASK) >> in fsl_sai_check_version()
968 sai->verid.minor = (val & FSL_SAI_VERID_MINOR_MASK) >> in fsl_sai_check_version()
970 sai->verid.feature = val & FSL_SAI_VERID_FEATURE_MASK; in fsl_sai_check_version()
972 ret = regmap_read(sai->regmap, FSL_SAI_PARAM, &val); in fsl_sai_check_version()
979 sai->param.slot_num = 1 << in fsl_sai_check_version()
983 sai->param.fifo_depth = 1 << in fsl_sai_check_version()
987 sai->param.dataline = val & FSL_SAI_PARAM_DLN_MASK; in fsl_sai_check_version()
994 struct device_node *np = pdev->dev.of_node; in fsl_sai_probe()
1003 sai = devm_kzalloc(&pdev->dev, sizeof(*sai), GFP_KERNEL); in fsl_sai_probe()
1005 return -ENOMEM; in fsl_sai_probe()
1007 sai->pdev = pdev; in fsl_sai_probe()
1008 sai->soc_data = of_device_get_match_data(&pdev->dev); in fsl_sai_probe()
1010 sai->is_lsb_first = of_property_read_bool(np, "lsb-first"); in fsl_sai_probe()
1013 base = devm_ioremap_resource(&pdev->dev, res); in fsl_sai_probe()
1017 if (sai->soc_data->reg_offset == 8) { in fsl_sai_probe()
1024 sai->regmap = devm_regmap_init_mmio_clk(&pdev->dev, in fsl_sai_probe()
1028 if (IS_ERR(sai->regmap) && PTR_ERR(sai->regmap) != -EPROBE_DEFER) in fsl_sai_probe()
1029 sai->regmap = devm_regmap_init_mmio_clk(&pdev->dev, in fsl_sai_probe()
1031 if (IS_ERR(sai->regmap)) { in fsl_sai_probe()
1032 dev_err(&pdev->dev, "regmap init failed\n"); in fsl_sai_probe()
1033 return PTR_ERR(sai->regmap); in fsl_sai_probe()
1037 sai->bus_clk = devm_clk_get(&pdev->dev, "bus"); in fsl_sai_probe()
1038 if (IS_ERR(sai->bus_clk)) { in fsl_sai_probe()
1039 dev_err(&pdev->dev, "failed to get bus clock: %ld\n", in fsl_sai_probe()
1040 PTR_ERR(sai->bus_clk)); in fsl_sai_probe()
1041 sai->bus_clk = NULL; in fsl_sai_probe()
1044 sai->mclk_clk[0] = sai->bus_clk; in fsl_sai_probe()
1047 sai->mclk_clk[i] = devm_clk_get(&pdev->dev, tmp); in fsl_sai_probe()
1048 if (IS_ERR(sai->mclk_clk[i])) { in fsl_sai_probe()
1049 dev_err(&pdev->dev, "failed to get mclk%d clock: %ld\n", in fsl_sai_probe()
1050 i + 1, PTR_ERR(sai->mclk_clk[i])); in fsl_sai_probe()
1051 sai->mclk_clk[i] = NULL; in fsl_sai_probe()
1059 ret = devm_request_irq(&pdev->dev, irq, fsl_sai_isr, IRQF_SHARED, in fsl_sai_probe()
1060 np->name, sai); in fsl_sai_probe()
1062 dev_err(&pdev->dev, "failed to claim irq %u\n", irq); in fsl_sai_probe()
1066 memcpy(&sai->cpu_dai_drv, &fsl_sai_dai_template, in fsl_sai_probe()
1070 sai->synchronous[RX] = true; in fsl_sai_probe()
1071 sai->synchronous[TX] = false; in fsl_sai_probe()
1072 sai->cpu_dai_drv.symmetric_rates = 1; in fsl_sai_probe()
1073 sai->cpu_dai_drv.symmetric_channels = 1; in fsl_sai_probe()
1074 sai->cpu_dai_drv.symmetric_samplebits = 1; in fsl_sai_probe()
1076 if (of_find_property(np, "fsl,sai-synchronous-rx", NULL) && in fsl_sai_probe()
1077 of_find_property(np, "fsl,sai-asynchronous", NULL)) { in fsl_sai_probe()
1079 dev_err(&pdev->dev, "invalid binding for synchronous mode\n"); in fsl_sai_probe()
1080 return -EINVAL; in fsl_sai_probe()
1083 if (of_find_property(np, "fsl,sai-synchronous-rx", NULL)) { in fsl_sai_probe()
1085 sai->synchronous[RX] = false; in fsl_sai_probe()
1086 sai->synchronous[TX] = true; in fsl_sai_probe()
1087 } else if (of_find_property(np, "fsl,sai-asynchronous", NULL)) { in fsl_sai_probe()
1089 sai->synchronous[RX] = false; in fsl_sai_probe()
1090 sai->synchronous[TX] = false; in fsl_sai_probe()
1091 sai->cpu_dai_drv.symmetric_rates = 0; in fsl_sai_probe()
1092 sai->cpu_dai_drv.symmetric_channels = 0; in fsl_sai_probe()
1093 sai->cpu_dai_drv.symmetric_samplebits = 0; in fsl_sai_probe()
1096 if (of_find_property(np, "fsl,sai-mclk-direction-output", NULL) && in fsl_sai_probe()
1097 of_device_is_compatible(np, "fsl,imx6ul-sai")) { in fsl_sai_probe()
1098 gpr = syscon_regmap_lookup_by_compatible("fsl,imx6ul-iomuxc-gpr"); in fsl_sai_probe()
1100 dev_err(&pdev->dev, "cannot find iomuxc registers\n"); in fsl_sai_probe()
1112 sai->dma_params_rx.addr = res->start + FSL_SAI_RDR0; in fsl_sai_probe()
1113 sai->dma_params_tx.addr = res->start + FSL_SAI_TDR0; in fsl_sai_probe()
1114 sai->dma_params_rx.maxburst = FSL_SAI_MAXBURST_RX; in fsl_sai_probe()
1115 sai->dma_params_tx.maxburst = FSL_SAI_MAXBURST_TX; in fsl_sai_probe()
1120 ret = fsl_sai_check_version(&pdev->dev); in fsl_sai_probe()
1122 dev_warn(&pdev->dev, "Error reading SAI version: %d\n", ret); in fsl_sai_probe()
1125 if (of_find_property(np, "fsl,sai-mclk-direction-output", NULL) && in fsl_sai_probe()
1126 sai->verid.major >= 3 && sai->verid.minor >= 1) { in fsl_sai_probe()
1127 regmap_update_bits(sai->regmap, FSL_SAI_MCTL, in fsl_sai_probe()
1131 pm_runtime_enable(&pdev->dev); in fsl_sai_probe()
1132 regcache_cache_only(sai->regmap, true); in fsl_sai_probe()
1134 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_component, in fsl_sai_probe()
1135 &sai->cpu_dai_drv, 1); in fsl_sai_probe()
1139 if (sai->soc_data->use_imx_pcm) { in fsl_sai_probe()
1144 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0); in fsl_sai_probe()
1152 pm_runtime_disable(&pdev->dev); in fsl_sai_probe()
1159 pm_runtime_disable(&pdev->dev); in fsl_sai_remove()
1200 { .compatible = "fsl,vf610-sai", .data = &fsl_sai_vf610_data },
1201 { .compatible = "fsl,imx6sx-sai", .data = &fsl_sai_imx6sx_data },
1202 { .compatible = "fsl,imx6ul-sai", .data = &fsl_sai_imx6sx_data },
1203 { .compatible = "fsl,imx7ulp-sai", .data = &fsl_sai_imx7ulp_data },
1204 { .compatible = "fsl,imx8mq-sai", .data = &fsl_sai_imx8mq_data },
1205 { .compatible = "fsl,imx8qm-sai", .data = &fsl_sai_imx8qm_data },
1215 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE)) in fsl_sai_runtime_suspend()
1216 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[0]]); in fsl_sai_runtime_suspend()
1218 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK)) in fsl_sai_runtime_suspend()
1219 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[1]]); in fsl_sai_runtime_suspend()
1221 clk_disable_unprepare(sai->bus_clk); in fsl_sai_runtime_suspend()
1223 regcache_cache_only(sai->regmap, true); in fsl_sai_runtime_suspend()
1231 unsigned int ofs = sai->soc_data->reg_offset; in fsl_sai_runtime_resume()
1234 ret = clk_prepare_enable(sai->bus_clk); in fsl_sai_runtime_resume()
1240 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK)) { in fsl_sai_runtime_resume()
1241 ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[1]]); in fsl_sai_runtime_resume()
1246 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE)) { in fsl_sai_runtime_resume()
1247 ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[0]]); in fsl_sai_runtime_resume()
1252 regcache_cache_only(sai->regmap, false); in fsl_sai_runtime_resume()
1253 regcache_mark_dirty(sai->regmap); in fsl_sai_runtime_resume()
1254 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), FSL_SAI_CSR_SR); in fsl_sai_runtime_resume()
1255 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), FSL_SAI_CSR_SR); in fsl_sai_runtime_resume()
1257 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), 0); in fsl_sai_runtime_resume()
1258 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), 0); in fsl_sai_runtime_resume()
1260 ret = regcache_sync(sai->regmap); in fsl_sai_runtime_resume()
1267 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE)) in fsl_sai_runtime_resume()
1268 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[0]]); in fsl_sai_runtime_resume()
1270 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK)) in fsl_sai_runtime_resume()
1271 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[1]]); in fsl_sai_runtime_resume()
1273 clk_disable_unprepare(sai->bus_clk); in fsl_sai_runtime_resume()
1290 .name = "fsl-sai",
1299 MODULE_ALIAS("platform:fsl-sai");