1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
15  * Hardware interface for generic Intel audio DSP HDA IP
26 static int hda_codec_mask = -1;
35 int hda_dsp_ctrl_link_reset(struct snd_sof_dev *sdev, bool reset)  in hda_dsp_ctrl_link_reset()  argument
41 	/* 0 to enter reset and 1 to exit reset */  in hda_dsp_ctrl_link_reset()
42 	val = reset ? 0 : SOF_HDA_GCTL_RESET;  in hda_dsp_ctrl_link_reset()
44 	/* enter/exit HDA controller reset */  in hda_dsp_ctrl_link_reset()
48 	/* wait to enter/exit reset */  in hda_dsp_ctrl_link_reset()
57 	/* enter/exit reset failed */  in hda_dsp_ctrl_link_reset()
58 	dev_err(sdev->dev, "error: failed to %s HDA controller gctl 0x%x\n",  in hda_dsp_ctrl_link_reset()
59 		reset ? "reset" : "ready", gctl);  in hda_dsp_ctrl_link_reset()
60 	return -EIO;  in hda_dsp_ctrl_link_reset()
71 	 * On some devices, one reset cycle is necessary before reading  in hda_dsp_ctrl_get_caps()
84 		dev_dbg(sdev->dev, "checking for capabilities at offset 0x%x\n",  in hda_dsp_ctrl_get_caps()
89 		if (cap == -1) {  in hda_dsp_ctrl_get_caps()
90 			dev_dbg(bus->dev, "Invalid capability reg read\n");  in hda_dsp_ctrl_get_caps()
98 			dev_dbg(sdev->dev, "found DSP capability at 0x%x\n",  in hda_dsp_ctrl_get_caps()
100 			bus->ppcap = bus->remap_addr + offset;  in hda_dsp_ctrl_get_caps()
101 			sdev->bar[HDA_DSP_PP_BAR] = bus->ppcap;  in hda_dsp_ctrl_get_caps()
104 			dev_dbg(sdev->dev, "found SPIB capability at 0x%x\n",  in hda_dsp_ctrl_get_caps()
106 			bus->spbcap = bus->remap_addr + offset;  in hda_dsp_ctrl_get_caps()
107 			sdev->bar[HDA_DSP_SPIB_BAR] = bus->spbcap;  in hda_dsp_ctrl_get_caps()
110 			dev_dbg(sdev->dev, "found DRSM capability at 0x%x\n",  in hda_dsp_ctrl_get_caps()
112 			bus->drsmcap = bus->remap_addr + offset;  in hda_dsp_ctrl_get_caps()
113 			sdev->bar[HDA_DSP_DRSM_BAR] = bus->drsmcap;  in hda_dsp_ctrl_get_caps()
116 			dev_dbg(sdev->dev, "found GTS capability at 0x%x\n",  in hda_dsp_ctrl_get_caps()
118 			bus->gtscap = bus->remap_addr + offset;  in hda_dsp_ctrl_get_caps()
121 			dev_dbg(sdev->dev, "found ML capability at 0x%x\n",  in hda_dsp_ctrl_get_caps()
123 			bus->mlcap = bus->remap_addr + offset;  in hda_dsp_ctrl_get_caps()
126 			dev_dbg(sdev->dev, "found capability %d at 0x%x\n",  in hda_dsp_ctrl_get_caps()
161  * enable/disable audio dsp clock gating and power gating bits.
163  * the audio dsp when it is idle
169 	/* enable/disable audio dsp clock gating */  in hda_dsp_ctrl_clock_power_gating()
178 	/* enable/disable audio dsp power gating */  in hda_dsp_ctrl_clock_power_gating()
194 	if (bus->chip_init)  in hda_dsp_ctrl_init_chip()
203 		/* reset HDA controller */  in hda_dsp_ctrl_init_chip()
206 			dev_err(sdev->dev, "error: failed to reset HDA controller\n");  in hda_dsp_ctrl_init_chip()
212 		/* exit HDA controller reset */  in hda_dsp_ctrl_init_chip()
215 			dev_err(sdev->dev, "error: failed to exit HDA controller reset\n");  in hda_dsp_ctrl_init_chip()
225 		dev_dbg(bus->dev, "controller not ready!\n");  in hda_dsp_ctrl_init_chip()
226 		ret = -EBUSY;  in hda_dsp_ctrl_init_chip()
234 	if (!bus->codec_mask) {  in hda_dsp_ctrl_init_chip()
235 		bus->codec_mask = snd_hdac_chip_readw(bus, STATESTS);  in hda_dsp_ctrl_init_chip()
236 		dev_dbg(bus->dev, "codec_mask = 0x%lx\n", bus->codec_mask);  in hda_dsp_ctrl_init_chip()
239 	if (hda_codec_mask != -1) {  in hda_dsp_ctrl_init_chip()
240 		bus->codec_mask &= hda_codec_mask;  in hda_dsp_ctrl_init_chip()
241 		dev_dbg(bus->dev, "filtered codec_mask = 0x%lx\n",  in hda_dsp_ctrl_init_chip()
242 			bus->codec_mask);  in hda_dsp_ctrl_init_chip()
247 	list_for_each_entry(stream, &bus->stream_list, list) {  in hda_dsp_ctrl_init_chip()
278 	if (bus->use_posbuf && bus->posbuf.addr) {  in hda_dsp_ctrl_init_chip()
280 				  (u32)bus->posbuf.addr);  in hda_dsp_ctrl_init_chip()
282 				  upper_32_bits(bus->posbuf.addr));  in hda_dsp_ctrl_init_chip()
286 	/* Reset stream-to-link mapping */  in hda_dsp_ctrl_init_chip()
287 	list_for_each_entry(hlink, &bus->hlink_list, list)  in hda_dsp_ctrl_init_chip()
288 		writel(0, hlink->ml_addr + AZX_REG_ML_LOSIDV);  in hda_dsp_ctrl_init_chip()
291 	bus->chip_init = true;  in hda_dsp_ctrl_init_chip()
308 	if (!bus->chip_init)  in hda_dsp_ctrl_stop_chip()
312 	list_for_each_entry(stream, &bus->stream_list, list) {  in hda_dsp_ctrl_stop_chip()
331 	list_for_each_entry(stream, &bus->stream_list, list) {  in hda_dsp_ctrl_stop_chip()
356 	if (bus->posbuf.addr) {  in hda_dsp_ctrl_stop_chip()
363 	bus->chip_init = false;  in hda_dsp_ctrl_stop_chip()