Lines Matching +full:da830 +full:- +full:mcasp +full:- +full:audio
1 // SPDX-License-Identifier: GPL-2.0-only
3 * ALSA SoC McASP Audio Layer for TI DAVINCI processor
5 * Multi-channel Audio Serial Port Driver
7 * Author: Nirmal Pandey <n-pandey@ti.com>,
39 #include "edma-pcm.h"
40 #include "sdma-pcm.h"
41 #include "udma-pcm.h"
42 #include "davinci-mcasp.h"
73 struct davinci_mcasp *mcasp; member
85 /* McASP specific data */
105 /* McASP FIFO related */
128 static inline void mcasp_set_bits(struct davinci_mcasp *mcasp, u32 offset, in mcasp_set_bits() argument
131 void __iomem *reg = mcasp->base + offset; in mcasp_set_bits()
135 static inline void mcasp_clr_bits(struct davinci_mcasp *mcasp, u32 offset, in mcasp_clr_bits() argument
138 void __iomem *reg = mcasp->base + offset; in mcasp_clr_bits()
142 static inline void mcasp_mod_bits(struct davinci_mcasp *mcasp, u32 offset, in mcasp_mod_bits() argument
145 void __iomem *reg = mcasp->base + offset; in mcasp_mod_bits()
149 static inline void mcasp_set_reg(struct davinci_mcasp *mcasp, u32 offset, in mcasp_set_reg() argument
152 __raw_writel(val, mcasp->base + offset); in mcasp_set_reg()
155 static inline u32 mcasp_get_reg(struct davinci_mcasp *mcasp, u32 offset) in mcasp_get_reg() argument
157 return (u32)__raw_readl(mcasp->base + offset); in mcasp_get_reg()
160 static void mcasp_set_ctl_reg(struct davinci_mcasp *mcasp, u32 ctl_reg, u32 val) in mcasp_set_ctl_reg() argument
164 mcasp_set_bits(mcasp, ctl_reg, val); in mcasp_set_ctl_reg()
167 /* loop count is to avoid the lock-up */ in mcasp_set_ctl_reg()
169 if ((mcasp_get_reg(mcasp, ctl_reg) & val) == val) in mcasp_set_ctl_reg()
173 if (i == 1000 && ((mcasp_get_reg(mcasp, ctl_reg) & val) != val)) in mcasp_set_ctl_reg()
177 static bool mcasp_is_synchronous(struct davinci_mcasp *mcasp) in mcasp_is_synchronous() argument
179 u32 rxfmctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG); in mcasp_is_synchronous()
180 u32 aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG); in mcasp_is_synchronous()
185 static inline void mcasp_set_clk_pdir(struct davinci_mcasp *mcasp, bool enable) in mcasp_set_clk_pdir() argument
189 for_each_set_bit_from(bit, &mcasp->pdir, PIN_BIT_AFSR + 1) { in mcasp_set_clk_pdir()
191 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit)); in mcasp_set_clk_pdir()
193 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit)); in mcasp_set_clk_pdir()
197 static inline void mcasp_set_axr_pdir(struct davinci_mcasp *mcasp, bool enable) in mcasp_set_axr_pdir() argument
201 for_each_set_bit(bit, &mcasp->pdir, PIN_BIT_AMUTE) { in mcasp_set_axr_pdir()
203 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit)); in mcasp_set_axr_pdir()
205 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit)); in mcasp_set_axr_pdir()
209 static void mcasp_start_rx(struct davinci_mcasp *mcasp) in mcasp_start_rx() argument
211 if (mcasp->rxnumevt) { /* enable FIFO */ in mcasp_start_rx()
212 u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; in mcasp_start_rx()
214 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); in mcasp_start_rx()
215 mcasp_set_bits(mcasp, reg, FIFO_ENABLE); in mcasp_start_rx()
219 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST); in mcasp_start_rx()
220 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST); in mcasp_start_rx()
226 if (mcasp_is_synchronous(mcasp)) { in mcasp_start_rx()
227 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST); in mcasp_start_rx()
228 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST); in mcasp_start_rx()
229 mcasp_set_clk_pdir(mcasp, true); in mcasp_start_rx()
233 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF); in mcasp_start_rx()
234 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR); in mcasp_start_rx()
236 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST); in mcasp_start_rx()
238 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST); in mcasp_start_rx()
239 if (mcasp_is_synchronous(mcasp)) in mcasp_start_rx()
240 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST); in mcasp_start_rx()
243 mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG, in mcasp_start_rx()
244 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]); in mcasp_start_rx()
247 static void mcasp_start_tx(struct davinci_mcasp *mcasp) in mcasp_start_tx() argument
251 if (mcasp->txnumevt) { /* enable FIFO */ in mcasp_start_tx()
252 u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; in mcasp_start_tx()
254 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); in mcasp_start_tx()
255 mcasp_set_bits(mcasp, reg, FIFO_ENABLE); in mcasp_start_tx()
259 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST); in mcasp_start_tx()
260 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST); in mcasp_start_tx()
261 mcasp_set_clk_pdir(mcasp, true); in mcasp_start_tx()
264 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF); in mcasp_start_tx()
265 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR); in mcasp_start_tx()
269 while ((mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG) & XRDATA) && in mcasp_start_tx()
273 mcasp_set_axr_pdir(mcasp, true); in mcasp_start_tx()
276 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSMRST); in mcasp_start_tx()
278 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST); in mcasp_start_tx()
281 mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG, in mcasp_start_tx()
282 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]); in mcasp_start_tx()
285 static void davinci_mcasp_start(struct davinci_mcasp *mcasp, int stream) in davinci_mcasp_start() argument
287 mcasp->streams++; in davinci_mcasp_start()
290 mcasp_start_tx(mcasp); in davinci_mcasp_start()
292 mcasp_start_rx(mcasp); in davinci_mcasp_start()
295 static void mcasp_stop_rx(struct davinci_mcasp *mcasp) in mcasp_stop_rx() argument
298 mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG, in mcasp_stop_rx()
299 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]); in mcasp_stop_rx()
305 if (mcasp_is_synchronous(mcasp) && !mcasp->streams) { in mcasp_stop_rx()
306 mcasp_set_clk_pdir(mcasp, false); in mcasp_stop_rx()
307 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, 0); in mcasp_stop_rx()
310 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, 0); in mcasp_stop_rx()
311 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF); in mcasp_stop_rx()
313 if (mcasp->rxnumevt) { /* disable FIFO */ in mcasp_stop_rx()
314 u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; in mcasp_stop_rx()
316 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); in mcasp_stop_rx()
320 static void mcasp_stop_tx(struct davinci_mcasp *mcasp) in mcasp_stop_tx() argument
325 mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG, in mcasp_stop_tx()
326 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]); in mcasp_stop_tx()
332 if (mcasp_is_synchronous(mcasp) && mcasp->streams) in mcasp_stop_tx()
335 mcasp_set_clk_pdir(mcasp, false); in mcasp_stop_tx()
338 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, val); in mcasp_stop_tx()
339 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF); in mcasp_stop_tx()
341 if (mcasp->txnumevt) { /* disable FIFO */ in mcasp_stop_tx()
342 u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; in mcasp_stop_tx()
344 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); in mcasp_stop_tx()
347 mcasp_set_axr_pdir(mcasp, false); in mcasp_stop_tx()
350 static void davinci_mcasp_stop(struct davinci_mcasp *mcasp, int stream) in davinci_mcasp_stop() argument
352 mcasp->streams--; in davinci_mcasp_stop()
355 mcasp_stop_tx(mcasp); in davinci_mcasp_stop()
357 mcasp_stop_rx(mcasp); in davinci_mcasp_stop()
362 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data; in davinci_mcasp_tx_irq_handler() local
364 u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]; in davinci_mcasp_tx_irq_handler()
368 stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG); in davinci_mcasp_tx_irq_handler()
370 dev_warn(mcasp->dev, "Transmit buffer underflow\n"); in davinci_mcasp_tx_irq_handler()
373 substream = mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK]; in davinci_mcasp_tx_irq_handler()
379 dev_warn(mcasp->dev, "unhandled tx event. txstat: 0x%08x\n", in davinci_mcasp_tx_irq_handler()
386 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, handled_mask); in davinci_mcasp_tx_irq_handler()
393 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data; in davinci_mcasp_rx_irq_handler() local
395 u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]; in davinci_mcasp_rx_irq_handler()
399 stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG); in davinci_mcasp_rx_irq_handler()
401 dev_warn(mcasp->dev, "Receive buffer overflow\n"); in davinci_mcasp_rx_irq_handler()
404 substream = mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE]; in davinci_mcasp_rx_irq_handler()
410 dev_warn(mcasp->dev, "unhandled rx event. rxstat: 0x%08x\n", in davinci_mcasp_rx_irq_handler()
417 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, handled_mask); in davinci_mcasp_rx_irq_handler()
424 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data; in davinci_mcasp_common_irq_handler() local
427 if (mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK]) in davinci_mcasp_common_irq_handler()
430 if (mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE]) in davinci_mcasp_common_irq_handler()
439 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); in davinci_mcasp_set_dai_fmt() local
448 pm_runtime_get_sync(mcasp->dev); in davinci_mcasp_set_dai_fmt()
451 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); in davinci_mcasp_set_dai_fmt()
452 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); in davinci_mcasp_set_dai_fmt()
458 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); in davinci_mcasp_set_dai_fmt()
459 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); in davinci_mcasp_set_dai_fmt()
464 /* configure a full-word SYNC pulse (LRCLK) */ in davinci_mcasp_set_dai_fmt()
465 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); in davinci_mcasp_set_dai_fmt()
466 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); in davinci_mcasp_set_dai_fmt()
474 /* configure a full-word SYNC pulse (LRCLK) */ in davinci_mcasp_set_dai_fmt()
475 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); in davinci_mcasp_set_dai_fmt()
476 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); in davinci_mcasp_set_dai_fmt()
481 ret = -EINVAL; in davinci_mcasp_set_dai_fmt()
485 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, FSXDLY(data_delay), in davinci_mcasp_set_dai_fmt()
487 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, FSRDLY(data_delay), in davinci_mcasp_set_dai_fmt()
493 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); in davinci_mcasp_set_dai_fmt()
494 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE); in davinci_mcasp_set_dai_fmt()
496 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); in davinci_mcasp_set_dai_fmt()
497 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE); in davinci_mcasp_set_dai_fmt()
500 set_bit(PIN_BIT_ACLKX, &mcasp->pdir); in davinci_mcasp_set_dai_fmt()
501 set_bit(PIN_BIT_ACLKR, &mcasp->pdir); in davinci_mcasp_set_dai_fmt()
503 set_bit(PIN_BIT_AFSX, &mcasp->pdir); in davinci_mcasp_set_dai_fmt()
504 set_bit(PIN_BIT_AFSR, &mcasp->pdir); in davinci_mcasp_set_dai_fmt()
506 mcasp->bclk_master = 1; in davinci_mcasp_set_dai_fmt()
510 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); in davinci_mcasp_set_dai_fmt()
511 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE); in davinci_mcasp_set_dai_fmt()
513 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); in davinci_mcasp_set_dai_fmt()
514 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE); in davinci_mcasp_set_dai_fmt()
517 set_bit(PIN_BIT_ACLKX, &mcasp->pdir); in davinci_mcasp_set_dai_fmt()
518 set_bit(PIN_BIT_ACLKR, &mcasp->pdir); in davinci_mcasp_set_dai_fmt()
520 clear_bit(PIN_BIT_AFSX, &mcasp->pdir); in davinci_mcasp_set_dai_fmt()
521 clear_bit(PIN_BIT_AFSR, &mcasp->pdir); in davinci_mcasp_set_dai_fmt()
523 mcasp->bclk_master = 1; in davinci_mcasp_set_dai_fmt()
527 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); in davinci_mcasp_set_dai_fmt()
528 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE); in davinci_mcasp_set_dai_fmt()
530 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); in davinci_mcasp_set_dai_fmt()
531 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE); in davinci_mcasp_set_dai_fmt()
534 clear_bit(PIN_BIT_ACLKX, &mcasp->pdir); in davinci_mcasp_set_dai_fmt()
535 clear_bit(PIN_BIT_ACLKR, &mcasp->pdir); in davinci_mcasp_set_dai_fmt()
537 set_bit(PIN_BIT_AFSX, &mcasp->pdir); in davinci_mcasp_set_dai_fmt()
538 set_bit(PIN_BIT_AFSR, &mcasp->pdir); in davinci_mcasp_set_dai_fmt()
540 mcasp->bclk_master = 0; in davinci_mcasp_set_dai_fmt()
544 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); in davinci_mcasp_set_dai_fmt()
545 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE); in davinci_mcasp_set_dai_fmt()
547 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); in davinci_mcasp_set_dai_fmt()
548 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE); in davinci_mcasp_set_dai_fmt()
551 clear_bit(PIN_BIT_ACLKX, &mcasp->pdir); in davinci_mcasp_set_dai_fmt()
552 clear_bit(PIN_BIT_ACLKR, &mcasp->pdir); in davinci_mcasp_set_dai_fmt()
554 clear_bit(PIN_BIT_AFSX, &mcasp->pdir); in davinci_mcasp_set_dai_fmt()
555 clear_bit(PIN_BIT_AFSR, &mcasp->pdir); in davinci_mcasp_set_dai_fmt()
557 mcasp->bclk_master = 0; in davinci_mcasp_set_dai_fmt()
560 ret = -EINVAL; in davinci_mcasp_set_dai_fmt()
566 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); in davinci_mcasp_set_dai_fmt()
567 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); in davinci_mcasp_set_dai_fmt()
571 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); in davinci_mcasp_set_dai_fmt()
572 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); in davinci_mcasp_set_dai_fmt()
576 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); in davinci_mcasp_set_dai_fmt()
577 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); in davinci_mcasp_set_dai_fmt()
581 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); in davinci_mcasp_set_dai_fmt()
582 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); in davinci_mcasp_set_dai_fmt()
586 ret = -EINVAL; in davinci_mcasp_set_dai_fmt()
594 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL); in davinci_mcasp_set_dai_fmt()
595 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL); in davinci_mcasp_set_dai_fmt()
597 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL); in davinci_mcasp_set_dai_fmt()
598 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL); in davinci_mcasp_set_dai_fmt()
601 mcasp->dai_fmt = fmt; in davinci_mcasp_set_dai_fmt()
603 pm_runtime_put(mcasp->dev); in davinci_mcasp_set_dai_fmt()
607 static int __davinci_mcasp_set_clkdiv(struct davinci_mcasp *mcasp, int div_id, in __davinci_mcasp_set_clkdiv() argument
610 pm_runtime_get_sync(mcasp->dev); in __davinci_mcasp_set_clkdiv()
613 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, in __davinci_mcasp_set_clkdiv()
614 AHCLKXDIV(div - 1), AHCLKXDIV_MASK); in __davinci_mcasp_set_clkdiv()
615 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, in __davinci_mcasp_set_clkdiv()
616 AHCLKRDIV(div - 1), AHCLKRDIV_MASK); in __davinci_mcasp_set_clkdiv()
620 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, in __davinci_mcasp_set_clkdiv()
621 ACLKXDIV(div - 1), ACLKXDIV_MASK); in __davinci_mcasp_set_clkdiv()
622 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, in __davinci_mcasp_set_clkdiv()
623 ACLKRDIV(div - 1), ACLKRDIV_MASK); in __davinci_mcasp_set_clkdiv()
625 mcasp->bclk_div = div; in __davinci_mcasp_set_clkdiv()
630 * BCLK/LRCLK ratio descries how many bit-clock cycles in __davinci_mcasp_set_clkdiv()
634 * of tdm-slots (for I2S - divided by 2). in __davinci_mcasp_set_clkdiv()
639 mcasp->slot_width = div / mcasp->tdm_slots; in __davinci_mcasp_set_clkdiv()
640 if (div % mcasp->tdm_slots) in __davinci_mcasp_set_clkdiv()
641 dev_warn(mcasp->dev, in __davinci_mcasp_set_clkdiv()
643 __func__, div, mcasp->tdm_slots); in __davinci_mcasp_set_clkdiv()
647 return -EINVAL; in __davinci_mcasp_set_clkdiv()
650 pm_runtime_put(mcasp->dev); in __davinci_mcasp_set_clkdiv()
657 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); in davinci_mcasp_set_clkdiv() local
659 return __davinci_mcasp_set_clkdiv(mcasp, div_id, div, 1); in davinci_mcasp_set_clkdiv()
665 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); in davinci_mcasp_set_sysclk() local
667 pm_runtime_get_sync(mcasp->dev); in davinci_mcasp_set_sysclk()
672 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, in davinci_mcasp_set_sysclk()
674 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, in davinci_mcasp_set_sysclk()
676 clear_bit(PIN_BIT_AHCLKX, &mcasp->pdir); in davinci_mcasp_set_sysclk()
679 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, in davinci_mcasp_set_sysclk()
681 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, in davinci_mcasp_set_sysclk()
683 set_bit(PIN_BIT_AHCLKX, &mcasp->pdir); in davinci_mcasp_set_sysclk()
686 dev_err(mcasp->dev, "Invalid clk id: %d\n", clk_id); in davinci_mcasp_set_sysclk()
691 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE); in davinci_mcasp_set_sysclk()
692 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE); in davinci_mcasp_set_sysclk()
693 set_bit(PIN_BIT_AHCLKX, &mcasp->pdir); in davinci_mcasp_set_sysclk()
697 * the same clock - coming via AUXCLK. in davinci_mcasp_set_sysclk()
699 mcasp->sysclk_freq = freq; in davinci_mcasp_set_sysclk()
701 pm_runtime_put(mcasp->dev); in davinci_mcasp_set_sysclk()
706 static int davinci_mcasp_ch_constraint(struct davinci_mcasp *mcasp, int stream, in davinci_mcasp_ch_constraint() argument
709 struct snd_pcm_hw_constraint_list *cl = &mcasp->chconstr[stream]; in davinci_mcasp_ch_constraint()
710 unsigned int *list = (unsigned int *) cl->list; in davinci_mcasp_ch_constraint()
711 int slots = mcasp->tdm_slots; in davinci_mcasp_ch_constraint()
714 if (mcasp->tdm_mask[stream]) in davinci_mcasp_ch_constraint()
715 slots = hweight32(mcasp->tdm_mask[stream]); in davinci_mcasp_ch_constraint()
723 cl->count = count; in davinci_mcasp_ch_constraint()
728 static int davinci_mcasp_set_ch_constraints(struct davinci_mcasp *mcasp) in davinci_mcasp_set_ch_constraints() argument
732 for (i = 0; i < mcasp->num_serializer; i++) in davinci_mcasp_set_ch_constraints()
733 if (mcasp->serial_dir[i] == TX_MODE) in davinci_mcasp_set_ch_constraints()
735 else if (mcasp->serial_dir[i] == RX_MODE) in davinci_mcasp_set_ch_constraints()
738 ret = davinci_mcasp_ch_constraint(mcasp, SNDRV_PCM_STREAM_PLAYBACK, in davinci_mcasp_set_ch_constraints()
743 ret = davinci_mcasp_ch_constraint(mcasp, SNDRV_PCM_STREAM_CAPTURE, in davinci_mcasp_set_ch_constraints()
755 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); in davinci_mcasp_set_tdm_slot() local
757 dev_dbg(mcasp->dev, in davinci_mcasp_set_tdm_slot()
762 dev_err(mcasp->dev, in davinci_mcasp_set_tdm_slot()
765 return -EINVAL; in davinci_mcasp_set_tdm_slot()
770 dev_err(mcasp->dev, "%s: Unsupported slot_width %d\n", in davinci_mcasp_set_tdm_slot()
772 return -EINVAL; in davinci_mcasp_set_tdm_slot()
775 mcasp->tdm_slots = slots; in davinci_mcasp_set_tdm_slot()
776 mcasp->tdm_mask[SNDRV_PCM_STREAM_PLAYBACK] = tx_mask; in davinci_mcasp_set_tdm_slot()
777 mcasp->tdm_mask[SNDRV_PCM_STREAM_CAPTURE] = rx_mask; in davinci_mcasp_set_tdm_slot()
778 mcasp->slot_width = slot_width; in davinci_mcasp_set_tdm_slot()
780 return davinci_mcasp_set_ch_constraints(mcasp); in davinci_mcasp_set_tdm_slot()
783 static int davinci_config_channel_size(struct davinci_mcasp *mcasp, in davinci_config_channel_size() argument
788 u32 mask = (1ULL << sample_width) - 1; in davinci_config_channel_size()
790 if (mcasp->slot_width) in davinci_config_channel_size()
791 slot_width = mcasp->slot_width; in davinci_config_channel_size()
792 else if (mcasp->max_format_width) in davinci_config_channel_size()
793 slot_width = mcasp->max_format_width; in davinci_config_channel_size()
803 * left aligned formats: rotate w/ (slot_width - sample_width) in davinci_config_channel_size()
805 if ((mcasp->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) == in davinci_config_channel_size()
811 rx_rotate = (slot_width - sample_width) / 4; in davinci_config_channel_size()
814 /* mapping of the XSSZ bit-field as described in the datasheet */ in davinci_config_channel_size()
815 fmt = (slot_width >> 1) - 1; in davinci_config_channel_size()
817 if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) { in davinci_config_channel_size()
818 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXSSZ(fmt), in davinci_config_channel_size()
820 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSSZ(fmt), in davinci_config_channel_size()
822 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(tx_rotate), in davinci_config_channel_size()
824 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXROT(rx_rotate), in davinci_config_channel_size()
826 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXMASK_REG, mask); in davinci_config_channel_size()
829 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXMASK_REG, mask); in davinci_config_channel_size()
834 static int mcasp_common_hw_param(struct davinci_mcasp *mcasp, int stream, in mcasp_common_hw_param() argument
837 struct snd_dmaengine_dai_dma_data *dma_data = &mcasp->dma_data[stream]; in mcasp_common_hw_param()
841 u8 slots = mcasp->tdm_slots; in mcasp_common_hw_param()
842 u8 max_active_serializers = (channels + slots - 1) / slots; in mcasp_common_hw_param()
847 if (mcasp->version < MCASP_VERSION_3) in mcasp_common_hw_param()
848 mcasp_set_bits(mcasp, DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT); in mcasp_common_hw_param()
851 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF); in mcasp_common_hw_param()
852 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS); in mcasp_common_hw_param()
855 mcasp->active_serializers[SNDRV_PCM_STREAM_CAPTURE]; in mcasp_common_hw_param()
857 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF); in mcasp_common_hw_param()
858 mcasp_clr_bits(mcasp, DAVINCI_MCASP_REVTCTL_REG, RXDATADMADIS); in mcasp_common_hw_param()
860 mcasp->active_serializers[SNDRV_PCM_STREAM_PLAYBACK]; in mcasp_common_hw_param()
864 for (i = 0; i < mcasp->num_serializer; i++) { in mcasp_common_hw_param()
865 mcasp_set_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i), in mcasp_common_hw_param()
866 mcasp->serial_dir[i]); in mcasp_common_hw_param()
867 if (mcasp->serial_dir[i] == TX_MODE && in mcasp_common_hw_param()
869 mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i), in mcasp_common_hw_param()
870 mcasp->dismod, DISMOD_MASK); in mcasp_common_hw_param()
871 set_bit(PIN_BIT_AXR(i), &mcasp->pdir); in mcasp_common_hw_param()
873 } else if (mcasp->serial_dir[i] == RX_MODE && in mcasp_common_hw_param()
875 clear_bit(PIN_BIT_AXR(i), &mcasp->pdir); in mcasp_common_hw_param()
879 mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i), in mcasp_common_hw_param()
882 if (mcasp->serial_dir[i] != INACTIVE_MODE) in mcasp_common_hw_param()
883 mcasp_mod_bits(mcasp, in mcasp_common_hw_param()
885 mcasp->dismod, DISMOD_MASK); in mcasp_common_hw_param()
886 clear_bit(PIN_BIT_AXR(i), &mcasp->pdir); in mcasp_common_hw_param()
892 numevt = mcasp->txnumevt; in mcasp_common_hw_param()
893 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; in mcasp_common_hw_param()
896 numevt = mcasp->rxnumevt; in mcasp_common_hw_param()
897 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; in mcasp_common_hw_param()
901 dev_warn(mcasp->dev, "stream has more channels (%d) than are " in mcasp_common_hw_param()
902 "enabled in mcasp (%d)\n", channels, in mcasp_common_hw_param()
904 return -EINVAL; in mcasp_common_hw_param()
917 dma_data->maxburst = active_serializers; in mcasp_common_hw_param()
919 dma_data->maxburst = 0; in mcasp_common_hw_param()
926 dev_err(mcasp->dev, "Invalid combination of period words and " in mcasp_common_hw_param()
929 return -EINVAL; in mcasp_common_hw_param()
940 numevt -= active_serializers; in mcasp_common_hw_param()
944 mcasp_mod_bits(mcasp, reg, active_serializers, NUMDMA_MASK); in mcasp_common_hw_param()
945 mcasp_mod_bits(mcasp, reg, NUMEVT(numevt), NUMEVT_MASK); in mcasp_common_hw_param()
950 dma_data->maxburst = numevt; in mcasp_common_hw_param()
953 mcasp->active_serializers[stream] = active_serializers; in mcasp_common_hw_param()
958 static int mcasp_i2s_hw_param(struct davinci_mcasp *mcasp, int stream, in mcasp_i2s_hw_param() argument
967 total_slots = mcasp->tdm_slots; in mcasp_i2s_hw_param()
975 if (mcasp->tdm_mask[stream]) { in mcasp_i2s_hw_param()
976 active_slots = hweight32(mcasp->tdm_mask[stream]); in mcasp_i2s_hw_param()
977 active_serializers = (channels + active_slots - 1) / in mcasp_i2s_hw_param()
982 if ((1 << i) & mcasp->tdm_mask[stream]) { in mcasp_i2s_hw_param()
984 if (--active_slots <= 0) in mcasp_i2s_hw_param()
989 active_serializers = (channels + total_slots - 1) / total_slots; in mcasp_i2s_hw_param()
999 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC); in mcasp_i2s_hw_param()
1001 if (!mcasp->dat_port) in mcasp_i2s_hw_param()
1005 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, mask); in mcasp_i2s_hw_param()
1006 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, busel | TXORD); in mcasp_i2s_hw_param()
1007 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, in mcasp_i2s_hw_param()
1010 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXTDM_REG, mask); in mcasp_i2s_hw_param()
1011 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, busel | RXORD); in mcasp_i2s_hw_param()
1012 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, in mcasp_i2s_hw_param()
1015 * If McASP is set to be TX/RX synchronous and the playback is in mcasp_i2s_hw_param()
1019 if (mcasp_is_synchronous(mcasp) && !mcasp->channels) in mcasp_i2s_hw_param()
1020 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, in mcasp_i2s_hw_param()
1028 static int mcasp_dit_hw_param(struct davinci_mcasp *mcasp, in mcasp_dit_hw_param() argument
1036 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(6) | TXSSZ(15)); in mcasp_dit_hw_param()
1039 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE | FSXMOD(0x180)); in mcasp_dit_hw_param()
1042 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF); in mcasp_dit_hw_param()
1045 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE | TX_ASYNC); in mcasp_dit_hw_param()
1047 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS); in mcasp_dit_hw_param()
1050 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXDIV(3)); in mcasp_dit_hw_param()
1053 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXDITCTL_REG, DITEN); in mcasp_dit_hw_param()
1089 return -EINVAL; in mcasp_dit_hw_param()
1092 mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRA_REG, cs_value); in mcasp_dit_hw_param()
1093 mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRB_REG, cs_value); in mcasp_dit_hw_param()
1098 static int davinci_mcasp_calc_clk_div(struct davinci_mcasp *mcasp, in davinci_mcasp_calc_clk_div() argument
1102 u32 reg = mcasp_get_reg(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG); in davinci_mcasp_calc_clk_div()
1118 dev_warn(mcasp->dev, "Too fast reference clock (%u)\n", in davinci_mcasp_calc_clk_div()
1125 ((sysclk_freq / div) - bclk_freq) > in davinci_mcasp_calc_clk_div()
1126 (bclk_freq - (sysclk_freq / (div+1)))) { in davinci_mcasp_calc_clk_div()
1128 rem = rem - bclk_freq; in davinci_mcasp_calc_clk_div()
1132 (int)bclk_freq)) / div - 1000000; in davinci_mcasp_calc_clk_div()
1136 dev_info(mcasp->dev, "Sample-rate is off by %d PPM\n", in davinci_mcasp_calc_clk_div()
1139 __davinci_mcasp_set_clkdiv(mcasp, MCASP_CLKDIV_BCLK, div, 0); in davinci_mcasp_calc_clk_div()
1141 __davinci_mcasp_set_clkdiv(mcasp, MCASP_CLKDIV_AUXCLK, in davinci_mcasp_calc_clk_div()
1148 static inline u32 davinci_mcasp_tx_delay(struct davinci_mcasp *mcasp) in davinci_mcasp_tx_delay() argument
1150 if (!mcasp->txnumevt) in davinci_mcasp_tx_delay()
1153 return mcasp_get_reg(mcasp, mcasp->fifo_base + MCASP_WFIFOSTS_OFFSET); in davinci_mcasp_tx_delay()
1156 static inline u32 davinci_mcasp_rx_delay(struct davinci_mcasp *mcasp) in davinci_mcasp_rx_delay() argument
1158 if (!mcasp->rxnumevt) in davinci_mcasp_rx_delay()
1161 return mcasp_get_reg(mcasp, mcasp->fifo_base + MCASP_RFIFOSTS_OFFSET); in davinci_mcasp_rx_delay()
1168 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); in davinci_mcasp_delay() local
1171 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) in davinci_mcasp_delay()
1172 fifo_use = davinci_mcasp_tx_delay(mcasp); in davinci_mcasp_delay()
1174 fifo_use = davinci_mcasp_rx_delay(mcasp); in davinci_mcasp_delay()
1181 return fifo_use / substream->runtime->channels; in davinci_mcasp_delay()
1188 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); in davinci_mcasp_hw_params() local
1221 printk(KERN_WARNING "davinci-mcasp: unsupported PCM format"); in davinci_mcasp_hw_params()
1222 return -EINVAL; in davinci_mcasp_hw_params()
1225 ret = davinci_mcasp_set_dai_fmt(cpu_dai, mcasp->dai_fmt); in davinci_mcasp_hw_params()
1230 * If mcasp is BCLK master, and a BCLK divider was not provided by in davinci_mcasp_hw_params()
1233 if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) { in davinci_mcasp_hw_params()
1234 int slots = mcasp->tdm_slots; in davinci_mcasp_hw_params()
1238 if (mcasp->slot_width) in davinci_mcasp_hw_params()
1239 sbits = mcasp->slot_width; in davinci_mcasp_hw_params()
1241 davinci_mcasp_calc_clk_div(mcasp, mcasp->sysclk_freq, in davinci_mcasp_hw_params()
1245 ret = mcasp_common_hw_param(mcasp, substream->stream, in davinci_mcasp_hw_params()
1250 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE) in davinci_mcasp_hw_params()
1251 ret = mcasp_dit_hw_param(mcasp, params_rate(params)); in davinci_mcasp_hw_params()
1253 ret = mcasp_i2s_hw_param(mcasp, substream->stream, in davinci_mcasp_hw_params()
1259 davinci_config_channel_size(mcasp, word_length); in davinci_mcasp_hw_params()
1261 if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE) { in davinci_mcasp_hw_params()
1262 mcasp->channels = channels; in davinci_mcasp_hw_params()
1263 if (!mcasp->max_format_width) in davinci_mcasp_hw_params()
1264 mcasp->max_format_width = word_length; in davinci_mcasp_hw_params()
1273 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); in davinci_mcasp_trigger() local
1280 davinci_mcasp_start(mcasp, substream->stream); in davinci_mcasp_trigger()
1285 davinci_mcasp_stop(mcasp, substream->stream); in davinci_mcasp_trigger()
1289 ret = -EINVAL; in davinci_mcasp_trigger()
1298 struct davinci_mcasp_ruledata *rd = rule->private; in davinci_mcasp_hw_rule_slot_width()
1304 slot_width = rd->mcasp->slot_width; in davinci_mcasp_hw_rule_slot_width()
1320 struct davinci_mcasp_ruledata *rd = rule->private; in davinci_mcasp_hw_rule_format_width()
1326 format_width = rd->mcasp->max_format_width; in davinci_mcasp_hw_rule_format_width()
1349 struct davinci_mcasp_ruledata *rd = rule->private; in davinci_mcasp_hw_rule_rate()
1353 int slots = rd->mcasp->tdm_slots; in davinci_mcasp_hw_rule_rate()
1357 if (rd->mcasp->slot_width) in davinci_mcasp_hw_rule_rate()
1358 sbits = rd->mcasp->slot_width; in davinci_mcasp_hw_rule_rate()
1370 if (rd->mcasp->auxclk_fs_ratio) in davinci_mcasp_hw_rule_rate()
1372 rd->mcasp->auxclk_fs_ratio; in davinci_mcasp_hw_rule_rate()
1374 sysclk_freq = rd->mcasp->sysclk_freq; in davinci_mcasp_hw_rule_rate()
1376 ppm = davinci_mcasp_calc_clk_div(rd->mcasp, sysclk_freq, in davinci_mcasp_hw_rule_rate()
1388 dev_dbg(rd->mcasp->dev, in davinci_mcasp_hw_rule_rate()
1389 "Frequencies %d-%d -> %d-%d for %d sbits and %d tdm slots\n", in davinci_mcasp_hw_rule_rate()
1390 ri->min, ri->max, range.min, range.max, sbits, slots); in davinci_mcasp_hw_rule_rate()
1392 return snd_interval_refine(hw_param_interval(params, rule->var), in davinci_mcasp_hw_rule_rate()
1399 struct davinci_mcasp_ruledata *rd = rule->private; in davinci_mcasp_hw_rule_format()
1403 int slots = rd->mcasp->tdm_slots; in davinci_mcasp_hw_rule_format()
1414 if (rd->mcasp->auxclk_fs_ratio) in davinci_mcasp_hw_rule_format()
1416 rd->mcasp->auxclk_fs_ratio; in davinci_mcasp_hw_rule_format()
1418 sysclk_freq = rd->mcasp->sysclk_freq; in davinci_mcasp_hw_rule_format()
1420 if (rd->mcasp->slot_width) in davinci_mcasp_hw_rule_format()
1421 sbits = rd->mcasp->slot_width; in davinci_mcasp_hw_rule_format()
1423 ppm = davinci_mcasp_calc_clk_div(rd->mcasp, sysclk_freq, in davinci_mcasp_hw_rule_format()
1432 dev_dbg(rd->mcasp->dev, in davinci_mcasp_hw_rule_format()
1456 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); in davinci_mcasp_startup() local
1458 &mcasp->ruledata[substream->stream]; in davinci_mcasp_startup()
1461 int tdm_slots = mcasp->tdm_slots; in davinci_mcasp_startup()
1464 if (mcasp->substreams[substream->stream]) in davinci_mcasp_startup()
1465 return -EBUSY; in davinci_mcasp_startup()
1467 mcasp->substreams[substream->stream] = substream; in davinci_mcasp_startup()
1469 if (mcasp->tdm_mask[substream->stream]) in davinci_mcasp_startup()
1470 tdm_slots = hweight32(mcasp->tdm_mask[substream->stream]); in davinci_mcasp_startup()
1472 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE) in davinci_mcasp_startup()
1479 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) in davinci_mcasp_startup()
1484 for (i = 0; i < mcasp->num_serializer; i++) { in davinci_mcasp_startup()
1485 if (mcasp->serial_dir[i] == dir) in davinci_mcasp_startup()
1488 ruledata->serializers = max_channels; in davinci_mcasp_startup()
1489 ruledata->mcasp = mcasp; in davinci_mcasp_startup()
1498 if (mcasp->channels && mcasp->channels < max_channels && in davinci_mcasp_startup()
1499 ruledata->serializers == 1) in davinci_mcasp_startup()
1500 max_channels = mcasp->channels; in davinci_mcasp_startup()
1508 snd_pcm_hw_constraint_minmax(substream->runtime, in davinci_mcasp_startup()
1512 snd_pcm_hw_constraint_list(substream->runtime, in davinci_mcasp_startup()
1514 &mcasp->chconstr[substream->stream]); in davinci_mcasp_startup()
1516 if (mcasp->max_format_width) { in davinci_mcasp_startup()
1521 ret = snd_pcm_hw_rule_add(substream->runtime, 0, in davinci_mcasp_startup()
1525 SNDRV_PCM_HW_PARAM_FORMAT, -1); in davinci_mcasp_startup()
1529 else if (mcasp->slot_width) { in davinci_mcasp_startup()
1531 ret = snd_pcm_hw_rule_add(substream->runtime, 0, in davinci_mcasp_startup()
1535 SNDRV_PCM_HW_PARAM_FORMAT, -1); in davinci_mcasp_startup()
1544 if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) { in davinci_mcasp_startup()
1545 ret = snd_pcm_hw_rule_add(substream->runtime, 0, in davinci_mcasp_startup()
1549 SNDRV_PCM_HW_PARAM_FORMAT, -1); in davinci_mcasp_startup()
1552 ret = snd_pcm_hw_rule_add(substream->runtime, 0, in davinci_mcasp_startup()
1556 SNDRV_PCM_HW_PARAM_RATE, -1); in davinci_mcasp_startup()
1561 snd_pcm_hw_rule_add(substream->runtime, 0, in davinci_mcasp_startup()
1564 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, -1); in davinci_mcasp_startup()
1572 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); in davinci_mcasp_shutdown() local
1574 mcasp->substreams[substream->stream] = NULL; in davinci_mcasp_shutdown()
1575 mcasp->active_serializers[substream->stream] = 0; in davinci_mcasp_shutdown()
1577 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE) in davinci_mcasp_shutdown()
1581 mcasp->channels = 0; in davinci_mcasp_shutdown()
1582 mcasp->max_format_width = 0; in davinci_mcasp_shutdown()
1600 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); in davinci_mcasp_dai_probe() local
1602 dai->playback_dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK]; in davinci_mcasp_dai_probe()
1603 dai->capture_dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE]; in davinci_mcasp_dai_probe()
1623 .name = "davinci-mcasp.0",
1644 .name = "davinci-mcasp.1",
1659 .name = "davinci-mcasp",
1690 .compatible = "ti,dm646x-mcasp-audio",
1694 .compatible = "ti,da830-mcasp-audio",
1698 .compatible = "ti,am33xx-mcasp-audio",
1702 .compatible = "ti,dra7-mcasp-audio",
1711 struct device_node *node = pdev->dev.of_node; in mcasp_reparent_fck()
1723 dev_warn(&pdev->dev, "Update the bindings to use assigned-clocks!\n"); in mcasp_reparent_fck()
1725 gfclk = clk_get(&pdev->dev, "fck"); in mcasp_reparent_fck()
1727 dev_err(&pdev->dev, "failed to get fck\n"); in mcasp_reparent_fck()
1733 dev_err(&pdev->dev, "failed to get parent clock\n"); in mcasp_reparent_fck()
1740 dev_err(&pdev->dev, "failed to reparent fck\n"); in mcasp_reparent_fck()
1754 struct device_node *np = pdev->dev.of_node; in davinci_mcasp_set_pdata_from_of()
1757 of_match_device(mcasp_dt_ids, &pdev->dev); in davinci_mcasp_set_pdata_from_of()
1764 if (pdev->dev.platform_data) { in davinci_mcasp_set_pdata_from_of()
1765 pdata = pdev->dev.platform_data; in davinci_mcasp_set_pdata_from_of()
1766 pdata->dismod = DISMOD_LOW; in davinci_mcasp_set_pdata_from_of()
1769 pdata = devm_kmemdup(&pdev->dev, match->data, sizeof(*pdata), in davinci_mcasp_set_pdata_from_of()
1775 ret = -EINVAL; in davinci_mcasp_set_pdata_from_of()
1779 ret = of_property_read_u32(np, "op-mode", &val); in davinci_mcasp_set_pdata_from_of()
1781 pdata->op_mode = val; in davinci_mcasp_set_pdata_from_of()
1783 ret = of_property_read_u32(np, "tdm-slots", &val); in davinci_mcasp_set_pdata_from_of()
1786 dev_err(&pdev->dev, in davinci_mcasp_set_pdata_from_of()
1787 "tdm-slots must be in rage [2-32]\n"); in davinci_mcasp_set_pdata_from_of()
1788 ret = -EINVAL; in davinci_mcasp_set_pdata_from_of()
1792 pdata->tdm_slots = val; in davinci_mcasp_set_pdata_from_of()
1795 of_serial_dir32 = of_get_property(np, "serial-dir", &val); in davinci_mcasp_set_pdata_from_of()
1798 u8 *of_serial_dir = devm_kzalloc(&pdev->dev, in davinci_mcasp_set_pdata_from_of()
1802 ret = -ENOMEM; in davinci_mcasp_set_pdata_from_of()
1809 pdata->num_serializer = val; in davinci_mcasp_set_pdata_from_of()
1810 pdata->serial_dir = of_serial_dir; in davinci_mcasp_set_pdata_from_of()
1813 ret = of_property_match_string(np, "dma-names", "tx"); in davinci_mcasp_set_pdata_from_of()
1817 ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret, in davinci_mcasp_set_pdata_from_of()
1822 pdata->tx_dma_channel = dma_spec.args[0]; in davinci_mcasp_set_pdata_from_of()
1825 if (pdata->op_mode != DAVINCI_MCASP_DIT_MODE) { in davinci_mcasp_set_pdata_from_of()
1826 ret = of_property_match_string(np, "dma-names", "rx"); in davinci_mcasp_set_pdata_from_of()
1830 ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret, in davinci_mcasp_set_pdata_from_of()
1835 pdata->rx_dma_channel = dma_spec.args[0]; in davinci_mcasp_set_pdata_from_of()
1838 ret = of_property_read_u32(np, "tx-num-evt", &val); in davinci_mcasp_set_pdata_from_of()
1840 pdata->txnumevt = val; in davinci_mcasp_set_pdata_from_of()
1842 ret = of_property_read_u32(np, "rx-num-evt", &val); in davinci_mcasp_set_pdata_from_of()
1844 pdata->rxnumevt = val; in davinci_mcasp_set_pdata_from_of()
1846 ret = of_property_read_u32(np, "sram-size-playback", &val); in davinci_mcasp_set_pdata_from_of()
1848 pdata->sram_size_playback = val; in davinci_mcasp_set_pdata_from_of()
1850 ret = of_property_read_u32(np, "sram-size-capture", &val); in davinci_mcasp_set_pdata_from_of()
1852 pdata->sram_size_capture = val; in davinci_mcasp_set_pdata_from_of()
1857 pdata->dismod = DISMOD_VAL(val); in davinci_mcasp_set_pdata_from_of()
1859 dev_warn(&pdev->dev, "Invalid dismod value: %u\n", val); in davinci_mcasp_set_pdata_from_of()
1860 pdata->dismod = DISMOD_LOW; in davinci_mcasp_set_pdata_from_of()
1863 pdata->dismod = DISMOD_LOW; in davinci_mcasp_set_pdata_from_of()
1870 dev_err(&pdev->dev, "Error populating platform data, err %d\n", in davinci_mcasp_set_pdata_from_of()
1884 static int davinci_mcasp_get_dma_type(struct davinci_mcasp *mcasp) in davinci_mcasp_get_dma_type() argument
1890 if (!mcasp->dev->of_node) in davinci_mcasp_get_dma_type()
1893 tmp = mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK].filter_data; in davinci_mcasp_get_dma_type()
1894 chan = dma_request_chan(mcasp->dev, tmp); in davinci_mcasp_get_dma_type()
1896 if (PTR_ERR(chan) != -EPROBE_DEFER) in davinci_mcasp_get_dma_type()
1897 dev_err(mcasp->dev, in davinci_mcasp_get_dma_type()
1902 if (WARN_ON(!chan->device || !chan->device->dev)) { in davinci_mcasp_get_dma_type()
1904 return -EINVAL; in davinci_mcasp_get_dma_type()
1907 if (chan->device->dev->of_node) in davinci_mcasp_get_dma_type()
1908 ret = of_property_read_string(chan->device->dev->of_node, in davinci_mcasp_get_dma_type()
1911 dev_dbg(mcasp->dev, "DMA controller has no of-node\n"); in davinci_mcasp_get_dma_type()
1917 dev_dbg(mcasp->dev, "DMA controller compatible = \"%s\"\n", tmp); in davinci_mcasp_get_dma_type()
1931 if (pdata->version != MCASP_VERSION_4) in davinci_mcasp_txdma_offset()
1932 return pdata->tx_dma_offset; in davinci_mcasp_txdma_offset()
1934 for (i = 0; i < pdata->num_serializer; i++) { in davinci_mcasp_txdma_offset()
1935 if (pdata->serial_dir[i] == TX_MODE) { in davinci_mcasp_txdma_offset()
1954 if (pdata->version != MCASP_VERSION_4) in davinci_mcasp_rxdma_offset()
1955 return pdata->rx_dma_offset; in davinci_mcasp_rxdma_offset()
1957 for (i = 0; i < pdata->num_serializer; i++) { in davinci_mcasp_rxdma_offset()
1958 if (pdata->serial_dir[i] == RX_MODE) { in davinci_mcasp_rxdma_offset()
1975 struct davinci_mcasp *mcasp = gpiochip_get_data(chip); in davinci_mcasp_gpio_request() local
1977 if (mcasp->num_serializer && offset < mcasp->num_serializer && in davinci_mcasp_gpio_request()
1978 mcasp->serial_dir[offset] != INACTIVE_MODE) { in davinci_mcasp_gpio_request()
1979 dev_err(mcasp->dev, "AXR%u pin is used for audio\n", offset); in davinci_mcasp_gpio_request()
1980 return -EBUSY; in davinci_mcasp_gpio_request()
1985 return pm_runtime_get_sync(mcasp->dev); in davinci_mcasp_gpio_request()
1990 struct davinci_mcasp *mcasp = gpiochip_get_data(chip); in davinci_mcasp_gpio_free() local
1993 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(offset)); in davinci_mcasp_gpio_free()
1995 /* Set the pin as McASP pin */ in davinci_mcasp_gpio_free()
1996 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PFUNC_REG, BIT(offset)); in davinci_mcasp_gpio_free()
1998 pm_runtime_put_sync(mcasp->dev); in davinci_mcasp_gpio_free()
2004 struct davinci_mcasp *mcasp = gpiochip_get_data(chip); in davinci_mcasp_gpio_direction_out() local
2008 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset)); in davinci_mcasp_gpio_direction_out()
2010 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset)); in davinci_mcasp_gpio_direction_out()
2012 val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PFUNC_REG); in davinci_mcasp_gpio_direction_out()
2015 mcasp_set_bits(mcasp, DAVINCI_MCASP_PFUNC_REG, BIT(offset)); in davinci_mcasp_gpio_direction_out()
2018 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(offset)); in davinci_mcasp_gpio_direction_out()
2027 struct davinci_mcasp *mcasp = gpiochip_get_data(chip); in davinci_mcasp_gpio_set() local
2030 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset)); in davinci_mcasp_gpio_set()
2032 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset)); in davinci_mcasp_gpio_set()
2038 struct davinci_mcasp *mcasp = gpiochip_get_data(chip); in davinci_mcasp_gpio_direction_in() local
2041 val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PFUNC_REG); in davinci_mcasp_gpio_direction_in()
2044 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(offset)); in davinci_mcasp_gpio_direction_in()
2047 mcasp_set_bits(mcasp, DAVINCI_MCASP_PFUNC_REG, BIT(offset)); in davinci_mcasp_gpio_direction_in()
2055 struct davinci_mcasp *mcasp = gpiochip_get_data(chip); in davinci_mcasp_gpio_get() local
2058 val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PDSET_REG); in davinci_mcasp_gpio_get()
2068 struct davinci_mcasp *mcasp = gpiochip_get_data(chip); in davinci_mcasp_gpio_get_direction() local
2071 val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PDIR_REG); in davinci_mcasp_gpio_get_direction()
2087 .base = -1,
2091 static int davinci_mcasp_init_gpiochip(struct davinci_mcasp *mcasp) in davinci_mcasp_init_gpiochip() argument
2093 if (!of_property_read_bool(mcasp->dev->of_node, "gpio-controller")) in davinci_mcasp_init_gpiochip()
2096 mcasp->gpio_chip = davinci_mcasp_template_chip; in davinci_mcasp_init_gpiochip()
2097 mcasp->gpio_chip.label = dev_name(mcasp->dev); in davinci_mcasp_init_gpiochip()
2098 mcasp->gpio_chip.parent = mcasp->dev; in davinci_mcasp_init_gpiochip()
2100 mcasp->gpio_chip.of_node = mcasp->dev->of_node; in davinci_mcasp_init_gpiochip()
2103 return devm_gpiochip_add_data(mcasp->dev, &mcasp->gpio_chip, mcasp); in davinci_mcasp_init_gpiochip()
2107 static inline int davinci_mcasp_init_gpiochip(struct davinci_mcasp *mcasp) in davinci_mcasp_init_gpiochip() argument
2113 static int davinci_mcasp_get_dt_params(struct davinci_mcasp *mcasp) in davinci_mcasp_get_dt_params() argument
2115 struct device_node *np = mcasp->dev->of_node; in davinci_mcasp_get_dt_params()
2122 ret = of_property_read_u32(np, "auxclk-fs-ratio", &val); in davinci_mcasp_get_dt_params()
2124 mcasp->auxclk_fs_ratio = val; in davinci_mcasp_get_dt_params()
2134 struct davinci_mcasp *mcasp; in davinci_mcasp_probe() local
2140 if (!pdev->dev.platform_data && !pdev->dev.of_node) { in davinci_mcasp_probe()
2141 dev_err(&pdev->dev, "No platform data supplied\n"); in davinci_mcasp_probe()
2142 return -EINVAL; in davinci_mcasp_probe()
2145 mcasp = devm_kzalloc(&pdev->dev, sizeof(struct davinci_mcasp), in davinci_mcasp_probe()
2147 if (!mcasp) in davinci_mcasp_probe()
2148 return -ENOMEM; in davinci_mcasp_probe()
2152 dev_err(&pdev->dev, "no platform data\n"); in davinci_mcasp_probe()
2153 return -EINVAL; in davinci_mcasp_probe()
2158 dev_warn(&pdev->dev, in davinci_mcasp_probe()
2162 dev_err(&pdev->dev, "no mem resource?\n"); in davinci_mcasp_probe()
2163 return -ENODEV; in davinci_mcasp_probe()
2167 mcasp->base = devm_ioremap_resource(&pdev->dev, mem); in davinci_mcasp_probe()
2168 if (IS_ERR(mcasp->base)) in davinci_mcasp_probe()
2169 return PTR_ERR(mcasp->base); in davinci_mcasp_probe()
2171 pm_runtime_enable(&pdev->dev); in davinci_mcasp_probe()
2173 mcasp->op_mode = pdata->op_mode; in davinci_mcasp_probe()
2175 if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE) { in davinci_mcasp_probe()
2176 if (pdata->tdm_slots < 2) { in davinci_mcasp_probe()
2177 dev_err(&pdev->dev, "invalid tdm slots: %d\n", in davinci_mcasp_probe()
2178 pdata->tdm_slots); in davinci_mcasp_probe()
2179 mcasp->tdm_slots = 2; in davinci_mcasp_probe()
2180 } else if (pdata->tdm_slots > 32) { in davinci_mcasp_probe()
2181 dev_err(&pdev->dev, "invalid tdm slots: %d\n", in davinci_mcasp_probe()
2182 pdata->tdm_slots); in davinci_mcasp_probe()
2183 mcasp->tdm_slots = 32; in davinci_mcasp_probe()
2185 mcasp->tdm_slots = pdata->tdm_slots; in davinci_mcasp_probe()
2189 mcasp->num_serializer = pdata->num_serializer; in davinci_mcasp_probe()
2191 mcasp->context.xrsr_regs = devm_kcalloc(&pdev->dev, in davinci_mcasp_probe()
2192 mcasp->num_serializer, sizeof(u32), in davinci_mcasp_probe()
2194 if (!mcasp->context.xrsr_regs) { in davinci_mcasp_probe()
2195 ret = -ENOMEM; in davinci_mcasp_probe()
2199 mcasp->serial_dir = pdata->serial_dir; in davinci_mcasp_probe()
2200 mcasp->version = pdata->version; in davinci_mcasp_probe()
2201 mcasp->txnumevt = pdata->txnumevt; in davinci_mcasp_probe()
2202 mcasp->rxnumevt = pdata->rxnumevt; in davinci_mcasp_probe()
2203 mcasp->dismod = pdata->dismod; in davinci_mcasp_probe()
2205 mcasp->dev = &pdev->dev; in davinci_mcasp_probe()
2209 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_common", in davinci_mcasp_probe()
2210 dev_name(&pdev->dev)); in davinci_mcasp_probe()
2212 ret = -ENOMEM; in davinci_mcasp_probe()
2215 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, in davinci_mcasp_probe()
2218 irq_name, mcasp); in davinci_mcasp_probe()
2220 dev_err(&pdev->dev, "common IRQ request failed\n"); in davinci_mcasp_probe()
2224 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN; in davinci_mcasp_probe()
2225 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN; in davinci_mcasp_probe()
2230 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_rx", in davinci_mcasp_probe()
2231 dev_name(&pdev->dev)); in davinci_mcasp_probe()
2233 ret = -ENOMEM; in davinci_mcasp_probe()
2236 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, in davinci_mcasp_probe()
2238 IRQF_ONESHOT, irq_name, mcasp); in davinci_mcasp_probe()
2240 dev_err(&pdev->dev, "RX IRQ request failed\n"); in davinci_mcasp_probe()
2244 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN; in davinci_mcasp_probe()
2249 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_tx", in davinci_mcasp_probe()
2250 dev_name(&pdev->dev)); in davinci_mcasp_probe()
2252 ret = -ENOMEM; in davinci_mcasp_probe()
2255 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, in davinci_mcasp_probe()
2257 IRQF_ONESHOT, irq_name, mcasp); in davinci_mcasp_probe()
2259 dev_err(&pdev->dev, "TX IRQ request failed\n"); in davinci_mcasp_probe()
2263 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN; in davinci_mcasp_probe()
2268 mcasp->dat_port = true; in davinci_mcasp_probe()
2270 dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK]; in davinci_mcasp_probe()
2272 dma_data->addr = dat->start; in davinci_mcasp_probe()
2274 dma_data->addr = mem->start + davinci_mcasp_txdma_offset(pdata); in davinci_mcasp_probe()
2276 dma = &mcasp->dma_request[SNDRV_PCM_STREAM_PLAYBACK]; in davinci_mcasp_probe()
2279 *dma = res->start; in davinci_mcasp_probe()
2281 *dma = pdata->tx_dma_channel; in davinci_mcasp_probe()
2283 /* dmaengine filter data for DT and non-DT boot */ in davinci_mcasp_probe()
2284 if (pdev->dev.of_node) in davinci_mcasp_probe()
2285 dma_data->filter_data = "tx"; in davinci_mcasp_probe()
2287 dma_data->filter_data = dma; in davinci_mcasp_probe()
2290 if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) { in davinci_mcasp_probe()
2291 dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE]; in davinci_mcasp_probe()
2293 dma_data->addr = dat->start; in davinci_mcasp_probe()
2295 dma_data->addr = in davinci_mcasp_probe()
2296 mem->start + davinci_mcasp_rxdma_offset(pdata); in davinci_mcasp_probe()
2298 dma = &mcasp->dma_request[SNDRV_PCM_STREAM_CAPTURE]; in davinci_mcasp_probe()
2301 *dma = res->start; in davinci_mcasp_probe()
2303 *dma = pdata->rx_dma_channel; in davinci_mcasp_probe()
2305 /* dmaengine filter data for DT and non-DT boot */ in davinci_mcasp_probe()
2306 if (pdev->dev.of_node) in davinci_mcasp_probe()
2307 dma_data->filter_data = "rx"; in davinci_mcasp_probe()
2309 dma_data->filter_data = dma; in davinci_mcasp_probe()
2312 if (mcasp->version < MCASP_VERSION_3) { in davinci_mcasp_probe()
2313 mcasp->fifo_base = DAVINCI_MCASP_V2_AFIFO_BASE; in davinci_mcasp_probe()
2314 /* dma_params->dma_addr is pointing to the data port address */ in davinci_mcasp_probe()
2315 mcasp->dat_port = true; in davinci_mcasp_probe()
2317 mcasp->fifo_base = DAVINCI_MCASP_V3_AFIFO_BASE; in davinci_mcasp_probe()
2327 mcasp->chconstr[SNDRV_PCM_STREAM_PLAYBACK].list = in davinci_mcasp_probe()
2328 devm_kcalloc(mcasp->dev, in davinci_mcasp_probe()
2329 32 + mcasp->num_serializer - 1, in davinci_mcasp_probe()
2333 mcasp->chconstr[SNDRV_PCM_STREAM_CAPTURE].list = in davinci_mcasp_probe()
2334 devm_kcalloc(mcasp->dev, in davinci_mcasp_probe()
2335 32 + mcasp->num_serializer - 1, in davinci_mcasp_probe()
2339 if (!mcasp->chconstr[SNDRV_PCM_STREAM_PLAYBACK].list || in davinci_mcasp_probe()
2340 !mcasp->chconstr[SNDRV_PCM_STREAM_CAPTURE].list) { in davinci_mcasp_probe()
2341 ret = -ENOMEM; in davinci_mcasp_probe()
2345 ret = davinci_mcasp_set_ch_constraints(mcasp); in davinci_mcasp_probe()
2349 dev_set_drvdata(&pdev->dev, mcasp); in davinci_mcasp_probe()
2353 /* All PINS as McASP */ in davinci_mcasp_probe()
2354 pm_runtime_get_sync(mcasp->dev); in davinci_mcasp_probe()
2355 mcasp_set_reg(mcasp, DAVINCI_MCASP_PFUNC_REG, 0x00000000); in davinci_mcasp_probe()
2356 pm_runtime_put(mcasp->dev); in davinci_mcasp_probe()
2358 ret = davinci_mcasp_init_gpiochip(mcasp); in davinci_mcasp_probe()
2362 ret = davinci_mcasp_get_dt_params(mcasp); in davinci_mcasp_probe()
2364 return -EINVAL; in davinci_mcasp_probe()
2366 ret = devm_snd_soc_register_component(&pdev->dev, in davinci_mcasp_probe()
2368 &davinci_mcasp_dai[pdata->op_mode], 1); in davinci_mcasp_probe()
2373 ret = davinci_mcasp_get_dma_type(mcasp); in davinci_mcasp_probe()
2376 ret = edma_pcm_platform_register(&pdev->dev); in davinci_mcasp_probe()
2379 ret = sdma_pcm_platform_register(&pdev->dev, "tx", "rx"); in davinci_mcasp_probe()
2382 ret = udma_pcm_platform_register(&pdev->dev); in davinci_mcasp_probe()
2385 dev_err(&pdev->dev, "No DMA controller found (%d)\n", ret); in davinci_mcasp_probe()
2386 case -EPROBE_DEFER: in davinci_mcasp_probe()
2392 dev_err(&pdev->dev, "register PCM failed: %d\n", ret); in davinci_mcasp_probe()
2399 pm_runtime_disable(&pdev->dev); in davinci_mcasp_probe()
2405 pm_runtime_disable(&pdev->dev); in davinci_mcasp_remove()
2413 struct davinci_mcasp *mcasp = dev_get_drvdata(dev); in davinci_mcasp_runtime_suspend() local
2414 struct davinci_mcasp_context *context = &mcasp->context; in davinci_mcasp_runtime_suspend()
2419 context->config_regs[i] = mcasp_get_reg(mcasp, context_regs[i]); in davinci_mcasp_runtime_suspend()
2421 if (mcasp->txnumevt) { in davinci_mcasp_runtime_suspend()
2422 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; in davinci_mcasp_runtime_suspend()
2423 context->afifo_regs[0] = mcasp_get_reg(mcasp, reg); in davinci_mcasp_runtime_suspend()
2425 if (mcasp->rxnumevt) { in davinci_mcasp_runtime_suspend()
2426 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; in davinci_mcasp_runtime_suspend()
2427 context->afifo_regs[1] = mcasp_get_reg(mcasp, reg); in davinci_mcasp_runtime_suspend()
2430 for (i = 0; i < mcasp->num_serializer; i++) in davinci_mcasp_runtime_suspend()
2431 context->xrsr_regs[i] = mcasp_get_reg(mcasp, in davinci_mcasp_runtime_suspend()
2439 struct davinci_mcasp *mcasp = dev_get_drvdata(dev); in davinci_mcasp_runtime_resume() local
2440 struct davinci_mcasp_context *context = &mcasp->context; in davinci_mcasp_runtime_resume()
2445 mcasp_set_reg(mcasp, context_regs[i], context->config_regs[i]); in davinci_mcasp_runtime_resume()
2447 if (mcasp->txnumevt) { in davinci_mcasp_runtime_resume()
2448 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; in davinci_mcasp_runtime_resume()
2449 mcasp_set_reg(mcasp, reg, context->afifo_regs[0]); in davinci_mcasp_runtime_resume()
2451 if (mcasp->rxnumevt) { in davinci_mcasp_runtime_resume()
2452 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; in davinci_mcasp_runtime_resume()
2453 mcasp_set_reg(mcasp, reg, context->afifo_regs[1]); in davinci_mcasp_runtime_resume()
2456 for (i = 0; i < mcasp->num_serializer; i++) in davinci_mcasp_runtime_resume()
2457 mcasp_set_reg(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i), in davinci_mcasp_runtime_resume()
2458 context->xrsr_regs[i]); in davinci_mcasp_runtime_resume()
2475 .name = "davinci-mcasp",
2484 MODULE_DESCRIPTION("TI DAVINCI McASP SoC Interface");