Lines Matching +full:c +full:- +full:states

1 .. SPDX-License-Identifier: GPL-2.0
24 Documentation/admin-guide/pm/cpuidle.rst if you have not done that yet.]
28 processor's functional blocks into low-power states.  That instruction takes two
38 only way to pass early-configuration-time parameters to it is via the kernel
42 .. _intel-idle-enumeration-of-states:
44 Enumeration of Idle States
50 as C-states (in the ACPI terminology) or idle states.  The list of meaningful
51 ``MWAIT`` hint values and idle states (i.e. low-power configurations of the
55 In order to create a list of available idle states required by the ``CPUIdle``
56 subsystem (see :ref:`idle-states-representation` in
57 Documentation/admin-guide/pm/cpuidle.rst),
58 ``intel_idle`` can use two sources of information: static tables of idle states
66 `below <intel-idle-parameters_>`_.]
69 states, ``intel_idle`` first looks for a ``_CST`` object under one of the ACPI
72 ``CPUIdle`` subsystem expects that the list of idle states supplied by the
76 state description and such that all of the idle states included in its return
81 descriptions extracted from it are stored in a preliminary list of idle states
83 configured to ignore the ACPI tables; see `below <intel-idle-parameters_>`_.]
85 Next, the first (index 0) entry in the list of available idle states is
86 initialized to represent a "polling idle state" (a pseudo-idle state in which
92 the "internal" table is the primary source of information on idle states and the
93 information from it is copied to the final list of available idle states.  If
94 using the ACPI tables for the enumeration of idle states is not required
98 states may not be enabled by default if there are no matching entries in the
99 preliminary list of idle states coming from the ACPI tables.  In that case user
100 space still can enable them later (on a per-CPU basis) with the help of
102 :ref:`idle-states-representation` in
103 Documentation/admin-guide/pm/cpuidle.rst).  This basically means that
104 the idle states "known" to the driver may not be enabled by default if they have
108 supports ``MWAIT``, the preliminary list of idle states coming from the ACPI
112 entry in the final list of idle states.  The name of the idle state represented
117 C1-type idle states the exit latency value is also used as the target residency
118 (for compatibility with the majority of the "internal" tables of idle states for
123 All of the idle states in the final list are enabled by default in this case.
126 .. _intel-idle-initialization:
136 driver, which determines the idle states enumeration method (see
137 `above <intel-idle-enumeration-of-states_>`_), and whether or not the processor
144 `below <intel-idle-parameters_>`_), the idle states information provided by the
148 available idle states is created as explained
149 `above <intel-idle-enumeration-of-states_>`_.
158 optionally performs some CPU-specific initialization actions that may be
162 .. _intel-idle-parameters:
178 of idle states supplied to the ``CPUIdle`` core during the registration of the
179 driver.  It is also the maximum number of regular (non-polling) idle states that
180 can be used by ``intel_idle``, so the enumeration of idle states is terminated
181 after finding that number of usable idle states (the other idle states that
184 ``intel_idle`` from exposing idle states that are regarded as "too deep" for
188 states in question cannot be enabled during system startup, because in the
190 QoS) feature can be used to prevent ``CPUIdle`` from touching those idle states
191 even if they have been enumerated (see :ref:`cpu-pm-qos` in
192 Documentation/admin-guide/pm/cpuidle.rst).
202 list of idle states to be disabled by default in the form of a bitmask.
205 the indices of idle states to be disabled by default (as reflected by the names
208 idle state; see :ref:`idle-states-representation` in
209 Documentation/admin-guide/pm/cpuidle.rst).
212 states 0 and 1 by default, and if it is equal to 8, idle state 3 will be
216 The idle states disabled this way can be enabled (on a per-CPU basis) from user
220 .. _intel-idle-core-and-package-idle-states:
222 Core and Package Levels of Idle States
226 least) two levels of idle states (or C-states).  One level, referred to as
227 "core C-states", covers individual cores in the processor, whereas the other
228 level, referred to as "package C-states", covers the entire processor package
232 Some of the ``MWAIT`` hint values allow the processor to use core C-states only
236 with the given hint value) into a specific core C-state and then (if possible)
237 to enter a specific package C-state at the deeper level.  For example, the
239 put the target core into the low-power state referred to as "core ``C3``" (or
244 including some non-CPU components such as a GPU or a memory controller) into the
245 low-power state referred to as "package ``C3``" (or ``PC3``), which happens if
248 be required to be in a certain GPU-specific low-power state for ``PC3`` to be
251 As a rule, there is no simple way to make the processor use core C-states only
252 if the conditions for entering the corresponding package C-states are met, so
253 the logical CPU executing ``MWAIT`` with a hint value that is not core-level
255 enter a package C-state.  [That is why the exit latency and target residency
257 tables of idle states in ``intel_idle`` reflect the properties of package
258 C-states.]  If using package C-states is not desirable at all, either
259 :ref:`PM QoS <cpu-pm-qos>` or the ``max_cstate`` module parameter of
260 ``intel_idle`` described `above <intel-idle-parameters_>`_ must be used to
261 restrict the range of permissible idle states to the ones with core-level only
268 .. [1] *Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2B*,
269 …www.intel.com/content/www/us/en/architecture-and-technology/64-ia-32-architectures-software-develo…