Lines Matching +full:1 +full:c0
34 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
37 mcr p15, 0, r0, c1, c0, 0 @ disable caches
57 mrc p15, 0, r2, c1, c0, 0 @ ctrl register
59 THUMB( bic r2, r2, #1 << 30 ) @ SCTLR.TE (Thumb exceptions)
60 mcr p15, 0, r2, c1, c0, 0 @ disable MMU
85 ALT_UP_B(1f)
87 1: dcache_line_size r2, r3
88 2: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
136 mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID
137 mrc p15, 0, r5, c13, c0, 3 @ User r/o thread ID
140 mrc p15, 0, r6, c3, c0, 0 @ Domain ID
142 mrrc p15, 1, r5, r7, c2 @ TTB 1
144 mrc p15, 0, r7, c2, c0, 1 @ TTB 1
146 mrc p15, 0, r11, c2, c0, 2 @ TTB control register
148 mrc p15, 0, r8, c1, c0, 0 @ Control register
149 mrc p15, 0, r9, c1, c0, 1 @ Auxiliary control register
150 mrc p15, 0, r10, c1, c0, 2 @ Co-processor access control
158 mcr p15, 0, ip, c13, c0, 1 @ set reserved context ID
160 mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID
161 mcr p15, 0, r5, c13, c0, 3 @ User r/o thread ID
165 mcr p15, 0, r6, c3, c0, 0 @ Domain ID
168 mcrr p15, 1, r5, r7, c2 @ TTB 1
172 mcr p15, 0, r1, c2, c0, 0 @ TTB 0
173 mcr p15, 0, r7, c2, c0, 1 @ TTB 1
175 mcr p15, 0, r11, c2, c0, 2 @ TTB control register
179 mcr p15, 0, r5, c10, c2, 1 @ write NMRR
181 mrc p15, 0, r4, c1, c0, 1 @ Read Auxiliary control register
183 mcrne p15, 0, r9, c1, c0, 1 @ No, so write it
184 mcr p15, 0, r10, c1, c0, 2 @ Co-processor access control
197 mrc p15, 0, r4, c15, c0, 1 @ Diagnostic register
198 mrc p15, 0, r5, c15, c0, 0 @ Power register
206 mrc p15, 0, r10, c15, c0, 1 @ Read Diagnostic register
208 mcrne p15, 0, r4, c15, c0, 1 @ No, so restore it
209 mrc p15, 0, r10, c15, c0, 0 @ Read Power register
211 mcrne p15, 0, r5, c15, c0, 0 @ No, so restore it
236 mrc p15, 1, r6, c15, c1, 0 @ save CP15 - extra features
237 mrc p15, 1, r7, c15, c2, 0 @ save CP15 - Aux Func Modes Ctrl 0
238 mrc p15, 1, r8, c15, c1, 2 @ save CP15 - Aux Debug Modes Ctrl 2
239 mrc p15, 1, r9, c15, c1, 1 @ save CP15 - Aux Debug Modes Ctrl 1
248 mcr p15, 1, r6, c15, c1, 0 @ restore CP15 - extra features
249 mcr p15, 1, r7, c15, c2, 0 @ restore CP15 - Aux Func Modes Ctrl 0
250 mcr p15, 1, r8, c15, c1, 2 @ restore CP15 - Aux Debug Modes Ctrl 2
251 mcr p15, 1, r9, c15, c1, 1 @ restore CP15 - Aux Debug Modes Ctrl 1
297 mov r10, #(1 << 0) @ Cache/TLB ops broadcasting
298 b 1f
306 1:
308 orr r10, r10, #(1 << 6) @ Enable SMP/nAMP mode
309 ALT_SMP(mrc p15, 0, r0, c1, c0, 1)
313 mcrne p15, 0, r10, c1, c0, 1 @ No, update register
328 mrceq p15, 0, r0, c1, c0, 1 @ read aux control register
329 orreq r0, r0, #(1 << 6) @ set IBE to 1
330 mcreq p15, 0, r0, c1, c0, 1 @ write aux control register
334 mrceq p15, 0, r0, c1, c0, 1 @ read aux control register
335 orreq r0, r0, #(1 << 5) @ set L1NEON to 1
336 orreq r0, r0, #(1 << 9) @ set PLDNOP to 1
337 mcreq p15, 0, r0, c1, c0, 1 @ write aux control register
341 mrceq p15, 1, r0, c9, c0, 2 @ read L2 cache aux ctrl register
342 tsteq r0, #1 << 22
343 orreq r0, r0, #(1 << 22) @ set the Write Allocate disable bit
344 mcreq p15, 1, r0, c9, c0, 2 @ write the L2 cache aux ctrl register
351 mrcle p15, 0, r0, c15, c0, 1 @ read diagnostic register
352 orrle r0, r0, #1 << 4 @ set bit #4
353 mcrle p15, 0, r0, c15, c0, 1 @ write diagnostic register
359 mrceq p15, 0, r0, c15, c0, 1 @ read diagnostic register
360 orreq r0, r0, #1 << 12 @ set bit #12
361 orreq r0, r0, #1 << 22 @ set bit #22
362 mcreq p15, 0, r0, c15, c0, 1 @ write diagnostic register
366 mrceq p15, 0, r0, c15, c0, 1 @ read diagnostic register
367 orreq r0, r0, #1 << 6 @ set bit #6
368 mcreq p15, 0, r0, c15, c0, 1 @ write diagnostic register
372 ALT_UP_B(1f)
373 mrclt p15, 0, r0, c15, c0, 1 @ read diagnostic register
374 orrlt r0, r0, #1 << 11 @ set bit #11
375 mcrlt p15, 0, r0, c15, c0, 1 @ write diagnostic register
376 1:
383 mrcle p15, 0, r0, c1, c0, 1 @ read aux control register
384 orrle r0, r0, #1 << 1 @ disable loop buffer
385 mcrle p15, 0, r0, c1, c0, 1 @ write aux control register
391 mrc p15, 0, r10, c15, c0, 1 @ read diagnostic register
392 orr r10, r10, #1 << 12 @ set bit #12
393 mcr p15, 0, r10, c15, c0, 1 @ write diagnostic register
396 mrc p15, 0, r10, c15, c0, 2 @ read internal feature reg
397 orr r10, r10, #1 << 1 @ set bit #1
398 mcr p15, 0, r10, c15, c0, 2 @ write internal feature reg
401 mrc p15, 0, r10, c15, c0, 1 @ read diagnostic register
402 orr r10, r10, #1 << 24 @ set bit #24
403 mcr p15, 0, r10, c15, c0, 1 @ write diagnostic register
406 mrc p15, 0, r10, c15, c0, 1 @ read diagnostic register
408 mcr p15, 0, r10, c15, c0, 1 @ write diagnostic register
415 mrcle p15, 0, r10, c15, c0, 1 @ read diagnostic register
416 orrle r10, r10, #1 << 24 @ set bit #24
417 mcrle p15, 0, r10, c15, c0, 1 @ write diagnostic register
421 mrcle p15, 0, r10, c15, c0, 1 @ read diagnostic register
422 orrle r10, r10, #1 << 12 @ set bit #12
423 mcrle p15, 0, r10, c15, c0, 1 @ write diagnostic register
426 mrc p15, 0, r10, c15, c0, 1 @ read diagnostic register
428 mcr p15, 0, r10, c15, c0, 1 @ write diagnostic register
435 /* Auxiliary Debug Modes Control 1 Register */
436 #define PJ4B_STATIC_BP (1 << 2) /* Enable Static BP */
437 #define PJ4B_INTER_PARITY (1 << 8) /* Disable Internal Parity Handling */
438 #define PJ4B_CLEAN_LINE (1 << 16) /* Disable data transfer for clean line */
441 #define PJ4B_FAST_LDR (1 << 23) /* Disable fast LDR */
442 #define PJ4B_SNOOP_DATA (1 << 25) /* Do not interleave write and snoop data */
443 #define PJ4B_CWF (1 << 27) /* Disable Critical Word First feature */
444 #define PJ4B_OUTSDNG_NC (1 << 29) /* Disable outstanding non cacheable rqst */
445 #define PJ4B_L1_REP_RR (1 << 30) /* L1 replacement - Strict round robin */
450 #define PJ4B_SMP_CFB (1 << 1) /* Set SMP mode. Join the coherency fabric */
451 #define PJ4B_L1_PAR_CHK (1 << 2) /* Support L1 parity checking */
452 #define PJ4B_BROADCAST_CACHE (1 << 8) /* Broadcast Cache and TLB maintenance */
455 #define PJ4B_WFI_WFE (1 << 22) /* WFI/WFE - serve the DVM and back to idle */
457 /* Auxiliary Debug Modes Control 1 Register */
458 mrc p15, 1, r0, c15, c1, 1
462 mcr p15, 1, r0, c15, c1, 1
465 mrc p15, 1, r0, c15, c1, 2
468 mcr p15, 1, r0, c15, c1, 2
471 mrc p15, 1, r0, c15, c2, 0
477 mcr p15, 1, r0, c15, c2, 0
480 mrc p15, 1, r0, c15, c1, 0
482 mcr p15, 1, r0, c15, c1, 0
532 mcr p15, 0, r6, c10, c2, 1 @ write NMRR
536 mrc p15, 0, r0, c0, c1, 0 @ read ID_PFR0 for ThumbEE
538 teq r0, #(1 << 12) @ check if ThumbEE is present
539 bne 1f
541 mcr p14, 6, r3, c1, c0, 0 @ Initialize TEEHBR to 0
542 mrc p14, 6, r0, c0, c0, 0 @ load TEECR
543 orr r0, r0, #1 @ set the 1st bit in order to
544 mcr p14, 6, r0, c0, c0, 0 @ stop userspace TEEHBR access
545 1:
549 ARM_BE8(orr r6, r6, #1 << 25) @ big-endian page tables
551 orr r3, r3, #(1 << 10) @ set SW bit in "clear"
552 bic r6, r6, #(1 << 10) @ clear it in "mmuset"
554 mrc p15, 0, r0, c1, c0, 0 @ read control register
557 THUMB( orr r0, r0, #1 << 30 ) @ Thumb exceptions
566 …define_processor_functions v7, dabort=v7_early_abort, pabort=v7_pabort, suspend=1, bugs=cpu_v7_bug…
581 …define_processor_functions v7_bpiall, dabort=v7_early_abort, pabort=v7_pabort, suspend=1, bugs=cpu…
602 …define_processor_functions ca8, dabort=v7_early_abort, pabort=v7_pabort, suspend=1, bugs=cpu_v7_ca…
617 …define_processor_functions ca9mp, dabort=v7_early_abort, pabort=v7_pabort, suspend=1, bugs=cpu_v7_…
635 …define_processor_functions ca15, dabort=v7_early_abort, pabort=v7_pabort, suspend=1, bugs=cpu_v7_c…
637 define_processor_functions pj4b, dabort=v7_early_abort, pabort=v7_pabort, suspend=1