Lines Matching full:macro
37 .macro disable_daif
41 .macro enable_daif
48 .macro save_and_disable_daif, flags
53 .macro save_and_disable_irq, flags
58 .macro restore_irq, flags
62 .macro enable_dbg
66 .macro disable_step_tsk, flgs, tmp
76 .macro enable_step_tsk, flgs, tmp
87 .macro esb
98 .macro csdb
105 .macro clearbhb
112 .macro sb
125 .macro nops, num
139 .macro ventry label
163 * Define a macro that constructs a 64-bit value by concatenating two
168 .macro regs_to_64, rd, lbits, hbits
170 .macro regs_to_64, rd, hbits, lbits
183 .macro adr_l, dst, sym
195 .macro ldr_l, dst, sym, tmp=
211 .macro str_l, src, sym, tmp
220 .macro get_this_cpu_offset, dst
224 .macro get_this_cpu_offset, dst
232 .macro set_this_cpu_offset, src
246 .macro adr_this_cpu, dst, sym, tmp
258 .macro ldr_this_cpu dst, sym, tmp
267 .macro vma_vm_mm, rd, rn
275 .macro read_ctr, reg
301 .macro raw_dcache_line_size, reg, tmp
311 .macro dcache_line_size, reg, tmp
322 .macro raw_icache_line_size, reg, tmp
332 .macro icache_line_size, reg, tmp
342 .macro tcr_set_t0sz, valreg, t0sz
349 .macro tcr_set_t1sz, valreg, t1sz
361 .macro idmap_get_t0sz, reg
375 .macro tcr_compute_pa_size, tcr, pos, tmp0, tmp1
385 .macro __dcache_op_workaround_clean_cache, op, addr
394 * Macro to perform a data cache maintenance for the interval
405 .macro dcache_by_myline_op op, domain, start, end, linesz, tmp, fixup
435 * Macro to perform a data cache maintenance for the interval
445 .macro dcache_by_line_op op, domain, start, end, tmp1, tmp2, fixup
451 * Macro to perform an instruction cache maintenance for the interval
458 .macro invalidate_icache_by_line start, end, tmp1, tmp2, fixup
478 .macro load_ttbr1, pgtbl, tmp1, tmp2
492 .macro break_before_make_ttbr_switch zero_page, page_table, tmp, tmp2
504 .macro reset_pmuserenr_el0, tmpreg
516 .macro reset_amuserenr_el0, tmpreg
526 .macro copy_page dest:req src:req t1:req t2:req t3:req t4:req t5:req t6:req t7:req t8:req
565 .macro le64sym, sym
575 .macro mov_q, reg, val
593 .macro get_current_task, rd
603 .macro offset_ttbr1, ttbr, tmp
620 .macro phys_to_ttbr, ttbr, phys
629 .macro phys_to_pte, pte, phys
642 .macro pte_to_phys, phys, pte
653 .macro tcr_clear_errata_bits, tcr, tmp1, tmp2
673 .macro pre_disable_mmu_workaround
685 .macro frame_push, regcount:req, extra
695 .macro frame_pop
699 .macro __frame_regs, reg1, reg2, op, num
707 .macro __frame, op, regcount, extra=0
746 .macro set_sctlr, sreg, reg
759 .macro set_sctlr_el1, reg
763 .macro set_sctlr_el2, reg
776 .macro cond_yield, lbl:req, tmp:req, tmp2:req
799 .macro bti, targets
807 * This macro emits a program property note section identifying
825 .macro emit_aarch64_feature_1_and, feat=GNU_PROPERTY_AARCH64_FEATURE_1_DEFAULT
851 .macro emit_aarch64_feature_1_and, feat=0
856 .macro __mitigate_spectre_bhb_loop tmp
869 .macro mitigate_spectre_bhb_loop tmp
880 .macro __mitigate_spectre_bhb_fw
893 .macro mitigate_spectre_bhb_clear_insn