Lines Matching +full:5 +full:- +full:8
1 /* SPDX-License-Identifier: GPL-2.0-only */
14 #include <linux/kasan-tags.h>
16 #include <asm/gpr-num.h>
22 * [20-19] : Op0
23 * [18-16] : Op1
24 * [15-12] : CRn
25 * [11-8] : CRm
26 * [7-5] : Op2
34 #define CRm_shift 8
36 #define Op2_shift 5
68 (((x) << 8) & 0x00ff0000) | \
69 (((x) >> 8) & 0x0000ff00) | \
83 * As per Arm ARM for v8-A, Section "C.5.1.3 op0 == 0b00, architectural hints,
128 #define SYS_IC_IALLU sys_insn(1, 0, 7, 5, 0)
129 #define SYS_IC_IVAU sys_insn(1, 3, 7, 5, 1)
133 #define SYS_DC_IGDVAC sys_insn(1, 0, 7, 6, 5)
137 #define SYS_DC_CGDVAC sys_insn(1, 3, 7, 10, 5)
143 #define SYS_DC_CGDVAP sys_insn(1, 3, 7, 12, 5)
147 #define SYS_DC_CGDVADP sys_insn(1, 3, 7, 13, 5)
151 #define SYS_DC_CIGDVAC sys_insn(1, 3, 7, 14, 5)
164 #include "asm/sysreg-defs.h"
175 #define SYS_DBGBCRn_EL1(n) sys_reg(2, 0, 0, n, 5)
188 #define SYS_DBGCLAIMSET_EL1 sys_reg(2, 0, 7, 8, 6)
193 #define SYS_DBGDTRRX_EL0 sys_reg(2, 3, 0, 5, 0)
194 #define SYS_DBGDTRTX_EL0 sys_reg(2, 3, 0, 5, 0)
197 #define SYS_BRBINF_EL1(n) sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) | 0))
199 #define SYS_BRBSRC_EL1(n) sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) | 1))
201 #define SYS_BRBTGT_EL1(n) sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) | 2))
220 #define SYS_TRCCLAIMSET sys_reg(2, 1, 7, 8, 6)
221 #define SYS_TRCCNTCTLR(m) sys_reg(2, 1, 0, (4 | (m & 3)), 5)
222 #define SYS_TRCCNTRLDVR(m) sys_reg(2, 1, 0, (0 | (m & 3)), 5)
223 #define SYS_TRCCNTVR(m) sys_reg(2, 1, 0, (8 | (m & 3)), 5)
227 #define SYS_TRCEVENTCTL0R sys_reg(2, 1, 0, 8, 0)
229 #define SYS_TRCEXTINSELR(m) sys_reg(2, 1, 0, (8 | (m & 3)), 4)
230 #define SYS_TRCIDR0 sys_reg(2, 1, 0, 8, 7)
234 #define SYS_TRCIDR13 sys_reg(2, 1, 0, 5, 6)
255 #define SYS_TRCSSCSR(m) sys_reg(2, 1, 1, (8 | (m & 7)), 2)
274 #define SYS_MPIDR_EL1 sys_reg(3, 0, 0, 0, 5)
278 #define SYS_RGSR_EL1 sys_reg(3, 0, 1, 0, 5)
303 #define SYS_AFSR0_EL1 sys_reg(3, 0, 5, 1, 0)
304 #define SYS_AFSR1_EL1 sys_reg(3, 0, 5, 1, 1)
305 #define SYS_ESR_EL1 sys_reg(3, 0, 5, 2, 0)
307 #define SYS_ERRIDR_EL1 sys_reg(3, 0, 5, 3, 0)
308 #define SYS_ERRSELR_EL1 sys_reg(3, 0, 5, 3, 1)
309 #define SYS_ERXFR_EL1 sys_reg(3, 0, 5, 4, 0)
310 #define SYS_ERXCTLR_EL1 sys_reg(3, 0, 5, 4, 1)
311 #define SYS_ERXSTATUS_EL1 sys_reg(3, 0, 5, 4, 2)
312 #define SYS_ERXADDR_EL1 sys_reg(3, 0, 5, 4, 3)
313 #define SYS_ERXPFGF_EL1 sys_reg(3, 0, 5, 4, 4)
314 #define SYS_ERXPFGCTL_EL1 sys_reg(3, 0, 5, 4, 5)
315 #define SYS_ERXPFGCDN_EL1 sys_reg(3, 0, 5, 4, 6)
316 #define SYS_ERXMISC0_EL1 sys_reg(3, 0, 5, 5, 0)
317 #define SYS_ERXMISC1_EL1 sys_reg(3, 0, 5, 5, 1)
318 #define SYS_ERXMISC2_EL1 sys_reg(3, 0, 5, 5, 2)
319 #define SYS_ERXMISC3_EL1 sys_reg(3, 0, 5, 5, 3)
320 #define SYS_TFSR_EL1 sys_reg(3, 0, 5, 6, 0)
321 #define SYS_TFSRE0_EL1 sys_reg(3, 0, 5, 6, 1)
330 (GENMASK_ULL(47, 32) | GENMASK_ULL(23, 16) | GENMASK_ULL(11, 8) |\
348 #define TRBSR_EL1_BSC_MASK GENMASK(5, 0)
362 #define SYS_ICC_IAR0_EL1 sys_reg(3, 0, 12, 8, 0)
363 #define SYS_ICC_EOIR0_EL1 sys_reg(3, 0, 12, 8, 1)
364 #define SYS_ICC_HPPIR0_EL1 sys_reg(3, 0, 12, 8, 2)
365 #define SYS_ICC_BPR0_EL1 sys_reg(3, 0, 12, 8, 3)
366 #define SYS_ICC_AP0Rn_EL1(n) sys_reg(3, 0, 12, 8, 4 | n)
378 #define SYS_ICC_SGI1R_EL1 sys_reg(3, 0, 12, 11, 5)
386 #define SYS_ICC_SRE_EL1 sys_reg(3, 0, 12, 12, 5)
390 #define SYS_ACCDATA_EL1 sys_reg(3, 0, 13, 0, 5)
404 #define SYS_PMSELR_EL0 sys_reg(3, 3, 9, 12, 5)
415 #define SYS_TPIDR2_EL0 sys_reg(3, 3, 13, 0, 5)
426 #define SYS_AMCNTENSET0_EL0 SYS_AM_EL0(2, 5)
435 * n: 0-15
441 * n: 0-15
458 #define SYS_CNTPCTSS_EL0 sys_reg(3, 3, 14, 0, 5)
472 #define SYS_AARCH32_CNTPCTSS sys_reg(0, 8, 0, 14, 0)
483 #define SYS_VMPIDR_EL2 sys_reg(3, 4, 0, 0, 5)
504 #define SYS_IFSR32_EL2 sys_reg(3, 4, 5, 0, 1)
505 #define SYS_AFSR0_EL2 sys_reg(3, 4, 5, 1, 0)
506 #define SYS_AFSR1_EL2 sys_reg(3, 4, 5, 1, 1)
507 #define SYS_ESR_EL2 sys_reg(3, 4, 5, 2, 0)
508 #define SYS_VSESR_EL2 sys_reg(3, 4, 5, 2, 3)
509 #define SYS_FPEXC32_EL2 sys_reg(3, 4, 5, 3, 0)
510 #define SYS_TFSR_EL2 sys_reg(3, 4, 5, 6, 0)
522 #define __SYS__AP0Rx_EL2(x) sys_reg(3, 4, 12, 8, x)
535 #define SYS_ICC_SRE_EL2 sys_reg(3, 4, 12, 9, 5)
540 #define SYS_ICH_ELRSR_EL2 sys_reg(3, 4, 12, 11, 5)
549 #define SYS_ICH_LR5_EL2 __SYS__LR0_EL2(5)
559 #define SYS_ICH_LR13_EL2 __SYS__LR8_EL2(5)
570 #define SYS_SCTLR_EL12 sys_reg(3, 5, 1, 0, 0)
571 #define SYS_TTBR0_EL12 sys_reg(3, 5, 2, 0, 0)
572 #define SYS_TTBR1_EL12 sys_reg(3, 5, 2, 0, 1)
573 #define SYS_TCR_EL12 sys_reg(3, 5, 2, 0, 2)
574 #define SYS_SPSR_EL12 sys_reg(3, 5, 4, 0, 0)
575 #define SYS_ELR_EL12 sys_reg(3, 5, 4, 0, 1)
576 #define SYS_AFSR0_EL12 sys_reg(3, 5, 5, 1, 0)
577 #define SYS_AFSR1_EL12 sys_reg(3, 5, 5, 1, 1)
578 #define SYS_ESR_EL12 sys_reg(3, 5, 5, 2, 0)
579 #define SYS_TFSR_EL12 sys_reg(3, 5, 5, 6, 0)
580 #define SYS_MAIR_EL12 sys_reg(3, 5, 10, 2, 0)
581 #define SYS_AMAIR_EL12 sys_reg(3, 5, 10, 3, 0)
582 #define SYS_VBAR_EL12 sys_reg(3, 5, 12, 0, 0)
583 #define SYS_CNTKCTL_EL12 sys_reg(3, 5, 14, 1, 0)
584 #define SYS_CNTP_TVAL_EL02 sys_reg(3, 5, 14, 2, 0)
585 #define SYS_CNTP_CTL_EL02 sys_reg(3, 5, 14, 2, 1)
586 #define SYS_CNTP_CVAL_EL02 sys_reg(3, 5, 14, 2, 2)
587 #define SYS_CNTV_TVAL_EL02 sys_reg(3, 5, 14, 3, 0)
588 #define SYS_CNTV_CTL_EL02 sys_reg(3, 5, 14, 3, 1)
589 #define SYS_CNTV_CVAL_EL02 sys_reg(3, 5, 14, 3, 2)
597 #define OP_AT_S1E1R sys_insn(AT_Op0, 0, AT_CRn, 8, 0)
598 #define OP_AT_S1E1W sys_insn(AT_Op0, 0, AT_CRn, 8, 1)
599 #define OP_AT_S1E0R sys_insn(AT_Op0, 0, AT_CRn, 8, 2)
600 #define OP_AT_S1E0W sys_insn(AT_Op0, 0, AT_CRn, 8, 3)
603 #define OP_AT_S1E2R sys_insn(AT_Op0, 4, AT_CRn, 8, 0)
604 #define OP_AT_S1E2W sys_insn(AT_Op0, 4, AT_CRn, 8, 1)
605 #define OP_AT_S12E1R sys_insn(AT_Op0, 4, AT_CRn, 8, 4)
606 #define OP_AT_S12E1W sys_insn(AT_Op0, 4, AT_CRn, 8, 5)
607 #define OP_AT_S12E0R sys_insn(AT_Op0, 4, AT_CRn, 8, 6)
608 #define OP_AT_S12E0W sys_insn(AT_Op0, 4, AT_CRn, 8, 7)
611 #define OP_TLBI_VMALLE1OS sys_insn(1, 0, 8, 1, 0)
612 #define OP_TLBI_VAE1OS sys_insn(1, 0, 8, 1, 1)
613 #define OP_TLBI_ASIDE1OS sys_insn(1, 0, 8, 1, 2)
614 #define OP_TLBI_VAAE1OS sys_insn(1, 0, 8, 1, 3)
615 #define OP_TLBI_VALE1OS sys_insn(1, 0, 8, 1, 5)
616 #define OP_TLBI_VAALE1OS sys_insn(1, 0, 8, 1, 7)
617 #define OP_TLBI_RVAE1IS sys_insn(1, 0, 8, 2, 1)
618 #define OP_TLBI_RVAAE1IS sys_insn(1, 0, 8, 2, 3)
619 #define OP_TLBI_RVALE1IS sys_insn(1, 0, 8, 2, 5)
620 #define OP_TLBI_RVAALE1IS sys_insn(1, 0, 8, 2, 7)
621 #define OP_TLBI_VMALLE1IS sys_insn(1, 0, 8, 3, 0)
622 #define OP_TLBI_VAE1IS sys_insn(1, 0, 8, 3, 1)
623 #define OP_TLBI_ASIDE1IS sys_insn(1, 0, 8, 3, 2)
624 #define OP_TLBI_VAAE1IS sys_insn(1, 0, 8, 3, 3)
625 #define OP_TLBI_VALE1IS sys_insn(1, 0, 8, 3, 5)
626 #define OP_TLBI_VAALE1IS sys_insn(1, 0, 8, 3, 7)
627 #define OP_TLBI_RVAE1OS sys_insn(1, 0, 8, 5, 1)
628 #define OP_TLBI_RVAAE1OS sys_insn(1, 0, 8, 5, 3)
629 #define OP_TLBI_RVALE1OS sys_insn(1, 0, 8, 5, 5)
630 #define OP_TLBI_RVAALE1OS sys_insn(1, 0, 8, 5, 7)
631 #define OP_TLBI_RVAE1 sys_insn(1, 0, 8, 6, 1)
632 #define OP_TLBI_RVAAE1 sys_insn(1, 0, 8, 6, 3)
633 #define OP_TLBI_RVALE1 sys_insn(1, 0, 8, 6, 5)
634 #define OP_TLBI_RVAALE1 sys_insn(1, 0, 8, 6, 7)
635 #define OP_TLBI_VMALLE1 sys_insn(1, 0, 8, 7, 0)
636 #define OP_TLBI_VAE1 sys_insn(1, 0, 8, 7, 1)
637 #define OP_TLBI_ASIDE1 sys_insn(1, 0, 8, 7, 2)
638 #define OP_TLBI_VAAE1 sys_insn(1, 0, 8, 7, 3)
639 #define OP_TLBI_VALE1 sys_insn(1, 0, 8, 7, 5)
640 #define OP_TLBI_VAALE1 sys_insn(1, 0, 8, 7, 7)
645 #define OP_TLBI_VALE1OSNXS sys_insn(1, 0, 9, 1, 5)
649 #define OP_TLBI_RVALE1ISNXS sys_insn(1, 0, 9, 2, 5)
655 #define OP_TLBI_VALE1ISNXS sys_insn(1, 0, 9, 3, 5)
657 #define OP_TLBI_RVAE1OSNXS sys_insn(1, 0, 9, 5, 1)
658 #define OP_TLBI_RVAAE1OSNXS sys_insn(1, 0, 9, 5, 3)
659 #define OP_TLBI_RVALE1OSNXS sys_insn(1, 0, 9, 5, 5)
660 #define OP_TLBI_RVAALE1OSNXS sys_insn(1, 0, 9, 5, 7)
663 #define OP_TLBI_RVALE1NXS sys_insn(1, 0, 9, 6, 5)
669 #define OP_TLBI_VALE1NXS sys_insn(1, 0, 9, 7, 5)
671 #define OP_TLBI_IPAS2E1IS sys_insn(1, 4, 8, 0, 1)
672 #define OP_TLBI_RIPAS2E1IS sys_insn(1, 4, 8, 0, 2)
673 #define OP_TLBI_IPAS2LE1IS sys_insn(1, 4, 8, 0, 5)
674 #define OP_TLBI_RIPAS2LE1IS sys_insn(1, 4, 8, 0, 6)
675 #define OP_TLBI_ALLE2OS sys_insn(1, 4, 8, 1, 0)
676 #define OP_TLBI_VAE2OS sys_insn(1, 4, 8, 1, 1)
677 #define OP_TLBI_ALLE1OS sys_insn(1, 4, 8, 1, 4)
678 #define OP_TLBI_VALE2OS sys_insn(1, 4, 8, 1, 5)
679 #define OP_TLBI_VMALLS12E1OS sys_insn(1, 4, 8, 1, 6)
680 #define OP_TLBI_RVAE2IS sys_insn(1, 4, 8, 2, 1)
681 #define OP_TLBI_RVALE2IS sys_insn(1, 4, 8, 2, 5)
682 #define OP_TLBI_ALLE2IS sys_insn(1, 4, 8, 3, 0)
683 #define OP_TLBI_VAE2IS sys_insn(1, 4, 8, 3, 1)
684 #define OP_TLBI_ALLE1IS sys_insn(1, 4, 8, 3, 4)
685 #define OP_TLBI_VALE2IS sys_insn(1, 4, 8, 3, 5)
686 #define OP_TLBI_VMALLS12E1IS sys_insn(1, 4, 8, 3, 6)
687 #define OP_TLBI_IPAS2E1OS sys_insn(1, 4, 8, 4, 0)
688 #define OP_TLBI_IPAS2E1 sys_insn(1, 4, 8, 4, 1)
689 #define OP_TLBI_RIPAS2E1 sys_insn(1, 4, 8, 4, 2)
690 #define OP_TLBI_RIPAS2E1OS sys_insn(1, 4, 8, 4, 3)
691 #define OP_TLBI_IPAS2LE1OS sys_insn(1, 4, 8, 4, 4)
692 #define OP_TLBI_IPAS2LE1 sys_insn(1, 4, 8, 4, 5)
693 #define OP_TLBI_RIPAS2LE1 sys_insn(1, 4, 8, 4, 6)
694 #define OP_TLBI_RIPAS2LE1OS sys_insn(1, 4, 8, 4, 7)
695 #define OP_TLBI_RVAE2OS sys_insn(1, 4, 8, 5, 1)
696 #define OP_TLBI_RVALE2OS sys_insn(1, 4, 8, 5, 5)
697 #define OP_TLBI_RVAE2 sys_insn(1, 4, 8, 6, 1)
698 #define OP_TLBI_RVALE2 sys_insn(1, 4, 8, 6, 5)
699 #define OP_TLBI_ALLE2 sys_insn(1, 4, 8, 7, 0)
700 #define OP_TLBI_VAE2 sys_insn(1, 4, 8, 7, 1)
701 #define OP_TLBI_ALLE1 sys_insn(1, 4, 8, 7, 4)
702 #define OP_TLBI_VALE2 sys_insn(1, 4, 8, 7, 5)
703 #define OP_TLBI_VMALLS12E1 sys_insn(1, 4, 8, 7, 6)
706 #define OP_TLBI_IPAS2LE1ISNXS sys_insn(1, 4, 9, 0, 5)
711 #define OP_TLBI_VALE2OSNXS sys_insn(1, 4, 9, 1, 5)
714 #define OP_TLBI_RVALE2ISNXS sys_insn(1, 4, 9, 2, 5)
718 #define OP_TLBI_VALE2ISNXS sys_insn(1, 4, 9, 3, 5)
725 #define OP_TLBI_IPAS2LE1NXS sys_insn(1, 4, 9, 4, 5)
728 #define OP_TLBI_RVAE2OSNXS sys_insn(1, 4, 9, 5, 1)
729 #define OP_TLBI_RVALE2OSNXS sys_insn(1, 4, 9, 5, 5)
731 #define OP_TLBI_RVALE2NXS sys_insn(1, 4, 9, 6, 5)
735 #define OP_TLBI_VALE2NXS sys_insn(1, 4, 9, 7, 5)
740 #define OP_BRB_INJ sys_insn(1, 1, 7, 2, 5)
742 #define OP_DVP_RCTX sys_insn(1, 3, 7, 3, 5)
773 #define SCTLR_EL2_RES1 ((BIT(4)) | (BIT(5)) | (BIT(11)) | (BIT(16)) | \
821 #define MAIR_ATTRIDX(attr, idx) ((attr) << ((idx) * 8))
881 * only uses tags in the range 0xF0-0xFF, which we map to MTE tags 0x0-0xF.
895 #define SYS_RGSR_EL1_SEED_SHIFT 8
907 #define TRFCR_ELx_TS_SHIFT 5
922 #define ICH_LR_VIRTUAL_ID_MASK ((1ULL << 32) - 1)
1090 * set mask are set. Other bits are left as-is.