Lines Matching +full:8 +full:- +full:9
1 /* SPDX-License-Identifier: GPL-2.0-only */
14 #include <linux/kasan-tags.h>
16 #include <asm/gpr-num.h>
22 * [20-19] : Op0
23 * [18-16] : Op1
24 * [15-12] : CRn
25 * [11-8] : CRm
26 * [7-5] : Op2
34 #define CRm_shift 8
68 (((x) << 8) & 0x00ff0000) | \
69 (((x) >> 8) & 0x0000ff00) | \
83 * As per Arm ARM for v8-A, Section "C.5.1.3 op0 == 0b00, architectural hints,
164 #include "asm/sysreg-defs.h"
188 #define SYS_DBGCLAIMSET_EL1 sys_reg(2, 0, 7, 8, 6)
189 #define SYS_DBGCLAIMCLR_EL1 sys_reg(2, 0, 7, 9, 6)
197 #define SYS_BRBINF_EL1(n) sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) | 0))
198 #define SYS_BRBINFINJ_EL1 sys_reg(2, 1, 9, 1, 0)
199 #define SYS_BRBSRC_EL1(n) sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) | 1))
200 #define SYS_BRBSRCINJ_EL1 sys_reg(2, 1, 9, 1, 1)
201 #define SYS_BRBTGT_EL1(n) sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) | 2))
202 #define SYS_BRBTGTINJ_EL1 sys_reg(2, 1, 9, 1, 2)
203 #define SYS_BRBTS_EL1 sys_reg(2, 1, 9, 0, 2)
205 #define SYS_BRBCR_EL1 sys_reg(2, 1, 9, 0, 0)
206 #define SYS_BRBFCR_EL1 sys_reg(2, 1, 9, 0, 1)
207 #define SYS_BRBIDR0_EL1 sys_reg(2, 1, 9, 2, 0)
219 #define SYS_TRCCLAIMCLR sys_reg(2, 1, 7, 9, 6)
220 #define SYS_TRCCLAIMSET sys_reg(2, 1, 7, 8, 6)
223 #define SYS_TRCCNTVR(m) sys_reg(2, 1, 0, (8 | (m & 3)), 5)
227 #define SYS_TRCEVENTCTL0R sys_reg(2, 1, 0, 8, 0)
228 #define SYS_TRCEVENTCTL1R sys_reg(2, 1, 0, 9, 0)
229 #define SYS_TRCEXTINSELR(m) sys_reg(2, 1, 0, (8 | (m & 3)), 4)
230 #define SYS_TRCIDR0 sys_reg(2, 1, 0, 8, 7)
235 #define SYS_TRCIDR1 sys_reg(2, 1, 0, 9, 7)
255 #define SYS_TRCSSCSR(m) sys_reg(2, 1, 1, (8 | (m & 7)), 2)
330 (GENMASK_ULL(47, 32) | GENMASK_ULL(23, 16) | GENMASK_ULL(11, 8) |\
351 #define SYS_PMINTENSET_EL1 sys_reg(3, 0, 9, 14, 1)
352 #define SYS_PMINTENCLR_EL1 sys_reg(3, 0, 9, 14, 2)
354 #define SYS_PMMIR_EL1 sys_reg(3, 0, 9, 14, 6)
362 #define SYS_ICC_IAR0_EL1 sys_reg(3, 0, 12, 8, 0)
363 #define SYS_ICC_EOIR0_EL1 sys_reg(3, 0, 12, 8, 1)
364 #define SYS_ICC_HPPIR0_EL1 sys_reg(3, 0, 12, 8, 2)
365 #define SYS_ICC_BPR0_EL1 sys_reg(3, 0, 12, 8, 3)
366 #define SYS_ICC_AP0Rn_EL1(n) sys_reg(3, 0, 12, 8, 4 | n)
371 #define SYS_ICC_AP1Rn_EL1(n) sys_reg(3, 0, 12, 9, n)
399 #define SYS_PMCR_EL0 sys_reg(3, 3, 9, 12, 0)
400 #define SYS_PMCNTENSET_EL0 sys_reg(3, 3, 9, 12, 1)
401 #define SYS_PMCNTENCLR_EL0 sys_reg(3, 3, 9, 12, 2)
402 #define SYS_PMOVSCLR_EL0 sys_reg(3, 3, 9, 12, 3)
403 #define SYS_PMSWINC_EL0 sys_reg(3, 3, 9, 12, 4)
404 #define SYS_PMSELR_EL0 sys_reg(3, 3, 9, 12, 5)
405 #define SYS_PMCEID0_EL0 sys_reg(3, 3, 9, 12, 6)
406 #define SYS_PMCEID1_EL0 sys_reg(3, 3, 9, 12, 7)
407 #define SYS_PMCCNTR_EL0 sys_reg(3, 3, 9, 13, 0)
408 #define SYS_PMXEVTYPER_EL0 sys_reg(3, 3, 9, 13, 1)
409 #define SYS_PMXEVCNTR_EL0 sys_reg(3, 3, 9, 13, 2)
410 #define SYS_PMUSERENR_EL0 sys_reg(3, 3, 9, 14, 0)
411 #define SYS_PMOVSSET_EL0 sys_reg(3, 3, 9, 14, 3)
435 * n: 0-15
441 * n: 0-15
472 #define SYS_AARCH32_CNTPCTSS sys_reg(0, 8, 0, 14, 0)
522 #define __SYS__AP0Rx_EL2(x) sys_reg(3, 4, 12, 8, x)
528 #define __SYS__AP1Rx_EL2(x) sys_reg(3, 4, 12, 9, x)
534 #define SYS_ICH_VSEIR_EL2 sys_reg(3, 4, 12, 9, 4)
535 #define SYS_ICC_SRE_EL2 sys_reg(3, 4, 12, 9, 5)
597 #define OP_AT_S1E1R sys_insn(AT_Op0, 0, AT_CRn, 8, 0)
598 #define OP_AT_S1E1W sys_insn(AT_Op0, 0, AT_CRn, 8, 1)
599 #define OP_AT_S1E0R sys_insn(AT_Op0, 0, AT_CRn, 8, 2)
600 #define OP_AT_S1E0W sys_insn(AT_Op0, 0, AT_CRn, 8, 3)
601 #define OP_AT_S1E1RP sys_insn(AT_Op0, 0, AT_CRn, 9, 0)
602 #define OP_AT_S1E1WP sys_insn(AT_Op0, 0, AT_CRn, 9, 1)
603 #define OP_AT_S1E2R sys_insn(AT_Op0, 4, AT_CRn, 8, 0)
604 #define OP_AT_S1E2W sys_insn(AT_Op0, 4, AT_CRn, 8, 1)
605 #define OP_AT_S12E1R sys_insn(AT_Op0, 4, AT_CRn, 8, 4)
606 #define OP_AT_S12E1W sys_insn(AT_Op0, 4, AT_CRn, 8, 5)
607 #define OP_AT_S12E0R sys_insn(AT_Op0, 4, AT_CRn, 8, 6)
608 #define OP_AT_S12E0W sys_insn(AT_Op0, 4, AT_CRn, 8, 7)
611 #define OP_TLBI_VMALLE1OS sys_insn(1, 0, 8, 1, 0)
612 #define OP_TLBI_VAE1OS sys_insn(1, 0, 8, 1, 1)
613 #define OP_TLBI_ASIDE1OS sys_insn(1, 0, 8, 1, 2)
614 #define OP_TLBI_VAAE1OS sys_insn(1, 0, 8, 1, 3)
615 #define OP_TLBI_VALE1OS sys_insn(1, 0, 8, 1, 5)
616 #define OP_TLBI_VAALE1OS sys_insn(1, 0, 8, 1, 7)
617 #define OP_TLBI_RVAE1IS sys_insn(1, 0, 8, 2, 1)
618 #define OP_TLBI_RVAAE1IS sys_insn(1, 0, 8, 2, 3)
619 #define OP_TLBI_RVALE1IS sys_insn(1, 0, 8, 2, 5)
620 #define OP_TLBI_RVAALE1IS sys_insn(1, 0, 8, 2, 7)
621 #define OP_TLBI_VMALLE1IS sys_insn(1, 0, 8, 3, 0)
622 #define OP_TLBI_VAE1IS sys_insn(1, 0, 8, 3, 1)
623 #define OP_TLBI_ASIDE1IS sys_insn(1, 0, 8, 3, 2)
624 #define OP_TLBI_VAAE1IS sys_insn(1, 0, 8, 3, 3)
625 #define OP_TLBI_VALE1IS sys_insn(1, 0, 8, 3, 5)
626 #define OP_TLBI_VAALE1IS sys_insn(1, 0, 8, 3, 7)
627 #define OP_TLBI_RVAE1OS sys_insn(1, 0, 8, 5, 1)
628 #define OP_TLBI_RVAAE1OS sys_insn(1, 0, 8, 5, 3)
629 #define OP_TLBI_RVALE1OS sys_insn(1, 0, 8, 5, 5)
630 #define OP_TLBI_RVAALE1OS sys_insn(1, 0, 8, 5, 7)
631 #define OP_TLBI_RVAE1 sys_insn(1, 0, 8, 6, 1)
632 #define OP_TLBI_RVAAE1 sys_insn(1, 0, 8, 6, 3)
633 #define OP_TLBI_RVALE1 sys_insn(1, 0, 8, 6, 5)
634 #define OP_TLBI_RVAALE1 sys_insn(1, 0, 8, 6, 7)
635 #define OP_TLBI_VMALLE1 sys_insn(1, 0, 8, 7, 0)
636 #define OP_TLBI_VAE1 sys_insn(1, 0, 8, 7, 1)
637 #define OP_TLBI_ASIDE1 sys_insn(1, 0, 8, 7, 2)
638 #define OP_TLBI_VAAE1 sys_insn(1, 0, 8, 7, 3)
639 #define OP_TLBI_VALE1 sys_insn(1, 0, 8, 7, 5)
640 #define OP_TLBI_VAALE1 sys_insn(1, 0, 8, 7, 7)
641 #define OP_TLBI_VMALLE1OSNXS sys_insn(1, 0, 9, 1, 0)
642 #define OP_TLBI_VAE1OSNXS sys_insn(1, 0, 9, 1, 1)
643 #define OP_TLBI_ASIDE1OSNXS sys_insn(1, 0, 9, 1, 2)
644 #define OP_TLBI_VAAE1OSNXS sys_insn(1, 0, 9, 1, 3)
645 #define OP_TLBI_VALE1OSNXS sys_insn(1, 0, 9, 1, 5)
646 #define OP_TLBI_VAALE1OSNXS sys_insn(1, 0, 9, 1, 7)
647 #define OP_TLBI_RVAE1ISNXS sys_insn(1, 0, 9, 2, 1)
648 #define OP_TLBI_RVAAE1ISNXS sys_insn(1, 0, 9, 2, 3)
649 #define OP_TLBI_RVALE1ISNXS sys_insn(1, 0, 9, 2, 5)
650 #define OP_TLBI_RVAALE1ISNXS sys_insn(1, 0, 9, 2, 7)
651 #define OP_TLBI_VMALLE1ISNXS sys_insn(1, 0, 9, 3, 0)
652 #define OP_TLBI_VAE1ISNXS sys_insn(1, 0, 9, 3, 1)
653 #define OP_TLBI_ASIDE1ISNXS sys_insn(1, 0, 9, 3, 2)
654 #define OP_TLBI_VAAE1ISNXS sys_insn(1, 0, 9, 3, 3)
655 #define OP_TLBI_VALE1ISNXS sys_insn(1, 0, 9, 3, 5)
656 #define OP_TLBI_VAALE1ISNXS sys_insn(1, 0, 9, 3, 7)
657 #define OP_TLBI_RVAE1OSNXS sys_insn(1, 0, 9, 5, 1)
658 #define OP_TLBI_RVAAE1OSNXS sys_insn(1, 0, 9, 5, 3)
659 #define OP_TLBI_RVALE1OSNXS sys_insn(1, 0, 9, 5, 5)
660 #define OP_TLBI_RVAALE1OSNXS sys_insn(1, 0, 9, 5, 7)
661 #define OP_TLBI_RVAE1NXS sys_insn(1, 0, 9, 6, 1)
662 #define OP_TLBI_RVAAE1NXS sys_insn(1, 0, 9, 6, 3)
663 #define OP_TLBI_RVALE1NXS sys_insn(1, 0, 9, 6, 5)
664 #define OP_TLBI_RVAALE1NXS sys_insn(1, 0, 9, 6, 7)
665 #define OP_TLBI_VMALLE1NXS sys_insn(1, 0, 9, 7, 0)
666 #define OP_TLBI_VAE1NXS sys_insn(1, 0, 9, 7, 1)
667 #define OP_TLBI_ASIDE1NXS sys_insn(1, 0, 9, 7, 2)
668 #define OP_TLBI_VAAE1NXS sys_insn(1, 0, 9, 7, 3)
669 #define OP_TLBI_VALE1NXS sys_insn(1, 0, 9, 7, 5)
670 #define OP_TLBI_VAALE1NXS sys_insn(1, 0, 9, 7, 7)
671 #define OP_TLBI_IPAS2E1IS sys_insn(1, 4, 8, 0, 1)
672 #define OP_TLBI_RIPAS2E1IS sys_insn(1, 4, 8, 0, 2)
673 #define OP_TLBI_IPAS2LE1IS sys_insn(1, 4, 8, 0, 5)
674 #define OP_TLBI_RIPAS2LE1IS sys_insn(1, 4, 8, 0, 6)
675 #define OP_TLBI_ALLE2OS sys_insn(1, 4, 8, 1, 0)
676 #define OP_TLBI_VAE2OS sys_insn(1, 4, 8, 1, 1)
677 #define OP_TLBI_ALLE1OS sys_insn(1, 4, 8, 1, 4)
678 #define OP_TLBI_VALE2OS sys_insn(1, 4, 8, 1, 5)
679 #define OP_TLBI_VMALLS12E1OS sys_insn(1, 4, 8, 1, 6)
680 #define OP_TLBI_RVAE2IS sys_insn(1, 4, 8, 2, 1)
681 #define OP_TLBI_RVALE2IS sys_insn(1, 4, 8, 2, 5)
682 #define OP_TLBI_ALLE2IS sys_insn(1, 4, 8, 3, 0)
683 #define OP_TLBI_VAE2IS sys_insn(1, 4, 8, 3, 1)
684 #define OP_TLBI_ALLE1IS sys_insn(1, 4, 8, 3, 4)
685 #define OP_TLBI_VALE2IS sys_insn(1, 4, 8, 3, 5)
686 #define OP_TLBI_VMALLS12E1IS sys_insn(1, 4, 8, 3, 6)
687 #define OP_TLBI_IPAS2E1OS sys_insn(1, 4, 8, 4, 0)
688 #define OP_TLBI_IPAS2E1 sys_insn(1, 4, 8, 4, 1)
689 #define OP_TLBI_RIPAS2E1 sys_insn(1, 4, 8, 4, 2)
690 #define OP_TLBI_RIPAS2E1OS sys_insn(1, 4, 8, 4, 3)
691 #define OP_TLBI_IPAS2LE1OS sys_insn(1, 4, 8, 4, 4)
692 #define OP_TLBI_IPAS2LE1 sys_insn(1, 4, 8, 4, 5)
693 #define OP_TLBI_RIPAS2LE1 sys_insn(1, 4, 8, 4, 6)
694 #define OP_TLBI_RIPAS2LE1OS sys_insn(1, 4, 8, 4, 7)
695 #define OP_TLBI_RVAE2OS sys_insn(1, 4, 8, 5, 1)
696 #define OP_TLBI_RVALE2OS sys_insn(1, 4, 8, 5, 5)
697 #define OP_TLBI_RVAE2 sys_insn(1, 4, 8, 6, 1)
698 #define OP_TLBI_RVALE2 sys_insn(1, 4, 8, 6, 5)
699 #define OP_TLBI_ALLE2 sys_insn(1, 4, 8, 7, 0)
700 #define OP_TLBI_VAE2 sys_insn(1, 4, 8, 7, 1)
701 #define OP_TLBI_ALLE1 sys_insn(1, 4, 8, 7, 4)
702 #define OP_TLBI_VALE2 sys_insn(1, 4, 8, 7, 5)
703 #define OP_TLBI_VMALLS12E1 sys_insn(1, 4, 8, 7, 6)
704 #define OP_TLBI_IPAS2E1ISNXS sys_insn(1, 4, 9, 0, 1)
705 #define OP_TLBI_RIPAS2E1ISNXS sys_insn(1, 4, 9, 0, 2)
706 #define OP_TLBI_IPAS2LE1ISNXS sys_insn(1, 4, 9, 0, 5)
707 #define OP_TLBI_RIPAS2LE1ISNXS sys_insn(1, 4, 9, 0, 6)
708 #define OP_TLBI_ALLE2OSNXS sys_insn(1, 4, 9, 1, 0)
709 #define OP_TLBI_VAE2OSNXS sys_insn(1, 4, 9, 1, 1)
710 #define OP_TLBI_ALLE1OSNXS sys_insn(1, 4, 9, 1, 4)
711 #define OP_TLBI_VALE2OSNXS sys_insn(1, 4, 9, 1, 5)
712 #define OP_TLBI_VMALLS12E1OSNXS sys_insn(1, 4, 9, 1, 6)
713 #define OP_TLBI_RVAE2ISNXS sys_insn(1, 4, 9, 2, 1)
714 #define OP_TLBI_RVALE2ISNXS sys_insn(1, 4, 9, 2, 5)
715 #define OP_TLBI_ALLE2ISNXS sys_insn(1, 4, 9, 3, 0)
716 #define OP_TLBI_VAE2ISNXS sys_insn(1, 4, 9, 3, 1)
717 #define OP_TLBI_ALLE1ISNXS sys_insn(1, 4, 9, 3, 4)
718 #define OP_TLBI_VALE2ISNXS sys_insn(1, 4, 9, 3, 5)
719 #define OP_TLBI_VMALLS12E1ISNXS sys_insn(1, 4, 9, 3, 6)
720 #define OP_TLBI_IPAS2E1OSNXS sys_insn(1, 4, 9, 4, 0)
721 #define OP_TLBI_IPAS2E1NXS sys_insn(1, 4, 9, 4, 1)
722 #define OP_TLBI_RIPAS2E1NXS sys_insn(1, 4, 9, 4, 2)
723 #define OP_TLBI_RIPAS2E1OSNXS sys_insn(1, 4, 9, 4, 3)
724 #define OP_TLBI_IPAS2LE1OSNXS sys_insn(1, 4, 9, 4, 4)
725 #define OP_TLBI_IPAS2LE1NXS sys_insn(1, 4, 9, 4, 5)
726 #define OP_TLBI_RIPAS2LE1NXS sys_insn(1, 4, 9, 4, 6)
727 #define OP_TLBI_RIPAS2LE1OSNXS sys_insn(1, 4, 9, 4, 7)
728 #define OP_TLBI_RVAE2OSNXS sys_insn(1, 4, 9, 5, 1)
729 #define OP_TLBI_RVALE2OSNXS sys_insn(1, 4, 9, 5, 5)
730 #define OP_TLBI_RVAE2NXS sys_insn(1, 4, 9, 6, 1)
731 #define OP_TLBI_RVALE2NXS sys_insn(1, 4, 9, 6, 5)
732 #define OP_TLBI_ALLE2NXS sys_insn(1, 4, 9, 7, 0)
733 #define OP_TLBI_VAE2NXS sys_insn(1, 4, 9, 7, 1)
734 #define OP_TLBI_ALLE1NXS sys_insn(1, 4, 9, 7, 4)
735 #define OP_TLBI_VALE2NXS sys_insn(1, 4, 9, 7, 5)
736 #define OP_TLBI_VMALLS12E1NXS sys_insn(1, 4, 9, 7, 6)
821 #define MAIR_ATTRIDX(attr, idx) ((attr) << ((idx) * 8))
881 * only uses tags in the range 0xF0-0xFF, which we map to MTE tags 0x0-0xF.
895 #define SYS_RGSR_EL1_SEED_SHIFT 8
922 #define ICH_LR_VIRTUAL_ID_MASK ((1ULL << 32) - 1)
953 #define ICH_VMCR_EOIM_SHIFT 9
1090 * set mask are set. Other bits are left as-is.