Lines Matching +full:9 +full:- +full:bit
1 /* SPDX-License-Identifier: GPL-2.0-only */
14 #include <linux/kasan-tags.h>
16 #include <asm/gpr-num.h>
22 * [20-19] : Op0
23 * [18-16] : Op1
24 * [15-12] : CRn
25 * [11-8] : CRm
26 * [7-5] : Op2
83 * As per Arm ARM for v8-A, Section "C.5.1.3 op0 == 0b00, architectural hints,
164 #include "asm/sysreg-defs.h"
181 #define OSLSR_EL1_OSLM_MASK (BIT(3) | BIT(0))
183 #define OSLSR_EL1_OSLM_IMPLEMENTED BIT(3)
184 #define OSLSR_EL1_OSLK BIT(1)
189 #define SYS_DBGCLAIMCLR_EL1 sys_reg(2, 0, 7, 9, 6)
198 #define SYS_BRBINFINJ_EL1 sys_reg(2, 1, 9, 1, 0)
200 #define SYS_BRBSRCINJ_EL1 sys_reg(2, 1, 9, 1, 1)
202 #define SYS_BRBTGTINJ_EL1 sys_reg(2, 1, 9, 1, 2)
203 #define SYS_BRBTS_EL1 sys_reg(2, 1, 9, 0, 2)
205 #define SYS_BRBCR_EL1 sys_reg(2, 1, 9, 0, 0)
206 #define SYS_BRBFCR_EL1 sys_reg(2, 1, 9, 0, 1)
207 #define SYS_BRBIDR0_EL1 sys_reg(2, 1, 9, 2, 0)
219 #define SYS_TRCCLAIMCLR sys_reg(2, 1, 7, 9, 6)
228 #define SYS_TRCEVENTCTL1R sys_reg(2, 1, 0, 9, 0)
235 #define SYS_TRCIDR1 sys_reg(2, 1, 0, 9, 7)
325 #define SYS_PAR_EL1_F BIT(0)
351 #define SYS_PMINTENSET_EL1 sys_reg(3, 0, 9, 14, 1)
352 #define SYS_PMINTENCLR_EL1 sys_reg(3, 0, 9, 14, 2)
354 #define SYS_PMMIR_EL1 sys_reg(3, 0, 9, 14, 6)
371 #define SYS_ICC_AP1Rn_EL1(n) sys_reg(3, 0, 12, 9, n)
399 #define SYS_PMCR_EL0 sys_reg(3, 3, 9, 12, 0)
400 #define SYS_PMCNTENSET_EL0 sys_reg(3, 3, 9, 12, 1)
401 #define SYS_PMCNTENCLR_EL0 sys_reg(3, 3, 9, 12, 2)
402 #define SYS_PMOVSCLR_EL0 sys_reg(3, 3, 9, 12, 3)
403 #define SYS_PMSWINC_EL0 sys_reg(3, 3, 9, 12, 4)
404 #define SYS_PMSELR_EL0 sys_reg(3, 3, 9, 12, 5)
405 #define SYS_PMCEID0_EL0 sys_reg(3, 3, 9, 12, 6)
406 #define SYS_PMCEID1_EL0 sys_reg(3, 3, 9, 12, 7)
407 #define SYS_PMCCNTR_EL0 sys_reg(3, 3, 9, 13, 0)
408 #define SYS_PMXEVTYPER_EL0 sys_reg(3, 3, 9, 13, 1)
409 #define SYS_PMXEVCNTR_EL0 sys_reg(3, 3, 9, 13, 2)
410 #define SYS_PMUSERENR_EL0 sys_reg(3, 3, 9, 14, 0)
411 #define SYS_PMOVSSET_EL0 sys_reg(3, 3, 9, 14, 3)
435 * n: 0-15
441 * n: 0-15
528 #define __SYS__AP1Rx_EL2(x) sys_reg(3, 4, 12, 9, x)
534 #define SYS_ICH_VSEIR_EL2 sys_reg(3, 4, 12, 9, 4)
535 #define SYS_ICC_SRE_EL2 sys_reg(3, 4, 12, 9, 5)
601 #define OP_AT_S1E1RP sys_insn(AT_Op0, 0, AT_CRn, 9, 0)
602 #define OP_AT_S1E1WP sys_insn(AT_Op0, 0, AT_CRn, 9, 1)
641 #define OP_TLBI_VMALLE1OSNXS sys_insn(1, 0, 9, 1, 0)
642 #define OP_TLBI_VAE1OSNXS sys_insn(1, 0, 9, 1, 1)
643 #define OP_TLBI_ASIDE1OSNXS sys_insn(1, 0, 9, 1, 2)
644 #define OP_TLBI_VAAE1OSNXS sys_insn(1, 0, 9, 1, 3)
645 #define OP_TLBI_VALE1OSNXS sys_insn(1, 0, 9, 1, 5)
646 #define OP_TLBI_VAALE1OSNXS sys_insn(1, 0, 9, 1, 7)
647 #define OP_TLBI_RVAE1ISNXS sys_insn(1, 0, 9, 2, 1)
648 #define OP_TLBI_RVAAE1ISNXS sys_insn(1, 0, 9, 2, 3)
649 #define OP_TLBI_RVALE1ISNXS sys_insn(1, 0, 9, 2, 5)
650 #define OP_TLBI_RVAALE1ISNXS sys_insn(1, 0, 9, 2, 7)
651 #define OP_TLBI_VMALLE1ISNXS sys_insn(1, 0, 9, 3, 0)
652 #define OP_TLBI_VAE1ISNXS sys_insn(1, 0, 9, 3, 1)
653 #define OP_TLBI_ASIDE1ISNXS sys_insn(1, 0, 9, 3, 2)
654 #define OP_TLBI_VAAE1ISNXS sys_insn(1, 0, 9, 3, 3)
655 #define OP_TLBI_VALE1ISNXS sys_insn(1, 0, 9, 3, 5)
656 #define OP_TLBI_VAALE1ISNXS sys_insn(1, 0, 9, 3, 7)
657 #define OP_TLBI_RVAE1OSNXS sys_insn(1, 0, 9, 5, 1)
658 #define OP_TLBI_RVAAE1OSNXS sys_insn(1, 0, 9, 5, 3)
659 #define OP_TLBI_RVALE1OSNXS sys_insn(1, 0, 9, 5, 5)
660 #define OP_TLBI_RVAALE1OSNXS sys_insn(1, 0, 9, 5, 7)
661 #define OP_TLBI_RVAE1NXS sys_insn(1, 0, 9, 6, 1)
662 #define OP_TLBI_RVAAE1NXS sys_insn(1, 0, 9, 6, 3)
663 #define OP_TLBI_RVALE1NXS sys_insn(1, 0, 9, 6, 5)
664 #define OP_TLBI_RVAALE1NXS sys_insn(1, 0, 9, 6, 7)
665 #define OP_TLBI_VMALLE1NXS sys_insn(1, 0, 9, 7, 0)
666 #define OP_TLBI_VAE1NXS sys_insn(1, 0, 9, 7, 1)
667 #define OP_TLBI_ASIDE1NXS sys_insn(1, 0, 9, 7, 2)
668 #define OP_TLBI_VAAE1NXS sys_insn(1, 0, 9, 7, 3)
669 #define OP_TLBI_VALE1NXS sys_insn(1, 0, 9, 7, 5)
670 #define OP_TLBI_VAALE1NXS sys_insn(1, 0, 9, 7, 7)
704 #define OP_TLBI_IPAS2E1ISNXS sys_insn(1, 4, 9, 0, 1)
705 #define OP_TLBI_RIPAS2E1ISNXS sys_insn(1, 4, 9, 0, 2)
706 #define OP_TLBI_IPAS2LE1ISNXS sys_insn(1, 4, 9, 0, 5)
707 #define OP_TLBI_RIPAS2LE1ISNXS sys_insn(1, 4, 9, 0, 6)
708 #define OP_TLBI_ALLE2OSNXS sys_insn(1, 4, 9, 1, 0)
709 #define OP_TLBI_VAE2OSNXS sys_insn(1, 4, 9, 1, 1)
710 #define OP_TLBI_ALLE1OSNXS sys_insn(1, 4, 9, 1, 4)
711 #define OP_TLBI_VALE2OSNXS sys_insn(1, 4, 9, 1, 5)
712 #define OP_TLBI_VMALLS12E1OSNXS sys_insn(1, 4, 9, 1, 6)
713 #define OP_TLBI_RVAE2ISNXS sys_insn(1, 4, 9, 2, 1)
714 #define OP_TLBI_RVALE2ISNXS sys_insn(1, 4, 9, 2, 5)
715 #define OP_TLBI_ALLE2ISNXS sys_insn(1, 4, 9, 3, 0)
716 #define OP_TLBI_VAE2ISNXS sys_insn(1, 4, 9, 3, 1)
717 #define OP_TLBI_ALLE1ISNXS sys_insn(1, 4, 9, 3, 4)
718 #define OP_TLBI_VALE2ISNXS sys_insn(1, 4, 9, 3, 5)
719 #define OP_TLBI_VMALLS12E1ISNXS sys_insn(1, 4, 9, 3, 6)
720 #define OP_TLBI_IPAS2E1OSNXS sys_insn(1, 4, 9, 4, 0)
721 #define OP_TLBI_IPAS2E1NXS sys_insn(1, 4, 9, 4, 1)
722 #define OP_TLBI_RIPAS2E1NXS sys_insn(1, 4, 9, 4, 2)
723 #define OP_TLBI_RIPAS2E1OSNXS sys_insn(1, 4, 9, 4, 3)
724 #define OP_TLBI_IPAS2LE1OSNXS sys_insn(1, 4, 9, 4, 4)
725 #define OP_TLBI_IPAS2LE1NXS sys_insn(1, 4, 9, 4, 5)
726 #define OP_TLBI_RIPAS2LE1NXS sys_insn(1, 4, 9, 4, 6)
727 #define OP_TLBI_RIPAS2LE1OSNXS sys_insn(1, 4, 9, 4, 7)
728 #define OP_TLBI_RVAE2OSNXS sys_insn(1, 4, 9, 5, 1)
729 #define OP_TLBI_RVALE2OSNXS sys_insn(1, 4, 9, 5, 5)
730 #define OP_TLBI_RVAE2NXS sys_insn(1, 4, 9, 6, 1)
731 #define OP_TLBI_RVALE2NXS sys_insn(1, 4, 9, 6, 5)
732 #define OP_TLBI_ALLE2NXS sys_insn(1, 4, 9, 7, 0)
733 #define OP_TLBI_VAE2NXS sys_insn(1, 4, 9, 7, 1)
734 #define OP_TLBI_ALLE1NXS sys_insn(1, 4, 9, 7, 4)
735 #define OP_TLBI_VALE2NXS sys_insn(1, 4, 9, 7, 5)
736 #define OP_TLBI_VMALLS12E1NXS sys_insn(1, 4, 9, 7, 6)
746 #define SCTLR_ELx_ENTP2 (BIT(60))
747 #define SCTLR_ELx_DSSBS (BIT(44))
748 #define SCTLR_ELx_ATA (BIT(43))
753 #define SCTLR_ELx_ITFSB (BIT(37))
754 #define SCTLR_ELx_ENIA (BIT(SCTLR_ELx_ENIA_SHIFT))
755 #define SCTLR_ELx_ENIB (BIT(30))
756 #define SCTLR_ELx_LSMAOE (BIT(29))
757 #define SCTLR_ELx_nTLSMD (BIT(28))
758 #define SCTLR_ELx_ENDA (BIT(27))
759 #define SCTLR_ELx_EE (BIT(SCTLR_ELx_EE_SHIFT))
760 #define SCTLR_ELx_EIS (BIT(22))
761 #define SCTLR_ELx_IESB (BIT(21))
762 #define SCTLR_ELx_TSCXT (BIT(20))
763 #define SCTLR_ELx_WXN (BIT(19))
764 #define SCTLR_ELx_ENDB (BIT(13))
765 #define SCTLR_ELx_I (BIT(12))
766 #define SCTLR_ELx_EOS (BIT(11))
767 #define SCTLR_ELx_SA (BIT(3))
768 #define SCTLR_ELx_C (BIT(2))
769 #define SCTLR_ELx_A (BIT(1))
770 #define SCTLR_ELx_M (BIT(0))
773 #define SCTLR_EL2_RES1 ((BIT(4)) | (BIT(5)) | (BIT(11)) | (BIT(16)) | \
774 (BIT(18)) | (BIT(22)) | (BIT(23)) | (BIT(28)) | \
775 (BIT(29)))
777 #define SCTLR_EL2_BT (BIT(36))
865 #define CPACR_EL1_FPEN_EL1EN (BIT(20)) /* enable EL1 access */
866 #define CPACR_EL1_FPEN_EL0EN (BIT(21)) /* enable EL0 access, if EL1EN set */
868 #define CPACR_EL1_SMEN_EL1EN (BIT(24)) /* enable EL1 access */
869 #define CPACR_EL1_SMEN_EL0EN (BIT(25)) /* enable EL0 access, if EL1EN set */
871 #define CPACR_EL1_ZEN_EL1EN (BIT(16)) /* enable EL1 access */
872 #define CPACR_EL1_ZEN_EL0EN (BIT(17)) /* enable EL0 access, if EL1EN set */
875 #define SYS_GCR_EL1_RRND (BIT(16))
881 * only uses tags in the range 0xF0-0xFF, which we map to MTE tags 0x0-0xF.
898 /* TFSR{,E0}_EL1 bit definitions */
905 #define SYS_MPIDR_SAFE_VAL (BIT(31))
912 #define TRFCR_EL2_CX BIT(3)
913 #define TRFCR_ELx_ExTRE BIT(1)
914 #define TRFCR_ELx_E0TRE BIT(0)
917 /* ICH_MISR_EL2 bit definitions */
921 /* ICH_LR*_EL2 bit definitions */
922 #define ICH_LR_VIRTUAL_ID_MASK ((1ULL << 32) - 1)
935 /* ICH_HCR_EL2 bit definitions */
946 /* ICH_VMCR_EL2 bit definitions */
953 #define ICH_VMCR_EOIM_SHIFT 9
966 /* ICH_VTR_EL2 bit definitions */
1090 * set mask are set. Other bits are left as-is.