1 /* SPDX-License-Identifier: GPL-2.0-or-later */
8 # error Please include asm/mips-cps.h rather than asm/mips-cm.h
18 /* The base address of the CM GCR block */
21 /* The base address of the CM L2-only sync region */
25  * __mips_cm_phys_base - retrieve the physical base address of the CM
32  * name mips_cm_phys_base (without underscores).
37  * mips_cm_is64 - determine CM register width
39  * The CM register width is determined by the version of the CM, with CM3
40  * introducing 64 bit GCRs and all prior CM versions having 32 bit GCRs.
42  * or vice-versa. This variable indicates the width of the memory accesses
46  * It's set to 0 for 32-bit accesses and 1 for 64-bit accesses.
51  * mips_cm_is_l2_hci_broken  - determine if HCI is broken
53  * Some CM reports show that Hardware Cache Initialization is
61  * mips_cm_error_report - Report CM cache errors
70  * mips_cm_probe - probe for a Coherence Manager
72  * Attempt to detect the presence of a Coherence Manager. Returns 0 if a CM
73  * is successfully detected, else -errno.
80 	return -ENODEV;  in mips_cm_probe()
85  * mips_cm_present - determine whether a Coherence Manager is present
87  * Returns true if a CM is present in the system, else false.
99  * mips_cm_update_property - update property from the device tree
101  * Retrieve the properties from the device tree if a CM node exist and
111  * mips_cm_has_l2sync - determine whether an L2-only sync region is present
113  * Returns true if the system implements an L2-only sync region, else false.
124 /* Offsets to register blocks from the CM base address */
130 /* Total size of the CM memory mapped registers */
133 /* Size of the L2-only sync region */
136 #define GCR_ACCESSOR_RO(sz, off, name)					\  argument
137 	CPS_ACCESSOR_RO(gcr, sz, MIPS_CM_GCB_OFS + off, name)		\
138 	CPS_ACCESSOR_RO(gcr, sz, MIPS_CM_COCB_OFS + off, redir_##name)
140 #define GCR_ACCESSOR_RW(sz, off, name)					\  argument
141 	CPS_ACCESSOR_RW(gcr, sz, MIPS_CM_GCB_OFS + off, name)		\
142 	CPS_ACCESSOR_RW(gcr, sz, MIPS_CM_COCB_OFS + off, redir_##name)
144 #define GCR_CX_ACCESSOR_RO(sz, off, name)				\  argument
145 	CPS_ACCESSOR_RO(gcr, sz, MIPS_CM_CLCB_OFS + off, cl_##name)	\
146 	CPS_ACCESSOR_RO(gcr, sz, MIPS_CM_COCB_OFS + off, co_##name)
148 #define GCR_CX_ACCESSOR_RW(sz, off, name)				\  argument
149 	CPS_ACCESSOR_RW(gcr, sz, MIPS_CM_CLCB_OFS + off, cl_##name)	\
150 	CPS_ACCESSOR_RW(gcr, sz, MIPS_CM_COCB_OFS + off, co_##name)
152 /* GCR_CONFIG - Information about the system */
160 /* GCR_BASE - Base address of the Global Configuration Registers (GCRs) */
169 /* GCR_ACCESS - Controls core/IOCU access to GCRs */
173 /* GCR_REV - Indicates the Coherence Manager revision */
187 /* GCR_ERR_CONTROL - Control error checking logic */
192 /* GCR_ERR_MASK - Control which errors are reported as interrupts */
195 /* GCR_ERR_CAUSE - Indicates the type of error that occurred */
201 /* GCR_ERR_ADDR - Indicates the address associated with an error */
204 /* GCR_ERR_MULT - Indicates when multiple errors have occurred */
208 /* GCR_L2_ONLY_SYNC_BASE - Base address of the L2 cache-only sync region */
213 /* GCR_GIC_BASE - Base address of the Global Interrupt Controller (GIC) */
218 /* GCR_CPC_BASE - Base address of the Cluster Power Controller (CPC) */
223 /* GCR_REGn_BASE - Base addresses of CM address regions */
230 /* GCR_REGn_MASK - Size & destination of CM address regions */
245 /* GCR_GIC_STATUS - Indicates presence of a Global Interrupt Controller (GIC) */
249 /* GCR_CPC_STATUS - Indicates presence of a Cluster Power Controller (CPC) */
253 /* GCR_ACCESS - Controls core/IOCU access to GCRs */
257 /* GCR_L2_CONFIG - Indicates L2 cache configuration when Config5.L2C=1 */
264 /* GCR_SYS_CONFIG2 - Further information about the system */
268 /* GCR_L2_PFT_CONTROL - Controls hardware L2 prefetching */
274 /* GCR_L2_PFT_CONTROL_B - Controls hardware L2 prefetching */
279 /* GCR_L2SM_COP - L2 cache op state machine control */
301 /* GCR_L2SM_TAG_ADDR_COP - L2 cache op state machine address control */
306 /* GCR_BEV_BASE - Controls the location of the BEV for powered up cores */
309 /* GCR_Cx_RESET_RELEASE - Controls core reset for CM 1.x */
312 /* GCR_Cx_COHERENCE - Controls core coherence */
317 /* GCR_Cx_CONFIG - Information about a core's configuration */
322 /* GCR_Cx_OTHER - Configure the core-other/redirect GCR block */
324 #define CM_GCR_Cx_OTHER_CORENUM			GENMASK(31, 16)	/* CM < 3 */
325 #define CM_GCR_Cx_OTHER_CLUSTER_EN		BIT(31)		/* CM >= 3.5 */
326 #define CM_GCR_Cx_OTHER_GIC_EN			BIT(30)		/* CM >= 3.5 */
327 #define CM_GCR_Cx_OTHER_BLOCK			GENMASK(25, 24)	/* CM >= 3.5 */
332 #define CM_GCR_Cx_OTHER_CLUSTER			GENMASK(21, 16)	/* CM >= 3.5 */
333 #define CM3_GCR_Cx_OTHER_CORE			GENMASK(13, 8)	/* CM >= 3 */
335 #define CM3_GCR_Cx_OTHER_VP			GENMASK(2, 0)	/* CM >= 3 */
337 /* GCR_Cx_RESET_BASE - Configure where powered up cores will fetch from */
341 /* GCR_Cx_ID - Identify the current core */
346 /* GCR_Cx_RESET_EXT_BASE - Configure behaviour when cores reset or power up */
355  * mips_cm_l2sync - perform an L2-only sync operation
357  * If an L2-only sync region is present in the system then this function
358  * performs and L2-only sync and returns zero. Otherwise it returns -ENODEV.
363 		return -ENODEV;  in mips_cm_l2sync()
370  * mips_cm_revision() - return CM revision
372  * Return: The revision of the CM, from GCR_REV, or 0 if no CM is present. The
384  * mips_cm_max_vp_width() - return the width in bits of VP indices
413  * mips_cm_vp_id() - calculate the hardware VP ID for a CPU
433  * mips_cm_lock_other - lock access to redirect/other region
440  * the CM revision) to target the specified @cluster, @core, @vp & register
446  * mips_cm_unlock_other() calls cannot be pre-empted by anything which may
454  * mips_cm_unlock_other - unlock access to redirect/other region
470  * mips_cm_lock_other_cpu - lock access to redirect/other region
474  * the CM revision) to target the specified @cpu & register @block. This is