Lines Matching +full:uart0 +full:- +full:0
1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Copyright 2002-2005 MontaVista Software Inc.
30 switch (pvr & 0xf0000ff0) { in chip_11_errata()
31 case 0x40000850: in chip_11_errata()
32 case 0x400008d0: in chip_11_errata()
33 case 0x200008d0: in chip_11_errata()
34 memsize -= 4096; in chip_11_errata()
49 memsize = 0; in ibm4xx_sdram_fixup_memsize()
50 for (i = 0; i < ARRAY_SIZE(sdram_bxcr); i++) { in ibm4xx_sdram_fixup_memsize()
57 dt_fixup_memory(0, memsize); in ibm4xx_sdram_fixup_memsize()
61 #define DCRN_MQ0_B0BAS 0x40
62 #define DCRN_MQ0_B1BAS 0x41
63 #define DCRN_MQ0_B2BAS 0x42
64 #define DCRN_MQ0_B3BAS 0x43
68 u64 base = ((u64)(bas & 0xFFE00000u)) << 2; in ibm440spe_decode_bas()
71 switch ((bas >> 4) & 0xFFF) { in ibm440spe_decode_bas()
72 case 0: in ibm440spe_decode_bas()
73 return 0; in ibm440spe_decode_bas()
74 case 0xffc: in ibm440spe_decode_bas()
75 return base + 0x000800000ull; in ibm440spe_decode_bas()
76 case 0xff8: in ibm440spe_decode_bas()
77 return base + 0x001000000ull; in ibm440spe_decode_bas()
78 case 0xff0: in ibm440spe_decode_bas()
79 return base + 0x002000000ull; in ibm440spe_decode_bas()
80 case 0xfe0: in ibm440spe_decode_bas()
81 return base + 0x004000000ull; in ibm440spe_decode_bas()
82 case 0xfc0: in ibm440spe_decode_bas()
83 return base + 0x008000000ull; in ibm440spe_decode_bas()
84 case 0xf80: in ibm440spe_decode_bas()
85 return base + 0x010000000ull; in ibm440spe_decode_bas()
86 case 0xf00: in ibm440spe_decode_bas()
87 return base + 0x020000000ull; in ibm440spe_decode_bas()
88 case 0xe00: in ibm440spe_decode_bas()
89 return base + 0x040000000ull; in ibm440spe_decode_bas()
90 case 0xc00: in ibm440spe_decode_bas()
91 return base + 0x080000000ull; in ibm440spe_decode_bas()
92 case 0x800: in ibm440spe_decode_bas()
93 return base + 0x100000000ull; in ibm440spe_decode_bas()
95 printf("Memory BAS value 0x%08x unsupported !\n", bas); in ibm440spe_decode_bas()
96 return 0; in ibm440spe_decode_bas()
101 u64 banktop, memsize = 0; in ibm440spe_fixup_memsize()
119 dt_fixup_memory(0, memsize); in ibm440spe_fixup_memsize()
133 #define DDR_START 0x1
134 #define DDR_START_SHIFT 0
135 #define DDR_MAX_CS_REG 0x3
137 #define DDR_MAX_COL_REG 0xf
139 #define DDR_MAX_ROW_REG 0xf
142 #define DDR_DDR2_MODE 0x1
143 #define DDR_DDR2_MODE_SHIFT 0
145 #define DDR_CS_MAP 0x3
148 #define DDR_REDUC 0x1
151 #define DDR_APIN 0x7
154 #define DDR_COL_SZ 0x7
156 #define DDR_BANK8 0x1
157 #define DDR_BANK8_SHIFT 0
162 * Some U-Boot versions set the number of chipselects to two
178 if (getprop(devp, "model", model, sizeof(model)) <= 0) in ibm4xx_denali_get_cs()
181 model[sizeof(model)-1] = 0; in ibm4xx_denali_get_cs()
192 cs = 0; in ibm4xx_denali_get_cs()
194 if (val & 0x1) in ibm4xx_denali_get_cs()
236 row = max_row - row; in ibm4xx_denali_fixup_memsize()
244 col = max_col - col; in ibm4xx_denali_fixup_memsize()
253 dt_fixup_memory(0, memsize); in ibm4xx_denali_fixup_memsize()
256 #define SPRN_DBCR0_40X 0x3F2
257 #define SPRN_DBCR0_44X 0x134
258 #define DBCR0_RST_SYSTEM 0x30000000
265 "mfspr %0,%1\n" in ibm44x_dbcr_reset()
266 "oris %0,%0,%2@h\n" in ibm44x_dbcr_reset()
267 "mtspr %1,%0" in ibm44x_dbcr_reset()
278 "mfspr %0,%1\n" in ibm40x_dbcr_reset()
279 "oris %0,%0,%2@h\n" in ibm40x_dbcr_reset()
280 "mtspr %1,%0" in ibm40x_dbcr_reset()
285 #define EMAC_RESET 0x20000000
311 for (i = 0; i < EBC_NUM_BANKS; i++) { in ibm4xx_fixup_ebc_ranges()
317 *p++ = 0; in ibm4xx_fixup_ebc_ranges()
327 setprop(devp, "ranges", ranges, (p - ranges) * sizeof(u32)); in ibm4xx_fixup_ebc_ranges()
335 u32 cpu, plb, opb, ebc, tb, uart0, uart1, m; in ibm440gp_fixup_clocks() local
357 if ((mfpvr() & 0xf0000fff) == 0x40000440) in ibm440gp_fixup_clocks()
366 uart0 = ser_clk; in ibm440gp_fixup_clocks()
369 uart0 = plb / CPC0_CR0_UDIV(cr0); in ibm440gp_fixup_clocks()
381 dt_fixup_cpu_clocks(cpu, tb, 0); in ibm440gp_fixup_clocks()
386 dt_fixup_clock("/plb/opb/serial@40000200", uart0); in ibm440gp_fixup_clocks()
390 #define SPRN_CCR1 0x378
406 u32 fbdv = __fix_zero((plld >> 24) & 0x1f, 32); in __ibm440eplike_fixup_clocks()
407 u32 fwdva = __fix_zero((plld >> 16) & 0xf, 16); in __ibm440eplike_fixup_clocks()
409 u32 lfbdv = __fix_zero(plld & 0x3f, 64); in __ibm440eplike_fixup_clocks()
424 if (pllc & 0x40000000) { in __ibm440eplike_fixup_clocks()
429 case 0: in __ibm440eplike_fixup_clocks()
431 m = ((pllc & 0x20000000) ? fwdvb : fwdva) * lfbdv; in __ibm440eplike_fixup_clocks()
452 vco = 0; in __ibm440eplike_fixup_clocks()
464 /* If passed a 0 tmr_clk, force CPU clock */ in __ibm440eplike_fixup_clocks()
465 if (tb == 0) { in __ibm440eplike_fixup_clocks()
466 ccr1 &= ~0x80u; in __ibm440eplike_fixup_clocks()
469 if ((ccr1 & 0x0080) == 0) in __ibm440eplike_fixup_clocks()
472 dt_fixup_cpu_clocks(cpu, tb, 0); in __ibm440eplike_fixup_clocks()
488 case 0: in eplike_fixup_uart_clk()
504 if (sdr & 0x00800000u) in eplike_fixup_uart_clk()
507 clock = plb_clk / __fix_zero(sdr & 0xff, 256); in eplike_fixup_uart_clk()
516 unsigned int plb_clk = __ibm440eplike_fixup_clocks(sys_clk, tmr_clk, 0); in ibm440ep_fixup_clocks()
519 eplike_fixup_uart_clk(0, "/plb/opb/serial@ef600300", ser_clk, plb_clk); in ibm440ep_fixup_clocks()
532 eplike_fixup_uart_clk(0, "/plb/opb/serial@40000200", ser_clk, plb_clk); in ibm440gx_fixup_clocks()
543 eplike_fixup_uart_clk(0, "/plb/opb/serial@f0000200", ser_clk, plb_clk); in ibm440spe_fixup_clocks()
554 u32 cpu, plb, opb, ebc, tb, uart0, uart1, m; in ibm405gp_fixup_clocks() local
557 fwdv = (8 - ((pllmr & 0xe0000000) >> 29)); in ibm405gp_fixup_clocks()
558 fbdv = (pllmr & 0x1e000000) >> 25; in ibm405gp_fixup_clocks()
559 if (fbdv == 0) in ibm405gp_fixup_clocks()
561 cbdv = ((pllmr & 0x00060000) >> 17) + 1; /* CPU:PLB */ in ibm405gp_fixup_clocks()
562 opdv = ((pllmr & 0x00018000) >> 15) + 1; /* PLB:OPB */ in ibm405gp_fixup_clocks()
563 ppdv = ((pllmr & 0x00006000) >> 13) + 1; /* PLB:PCI */ in ibm405gp_fixup_clocks()
564 epdv = ((pllmr & 0x00001800) >> 11) + 2; /* PLB:EBC */ in ibm405gp_fixup_clocks()
565 udiv = ((cpc0_cr0 & 0x3e) >> 1) + 1; in ibm405gp_fixup_clocks()
568 if ((mfpvr() & 0xfffffff0) == (0x50910951 & 0xfffffff0)) { in ibm405gp_fixup_clocks()
569 fwdvb = 8 - (pllmr & 0x00000007); in ibm405gp_fixup_clocks()
570 if (!(psr & 0x00001000)) /* PCI async mode enable == 0 */ in ibm405gp_fixup_clocks()
571 if (psr & 0x00000020) /* New mode enable */ in ibm405gp_fixup_clocks()
575 else if (psr & 0x00000020) /* New mode enable */ in ibm405gp_fixup_clocks()
576 if (psr & 0x00000800) /* PerClk synch mode */ in ibm405gp_fixup_clocks()
595 if (cpc0_cr0 & 0x80) in ibm405gp_fixup_clocks()
596 /* uart0 uses the external clock */ in ibm405gp_fixup_clocks()
597 uart0 = ser_clk; in ibm405gp_fixup_clocks()
599 uart0 = cpu / udiv; in ibm405gp_fixup_clocks()
601 if (cpc0_cr0 & 0x40) in ibm405gp_fixup_clocks()
608 cpc0_cr1 = cpc0_cr1 & ~0x00800000; in ibm405gp_fixup_clocks()
612 dt_fixup_cpu_clocks(cpu, tb, 0); in ibm405gp_fixup_clocks()
616 dt_fixup_clock("/plb/opb/serial@ef600300", uart0); in ibm405gp_fixup_clocks()
626 u32 cpu, plb, opb, ebc, uart0, uart1; in ibm405ep_fixup_clocks() local
630 fwdva = 8 - ((pllmr1 & 0x00070000) >> 16); in ibm405ep_fixup_clocks()
631 fwdvb = 8 - ((pllmr1 & 0x00007000) >> 12); in ibm405ep_fixup_clocks()
632 fbdv = (pllmr1 & 0x00f00000) >> 20; in ibm405ep_fixup_clocks()
633 if (fbdv == 0) in ibm405ep_fixup_clocks()
636 cbdv = ((pllmr0 & 0x00030000) >> 16) + 1; /* CPU:PLB */ in ibm405ep_fixup_clocks()
637 epdv = ((pllmr0 & 0x00000300) >> 8) + 2; /* PLB:EBC */ in ibm405ep_fixup_clocks()
638 opdv = ((pllmr0 & 0x00003000) >> 12) + 1; /* PLB:OPB */ in ibm405ep_fixup_clocks()
642 pllmr0_ccdv = ((pllmr0 & 0x00300000) >> 20) + 1; in ibm405ep_fixup_clocks()
643 if (pllmr1 & 0x80000000) in ibm405ep_fixup_clocks()
652 uart0 = cpu / (cpc0_ucr & 0x0000007f); in ibm405ep_fixup_clocks()
653 uart1 = cpu / ((cpc0_ucr & 0x00007f00) >> 8); in ibm405ep_fixup_clocks()
655 dt_fixup_cpu_clocks(cpu, tb, 0); in ibm405ep_fixup_clocks()
659 dt_fixup_clock("/plb/opb/serial@ef600300", uart0); in ibm405ep_fixup_clocks()
664 /* values for: 1 - 16 */
665 0x01, 0x02, 0x0e, 0x09, 0x04, 0x0b, 0x10, 0x0d, 0x0c, 0x05,
666 0x06, 0x0f, 0x0a, 0x07, 0x08, 0x03
673 for (index = 0; index < ARRAY_SIZE(ibm405ex_fwdv_multi_bits); index++) in ibm405ex_get_fwdva()
677 return 0; in ibm405ex_get_fwdva()
681 /* values for: 1 - 100 */
682 0x00, 0xff, 0x7e, 0xfd, 0x7a, 0xf5, 0x6a, 0xd5, 0x2a, 0xd4,
683 0x29, 0xd3, 0x26, 0xcc, 0x19, 0xb3, 0x67, 0xce, 0x1d, 0xbb,
684 0x77, 0xee, 0x5d, 0xba, 0x74, 0xe9, 0x52, 0xa5, 0x4b, 0x96,
685 0x2c, 0xd8, 0x31, 0xe3, 0x46, 0x8d, 0x1b, 0xb7, 0x6f, 0xde,
686 0x3d, 0xfb, 0x76, 0xed, 0x5a, 0xb5, 0x6b, 0xd6, 0x2d, 0xdb,
687 0x36, 0xec, 0x59, 0xb2, 0x64, 0xc9, 0x12, 0xa4, 0x48, 0x91,
688 0x23, 0xc7, 0x0e, 0x9c, 0x38, 0xf0, 0x61, 0xc2, 0x05, 0x8b,
689 0x17, 0xaf, 0x5f, 0xbe, 0x7c, 0xf9, 0x72, 0xe5, 0x4a, 0x95,
690 0x2b, 0xd7, 0x2e, 0xdc, 0x39, 0xf3, 0x66, 0xcd, 0x1a, 0xb4,
691 0x68, 0xd1, 0x22, 0xc4, 0x09, 0x93, 0x27, 0xcf, 0x1e, 0xbc,
692 /* values for: 101 - 200 */
693 0x78, 0xf1, 0x62, 0xc5, 0x0a, 0x94, 0x28, 0xd0, 0x21, 0xc3,
694 0x06, 0x8c, 0x18, 0xb0, 0x60, 0xc1, 0x02, 0x84, 0x08, 0x90,
695 0x20, 0xc0, 0x01, 0x83, 0x07, 0x8f, 0x1f, 0xbf, 0x7f, 0xfe,
696 0x7d, 0xfa, 0x75, 0xea, 0x55, 0xaa, 0x54, 0xa9, 0x53, 0xa6,
697 0x4c, 0x99, 0x33, 0xe7, 0x4e, 0x9d, 0x3b, 0xf7, 0x6e, 0xdd,
698 0x3a, 0xf4, 0x69, 0xd2, 0x25, 0xcb, 0x16, 0xac, 0x58, 0xb1,
699 0x63, 0xc6, 0x0d, 0x9b, 0x37, 0xef, 0x5e, 0xbd, 0x7b, 0xf6,
700 0x6d, 0xda, 0x35, 0xeb, 0x56, 0xad, 0x5b, 0xb6, 0x6c, 0xd9,
701 0x32, 0xe4, 0x49, 0x92, 0x24, 0xc8, 0x11, 0xa3, 0x47, 0x8e,
702 0x1c, 0xb8, 0x70, 0xe1, 0x42, 0x85, 0x0b, 0x97, 0x2f, 0xdf,
703 /* values for: 201 - 255 */
704 0x3e, 0xfc, 0x79, 0xf2, 0x65, 0xca, 0x15, 0xab, 0x57, 0xae,
705 0x5c, 0xb9, 0x73, 0xe6, 0x4d, 0x9a, 0x34, 0xe8, 0x51, 0xa2,
706 0x44, 0x89, 0x13, 0xa7, 0x4f, 0x9e, 0x3c, 0xf8, 0x71, 0xe2,
707 0x45, 0x8a, 0x14, 0xa8, 0x50, 0xa1, 0x43, 0x86, 0x0c, 0x98,
708 0x30, 0xe0, 0x41, 0x82, 0x04, 0x88, 0x10, 0xa0, 0x40, 0x81,
709 0x03, 0x87, 0x0f, 0x9f, 0x3f /* END */
716 for (index = 0; index < ARRAY_SIZE(ibm405ex_fbdv_multi_bits); index++) in ibm405ex_get_fbdv()
720 return 0; in ibm405ex_get_fbdv()
734 u32 fbdv = ibm405ex_get_fbdv(__fix_zero((plld >> 24) & 0xff, 1)); in ibm405ex_fixup_clocks()
736 u32 fwdva = ibm405ex_get_fwdva(__fix_zero((plld >> 16) & 0x0f, 1)); in ibm405ex_fixup_clocks()
749 u32 cpu, plb, opb, ebc, vco, tb, uart0, uart1; in ibm405ex_fixup_clocks() local
752 if (pllc & 0x40000000) { in ibm405ex_fixup_clocks()
757 case 0: in ibm405ex_fixup_clocks()
778 vco = 0; in ibm405ex_fixup_clocks()
791 uart0 = uart1 = uart_clk; in ibm405ex_fixup_clocks()
793 dt_fixup_cpu_clocks(cpu, tb, 0); in ibm405ex_fixup_clocks()
797 dt_fixup_clock("/plb/opb/serial@ef600200", uart0); in ibm405ex_fixup_clocks()