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1 /* SPDX-License-Identifier: GPL-2.0 */
18 * MICROARCH Is the code name for the micro-architecture for this core.
24 * - regular client parts
25 * _L - regular mobile parts
26 * _G - parts with extra graphics on
27 * _X - regular server parts
28 * _D - micro server parts
29 * _N,_P - other mobile parts
30 * _H - premium mobile parts
31 * _S - other client parts
35 * _EP - 2 socket server parts
36 * _EX - 4+ socket server parts
40 * their own names :-(
50 #define INTEL_FAM6_CORE_YONAH 0x0E
51 #define INTEL_CORE_YONAH IFM(6, 0x0E)
53 #define INTEL_FAM6_CORE2_MEROM 0x0F
54 #define INTEL_CORE2_MEROM IFM(6, 0x0F)
55 #define INTEL_FAM6_CORE2_MEROM_L 0x16
56 #define INTEL_CORE2_MEROM_L IFM(6, 0x16)
57 #define INTEL_FAM6_CORE2_PENRYN 0x17
58 #define INTEL_CORE2_PENRYN IFM(6, 0x17)
59 #define INTEL_FAM6_CORE2_DUNNINGTON 0x1D
60 #define INTEL_CORE2_DUNNINGTON IFM(6, 0x1D)
62 #define INTEL_FAM6_NEHALEM 0x1E
63 #define INTEL_NEHALEM IFM(6, 0x1E)
64 #define INTEL_FAM6_NEHALEM_G 0x1F /* Auburndale / Havendale */
65 #define INTEL_NEHALEM_G IFM(6, 0x1F) /* Auburndale / Havendale */
66 #define INTEL_FAM6_NEHALEM_EP 0x1A
67 #define INTEL_NEHALEM_EP IFM(6, 0x1A)
68 #define INTEL_FAM6_NEHALEM_EX 0x2E
69 #define INTEL_NEHALEM_EX IFM(6, 0x2E)
71 #define INTEL_FAM6_WESTMERE 0x25
72 #define INTEL_WESTMERE IFM(6, 0x25)
73 #define INTEL_FAM6_WESTMERE_EP 0x2C
74 #define INTEL_WESTMERE_EP IFM(6, 0x2C)
75 #define INTEL_FAM6_WESTMERE_EX 0x2F
76 #define INTEL_WESTMERE_EX IFM(6, 0x2F)
78 #define INTEL_FAM6_SANDYBRIDGE 0x2A
79 #define INTEL_SANDYBRIDGE IFM(6, 0x2A)
80 #define INTEL_FAM6_SANDYBRIDGE_X 0x2D
81 #define INTEL_SANDYBRIDGE_X IFM(6, 0x2D)
82 #define INTEL_FAM6_IVYBRIDGE 0x3A
83 #define INTEL_IVYBRIDGE IFM(6, 0x3A)
84 #define INTEL_FAM6_IVYBRIDGE_X 0x3E
85 #define INTEL_IVYBRIDGE_X IFM(6, 0x3E)
87 #define INTEL_FAM6_HASWELL 0x3C
88 #define INTEL_HASWELL IFM(6, 0x3C)
89 #define INTEL_FAM6_HASWELL_X 0x3F
90 #define INTEL_HASWELL_X IFM(6, 0x3F)
91 #define INTEL_FAM6_HASWELL_L 0x45
92 #define INTEL_HASWELL_L IFM(6, 0x45)
93 #define INTEL_FAM6_HASWELL_G 0x46
94 #define INTEL_HASWELL_G IFM(6, 0x46)
96 #define INTEL_FAM6_BROADWELL 0x3D
97 #define INTEL_BROADWELL IFM(6, 0x3D)
98 #define INTEL_FAM6_BROADWELL_G 0x47
99 #define INTEL_BROADWELL_G IFM(6, 0x47)
100 #define INTEL_FAM6_BROADWELL_X 0x4F
101 #define INTEL_BROADWELL_X IFM(6, 0x4F)
102 #define INTEL_FAM6_BROADWELL_D 0x56
103 #define INTEL_BROADWELL_D IFM(6, 0x56)
105 #define INTEL_FAM6_SKYLAKE_L 0x4E /* Sky Lake */
106 #define INTEL_SKYLAKE_L IFM(6, 0x4E) /* Sky Lake */
107 #define INTEL_FAM6_SKYLAKE 0x5E /* Sky Lake */
108 #define INTEL_SKYLAKE IFM(6, 0x5E) /* Sky Lake */
109 #define INTEL_FAM6_SKYLAKE_X 0x55 /* Sky Lake */
110 #define INTEL_SKYLAKE_X IFM(6, 0x55) /* Sky Lake */
111 /* CASCADELAKE_X 0x55 Sky Lake -- s: 7 */
112 /* COOPERLAKE_X 0x55 Sky Lake -- s: 11 */
114 #define INTEL_FAM6_KABYLAKE_L 0x8E /* Sky Lake */
115 #define INTEL_KABYLAKE_L IFM(6, 0x8E) /* Sky Lake */
116 /* AMBERLAKE_L 0x8E Sky Lake -- s: 9 */
117 /* COFFEELAKE_L 0x8E Sky Lake -- s: 10 */
118 /* WHISKEYLAKE_L 0x8E Sky Lake -- s: 11,12 */
120 #define INTEL_FAM6_KABYLAKE 0x9E /* Sky Lake */
121 #define INTEL_KABYLAKE IFM(6, 0x9E) /* Sky Lake */
122 /* COFFEELAKE 0x9E Sky Lake -- s: 10-13 */
124 #define INTEL_FAM6_COMETLAKE 0xA5 /* Sky Lake */
125 #define INTEL_COMETLAKE IFM(6, 0xA5) /* Sky Lake */
126 #define INTEL_FAM6_COMETLAKE_L 0xA6 /* Sky Lake */
127 #define INTEL_COMETLAKE_L IFM(6, 0xA6) /* Sky Lake */
129 #define INTEL_FAM6_CANNONLAKE_L 0x66 /* Palm Cove */
130 #define INTEL_CANNONLAKE_L IFM(6, 0x66) /* Palm Cove */
132 #define INTEL_FAM6_ICELAKE_X 0x6A /* Sunny Cove */
133 #define INTEL_ICELAKE_X IFM(6, 0x6A) /* Sunny Cove */
134 #define INTEL_FAM6_ICELAKE_D 0x6C /* Sunny Cove */
135 #define INTEL_ICELAKE_D IFM(6, 0x6C) /* Sunny Cove */
136 #define INTEL_FAM6_ICELAKE 0x7D /* Sunny Cove */
137 #define INTEL_ICELAKE IFM(6, 0x7D) /* Sunny Cove */
138 #define INTEL_FAM6_ICELAKE_L 0x7E /* Sunny Cove */
139 #define INTEL_ICELAKE_L IFM(6, 0x7E) /* Sunny Cove */
140 #define INTEL_FAM6_ICELAKE_NNPI 0x9D /* Sunny Cove */
141 #define INTEL_ICELAKE_NNPI IFM(6, 0x9D) /* Sunny Cove */
143 #define INTEL_FAM6_ROCKETLAKE 0xA7 /* Cypress Cove */
144 #define INTEL_ROCKETLAKE IFM(6, 0xA7) /* Cypress Cove */
146 #define INTEL_FAM6_TIGERLAKE_L 0x8C /* Willow Cove */
147 #define INTEL_TIGERLAKE_L IFM(6, 0x8C) /* Willow Cove */
148 #define INTEL_FAM6_TIGERLAKE 0x8D /* Willow Cove */
149 #define INTEL_TIGERLAKE IFM(6, 0x8D) /* Willow Cove */
151 #define INTEL_FAM6_SAPPHIRERAPIDS_X 0x8F /* Golden Cove */
152 #define INTEL_SAPPHIRERAPIDS_X IFM(6, 0x8F) /* Golden Cove */
154 #define INTEL_FAM6_EMERALDRAPIDS_X 0xCF
155 #define INTEL_EMERALDRAPIDS_X IFM(6, 0xCF)
157 #define INTEL_FAM6_GRANITERAPIDS_X 0xAD
158 #define INTEL_GRANITERAPIDS_X IFM(6, 0xAD)
159 #define INTEL_FAM6_GRANITERAPIDS_D 0xAE
160 #define INTEL_GRANITERAPIDS_D IFM(6, 0xAE)
162 #define INTEL_BARTLETTLAKE IFM(6, 0xD7) /* Raptor Cove */
164 /* "Hybrid" Processors (P-Core/E-Core) */
166 #define INTEL_FAM6_LAKEFIELD 0x8A /* Sunny Cove / Tremont */
167 #define INTEL_LAKEFIELD IFM(6, 0x8A) /* Sunny Cove / Tremont */
169 #define INTEL_FAM6_ALDERLAKE 0x97 /* Golden Cove / Gracemont */
170 #define INTEL_ALDERLAKE IFM(6, 0x97) /* Golden Cove / Gracemont */
171 #define INTEL_FAM6_ALDERLAKE_L 0x9A /* Golden Cove / Gracemont */
172 #define INTEL_ALDERLAKE_L IFM(6, 0x9A) /* Golden Cove / Gracemont */
174 #define INTEL_FAM6_RAPTORLAKE 0xB7 /* Raptor Cove / Enhanced Gracemont */
175 #define INTEL_RAPTORLAKE IFM(6, 0xB7) /* Raptor Cove / Enhanced Gracemont */
176 #define INTEL_FAM6_RAPTORLAKE_P 0xBA
177 #define INTEL_RAPTORLAKE_P IFM(6, 0xBA)
178 #define INTEL_FAM6_RAPTORLAKE_S 0xBF
179 #define INTEL_RAPTORLAKE_S IFM(6, 0xBF)
181 #define INTEL_FAM6_METEORLAKE 0xAC
182 #define INTEL_METEORLAKE IFM(6, 0xAC)
183 #define INTEL_FAM6_METEORLAKE_L 0xAA
184 #define INTEL_METEORLAKE_L IFM(6, 0xAA)
186 #define INTEL_FAM6_ARROWLAKE_H 0xC5
187 #define INTEL_ARROWLAKE_H IFM(6, 0xC5)
188 #define INTEL_FAM6_ARROWLAKE 0xC6
189 #define INTEL_ARROWLAKE IFM(6, 0xC6)
190 #define INTEL_FAM6_ARROWLAKE_U 0xB5
191 #define INTEL_ARROWLAKE_U IFM(6, 0xB5)
193 #define INTEL_FAM6_LUNARLAKE_M 0xBD
194 #define INTEL_LUNARLAKE_M IFM(6, 0xBD)
196 /* "Small Core" Processors (Atom/E-Core) */
198 #define INTEL_FAM6_ATOM_BONNELL 0x1C /* Diamondville, Pineview */
199 #define INTEL_ATOM_BONNELL IFM(6, 0x1C) /* Diamondville, Pineview */
200 #define INTEL_FAM6_ATOM_BONNELL_MID 0x26 /* Silverthorne, Lincroft */
201 #define INTEL_ATOM_BONNELL_MID IFM(6, 0x26) /* Silverthorne, Lincroft */
203 #define INTEL_FAM6_ATOM_SALTWELL 0x36 /* Cedarview */
204 #define INTEL_ATOM_SALTWELL IFM(6, 0x36) /* Cedarview */
205 #define INTEL_FAM6_ATOM_SALTWELL_MID 0x27 /* Penwell */
206 #define INTEL_ATOM_SALTWELL_MID IFM(6, 0x27) /* Penwell */
207 #define INTEL_FAM6_ATOM_SALTWELL_TABLET 0x35 /* Cloverview */
208 #define INTEL_ATOM_SALTWELL_TABLET IFM(6, 0x35) /* Cloverview */
210 #define INTEL_FAM6_ATOM_SILVERMONT 0x37 /* Bay Trail, Valleyview */
211 #define INTEL_ATOM_SILVERMONT IFM(6, 0x37) /* Bay Trail, Valleyview */
212 #define INTEL_FAM6_ATOM_SILVERMONT_D 0x4D /* Avaton, Rangely */
213 #define INTEL_ATOM_SILVERMONT_D IFM(6, 0x4D) /* Avaton, Rangely */
214 #define INTEL_FAM6_ATOM_SILVERMONT_MID 0x4A /* Merriefield */
215 #define INTEL_ATOM_SILVERMONT_MID IFM(6, 0x4A) /* Merriefield */
217 #define INTEL_FAM6_ATOM_AIRMONT 0x4C /* Cherry Trail, Braswell */
218 #define INTEL_ATOM_AIRMONT IFM(6, 0x4C) /* Cherry Trail, Braswell */
219 #define INTEL_FAM6_ATOM_AIRMONT_MID 0x5A /* Moorefield */
220 #define INTEL_ATOM_AIRMONT_MID IFM(6, 0x5A) /* Moorefield */
221 #define INTEL_FAM6_ATOM_AIRMONT_NP 0x75 /* Lightning Mountain */
222 #define INTEL_ATOM_AIRMONT_NP IFM(6, 0x75) /* Lightning Mountain */
224 #define INTEL_FAM6_ATOM_GOLDMONT 0x5C /* Apollo Lake */
225 #define INTEL_ATOM_GOLDMONT IFM(6, 0x5C) /* Apollo Lake */
226 #define INTEL_FAM6_ATOM_GOLDMONT_D 0x5F /* Denverton */
227 #define INTEL_ATOM_GOLDMONT_D IFM(6, 0x5F) /* Denverton */
229 /* Note: the micro-architecture is "Goldmont Plus" */
230 #define INTEL_FAM6_ATOM_GOLDMONT_PLUS 0x7A /* Gemini Lake */
231 #define INTEL_ATOM_GOLDMONT_PLUS IFM(6, 0x7A) /* Gemini Lake */
233 #define INTEL_FAM6_ATOM_TREMONT_D 0x86 /* Jacobsville */
234 #define INTEL_ATOM_TREMONT_D IFM(6, 0x86) /* Jacobsville */
235 #define INTEL_FAM6_ATOM_TREMONT 0x96 /* Elkhart Lake */
236 #define INTEL_ATOM_TREMONT IFM(6, 0x96) /* Elkhart Lake */
237 #define INTEL_FAM6_ATOM_TREMONT_L 0x9C /* Jasper Lake */
238 #define INTEL_ATOM_TREMONT_L IFM(6, 0x9C) /* Jasper Lake */
240 #define INTEL_FAM6_ATOM_GRACEMONT 0xBE /* Alderlake N */
241 #define INTEL_ATOM_GRACEMONT IFM(6, 0xBE) /* Alderlake N */
243 #define INTEL_FAM6_ATOM_CRESTMONT_X 0xAF /* Sierra Forest */
244 #define INTEL_ATOM_CRESTMONT_X IFM(6, 0xAF) /* Sierra Forest */
245 #define INTEL_FAM6_ATOM_CRESTMONT 0xB6 /* Grand Ridge */
246 #define INTEL_ATOM_CRESTMONT IFM(6, 0xB6) /* Grand Ridge */
248 #define INTEL_FAM6_ATOM_DARKMONT_X 0xDD /* Clearwater Forest */
249 #define INTEL_ATOM_DARKMONT_X IFM(6, 0xDD) /* Clearwater Forest */
253 #define INTEL_FAM6_XEON_PHI_KNL 0x57 /* Knights Landing */
254 #define INTEL_XEON_PHI_KNL IFM(6, 0x57) /* Knights Landing */
255 #define INTEL_FAM6_XEON_PHI_KNM 0x85 /* Knights Mill */
256 #define INTEL_XEON_PHI_KNM IFM(6, 0x85) /* Knights Mill */
259 #define INTEL_FAM5_QUARK_X1000 0x09 /* Quark X1000 SoC */
260 #define INTEL_QUARK_X1000 IFM(5, 0x09) /* Quark X1000 SoC */