Lines Matching full:hw
65 .hw.init = &(struct clk_init_data){
82 .hw.init = &(struct clk_init_data){
86 &g12a_fixed_pll_dco.hw
130 .hw.init = &(struct clk_init_data){
149 .hw.init = &(struct clk_init_data){
153 &g12a_sys_pll_dco.hw
189 .hw.init = &(struct clk_init_data){
208 .hw.init = &(struct clk_init_data){
212 &g12b_sys1_pll_dco.hw
224 .hw.init = &(struct clk_init_data) {
227 .parent_hws = (const struct clk_hw *[]) { &g12a_sys_pll.hw },
241 .hw.init = &(struct clk_init_data) {
245 &g12b_sys1_pll.hw
258 .hw.init = &(struct clk_init_data){
262 &g12a_sys_pll_div16_en.hw
271 .hw.init = &(struct clk_init_data){
275 &g12b_sys1_pll_div16_en.hw
284 .hw.init = &(struct clk_init_data){
287 .parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },
297 .hw.init = &(struct clk_init_data){
301 &g12a_fclk_div2_div.hw
321 .hw.init = &(struct clk_init_data){
324 .parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },
334 .hw.init = &(struct clk_init_data){
338 &g12a_fclk_div3_div.hw
362 .hw.init = &(struct clk_init_data){
367 { .hw = &g12a_fclk_div2.hw },
368 { .hw = &g12a_fclk_div3.hw },
382 .hw.init = &(struct clk_init_data){
387 { .hw = &g12a_fclk_div2.hw },
388 { .hw = &g12a_fclk_div3.hw },
410 .hw.init = &(struct clk_init_data){
414 &g12a_cpu_clk_premux0.hw
429 .hw.init = &(struct clk_init_data){
433 &g12a_cpu_clk_premux0.hw,
434 &g12a_cpu_clk_mux0_div.hw,
448 .hw.init = &(struct clk_init_data){
452 &g12a_cpu_clk_premux1.hw
465 .hw.init = &(struct clk_init_data){
469 &g12a_cpu_clk_premux1.hw,
470 &g12a_cpu_clk_mux1_div.hw,
486 .hw.init = &(struct clk_init_data){
490 &g12a_cpu_clk_postmux0.hw,
491 &g12a_cpu_clk_postmux1.hw,
506 .hw.init = &(struct clk_init_data){
510 &g12a_cpu_clk_dyn.hw,
511 &g12a_sys_pll.hw,
526 .hw.init = &(struct clk_init_data){
530 &g12a_cpu_clk_dyn.hw,
531 &g12b_sys1_pll.hw
546 .hw.init = &(struct clk_init_data){
551 { .hw = &g12a_fclk_div2.hw },
552 { .hw = &g12a_fclk_div3.hw },
573 .hw.init = &(struct clk_init_data){
577 &g12b_cpub_clk_premux0.hw
592 .hw.init = &(struct clk_init_data){
596 &g12b_cpub_clk_premux0.hw,
597 &g12b_cpub_clk_mux0_div.hw
611 .hw.init = &(struct clk_init_data){
616 { .hw = &g12a_fclk_div2.hw },
617 { .hw = &g12a_fclk_div3.hw },
632 .hw.init = &(struct clk_init_data){
636 &g12b_cpub_clk_premux1.hw
649 .hw.init = &(struct clk_init_data){
653 &g12b_cpub_clk_premux1.hw,
654 &g12b_cpub_clk_mux1_div.hw
670 .hw.init = &(struct clk_init_data){
674 &g12b_cpub_clk_postmux0.hw,
675 &g12b_cpub_clk_postmux1.hw
690 .hw.init = &(struct clk_init_data){
694 &g12b_cpub_clk_dyn.hw,
695 &g12a_sys_pll.hw
711 .hw.init = &(struct clk_init_data){
716 { .hw = &g12a_fclk_div2.hw },
717 { .hw = &g12a_fclk_div3.hw },
718 { .hw = &sm1_gp1_pll.hw },
731 .hw.init = &(struct clk_init_data){
736 { .hw = &g12a_fclk_div2.hw },
737 { .hw = &g12a_fclk_div3.hw },
738 { .hw = &sm1_gp1_pll.hw },
751 .hw.init = &(struct clk_init_data){
755 &sm1_dsu_clk_premux0.hw
768 .hw.init = &(struct clk_init_data){
772 &sm1_dsu_clk_premux0.hw,
773 &sm1_dsu_clk_mux0_div.hw,
786 .hw.init = &(struct clk_init_data){
790 &sm1_dsu_clk_premux1.hw
803 .hw.init = &(struct clk_init_data){
807 &sm1_dsu_clk_premux1.hw,
808 &sm1_dsu_clk_mux1_div.hw,
821 .hw.init = &(struct clk_init_data){
825 &sm1_dsu_clk_postmux0.hw,
826 &sm1_dsu_clk_postmux1.hw,
839 .hw.init = &(struct clk_init_data){
843 &sm1_dsu_clk_dyn.hw,
844 &g12a_sys_pll.hw,
857 .hw.init = &(struct clk_init_data){
861 &g12a_cpu_clk.hw,
875 .hw.init = &(struct clk_init_data){
879 &g12a_cpu_clk.hw,
893 .hw.init = &(struct clk_init_data){
897 &g12a_cpu_clk.hw,
911 .hw.init = &(struct clk_init_data){
915 &g12a_cpu_clk.hw,
916 &sm1_dsu_final_clk.hw,
1028 .cpu_clk_dyn = &g12a_cpu_clk_dyn.hw,
1029 .cpu_clk_postmux0 = &g12a_cpu_clk_postmux0.hw,
1030 .cpu_clk_postmux1 = &g12a_cpu_clk_postmux1.hw,
1031 .cpu_clk_premux1 = &g12a_cpu_clk_premux1.hw,
1036 .cpu_clk_dyn = &g12b_cpub_clk_dyn.hw,
1037 .cpu_clk_postmux0 = &g12b_cpub_clk_postmux0.hw,
1038 .cpu_clk_postmux1 = &g12b_cpub_clk_postmux1.hw,
1039 .cpu_clk_premux1 = &g12b_cpub_clk_premux1.hw,
1111 .sys_pll = &g12a_sys_pll.hw,
1112 .cpu_clk = &g12a_cpu_clk.hw,
1113 .cpu_clk_dyn = &g12a_cpu_clk_dyn.hw,
1119 .sys_pll = &g12b_sys1_pll.hw,
1120 .cpu_clk = &g12b_cpu_clk.hw,
1121 .cpu_clk_dyn = &g12a_cpu_clk_dyn.hw,
1127 .sys_pll = &g12a_sys_pll.hw,
1128 .cpu_clk = &g12b_cpub_clk.hw,
1129 .cpu_clk_dyn = &g12b_cpub_clk_dyn.hw,
1138 .hw.init = &(struct clk_init_data) {
1167 .hw.init = &(struct clk_init_data) {
1171 &g12b_cpub_clk.hw
1184 .hw.init = &(struct clk_init_data){
1188 &g12a_cpu_clk_div16_en.hw
1197 .hw.init = &(struct clk_init_data){
1201 &g12b_cpub_clk_div16_en.hw
1214 .hw.init = &(struct clk_init_data){
1230 .hw.init = &(struct clk_init_data) {
1234 &g12a_cpu_clk_apb_div.hw
1251 .hw.init = &(struct clk_init_data){
1267 .hw.init = &(struct clk_init_data) {
1271 &g12a_cpu_clk_atb_div.hw
1288 .hw.init = &(struct clk_init_data){
1304 .hw.init = &(struct clk_init_data) {
1308 &g12a_cpu_clk_axi_div.hw
1325 .hw.init = &(struct clk_init_data){
1341 .hw.init = &(struct clk_init_data) {
1345 &g12a_cpu_clk_trace_div.hw
1358 .hw.init = &(struct clk_init_data){
1362 &g12b_cpub_clk.hw
1371 .hw.init = &(struct clk_init_data){
1375 &g12b_cpub_clk.hw
1384 .hw.init = &(struct clk_init_data){
1388 &g12b_cpub_clk.hw
1397 .hw.init = &(struct clk_init_data){
1401 &g12b_cpub_clk.hw
1410 .hw.init = &(struct clk_init_data){
1414 &g12b_cpub_clk.hw
1423 .hw.init = &(struct clk_init_data){
1427 &g12b_cpub_clk.hw
1436 .hw.init = &(struct clk_init_data){
1440 &g12b_cpub_clk.hw
1454 .hw.init = &(struct clk_init_data){
1458 &g12b_cpub_clk_div2.hw,
1459 &g12b_cpub_clk_div3.hw,
1460 &g12b_cpub_clk_div4.hw,
1461 &g12b_cpub_clk_div5.hw,
1462 &g12b_cpub_clk_div6.hw,
1463 &g12b_cpub_clk_div7.hw,
1464 &g12b_cpub_clk_div8.hw
1476 .hw.init = &(struct clk_init_data) {
1480 &g12b_cpub_clk_apb_sel.hw
1497 .hw.init = &(struct clk_init_data){
1501 &g12b_cpub_clk_div2.hw,
1502 &g12b_cpub_clk_div3.hw,
1503 &g12b_cpub_clk_div4.hw,
1504 &g12b_cpub_clk_div5.hw,
1505 &g12b_cpub_clk_div6.hw,
1506 &g12b_cpub_clk_div7.hw,
1507 &g12b_cpub_clk_div8.hw
1519 .hw.init = &(struct clk_init_data) {
1523 &g12b_cpub_clk_atb_sel.hw
1540 .hw.init = &(struct clk_init_data){
1544 &g12b_cpub_clk_div2.hw,
1545 &g12b_cpub_clk_div3.hw,
1546 &g12b_cpub_clk_div4.hw,
1547 &g12b_cpub_clk_div5.hw,
1548 &g12b_cpub_clk_div6.hw,
1549 &g12b_cpub_clk_div7.hw,
1550 &g12b_cpub_clk_div8.hw
1562 .hw.init = &(struct clk_init_data) {
1566 &g12b_cpub_clk_axi_sel.hw
1583 .hw.init = &(struct clk_init_data){
1587 &g12b_cpub_clk_div2.hw,
1588 &g12b_cpub_clk_div3.hw,
1589 &g12b_cpub_clk_div4.hw,
1590 &g12b_cpub_clk_div5.hw,
1591 &g12b_cpub_clk_div6.hw,
1592 &g12b_cpub_clk_div7.hw,
1593 &g12b_cpub_clk_div8.hw
1605 .hw.init = &(struct clk_init_data) {
1609 &g12b_cpub_clk_trace_sel.hw
1672 .hw.init = &(struct clk_init_data){
1690 .hw.init = &(struct clk_init_data){
1694 &g12a_gp0_pll_dco.hw
1734 .hw.init = &(struct clk_init_data){
1754 .hw.init = &(struct clk_init_data){
1758 &sm1_gp1_pll_dco.hw
1813 .hw.init = &(struct clk_init_data){
1831 .hw.init = &(struct clk_init_data){
1835 &g12a_hifi_pll_dco.hw
1904 .hw.init = &(struct clk_init_data){
1917 .hw.init = &(struct clk_init_data){
1921 &g12a_pcie_pll_dco.hw
1937 .hw.init = &(struct clk_init_data){
1941 &g12a_pcie_pll_dco_div2.hw
1951 .hw.init = &(struct clk_init_data){
1955 &g12a_pcie_pll_od.hw
1995 .hw.init = &(struct clk_init_data){
2017 .hw.init = &(struct clk_init_data){
2021 &g12a_hdmi_pll_dco.hw
2035 .hw.init = &(struct clk_init_data){
2039 &g12a_hdmi_pll_od.hw
2053 .hw.init = &(struct clk_init_data){
2057 &g12a_hdmi_pll_od2.hw
2067 .hw.init = &(struct clk_init_data){
2070 .parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },
2080 .hw.init = &(struct clk_init_data){
2084 &g12a_fclk_div4_div.hw
2093 .hw.init = &(struct clk_init_data){
2096 .parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },
2106 .hw.init = &(struct clk_init_data){
2110 &g12a_fclk_div5_div.hw
2119 .hw.init = &(struct clk_init_data){
2122 .parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },
2132 .hw.init = &(struct clk_init_data){
2136 &g12a_fclk_div7_div.hw
2145 .hw.init = &(struct clk_init_data){
2149 &g12a_fixed_pll_dco.hw
2160 .hw.init = &(struct clk_init_data){
2164 &g12a_fclk_div2p5_div.hw
2173 .hw.init = &(struct clk_init_data){
2177 &g12a_fixed_pll_dco.hw
2189 .hw.init = &(struct clk_init_data){
2194 { .hw = &g12a_mpll_50m_div.hw },
2203 .hw.init = &(struct clk_init_data){
2207 &g12a_fixed_pll_dco.hw
2243 .hw.init = &(struct clk_init_data){
2247 &g12a_mpll_prediv.hw
2258 .hw.init = &(struct clk_init_data){
2261 .parent_hws = (const struct clk_hw *[]) { &g12a_mpll0_div.hw },
2297 .hw.init = &(struct clk_init_data){
2301 &g12a_mpll_prediv.hw
2312 .hw.init = &(struct clk_init_data){
2315 .parent_hws = (const struct clk_hw *[]) { &g12a_mpll1_div.hw },
2351 .hw.init = &(struct clk_init_data){
2355 &g12a_mpll_prediv.hw
2366 .hw.init = &(struct clk_init_data){
2369 .parent_hws = (const struct clk_hw *[]) { &g12a_mpll2_div.hw },
2405 .hw.init = &(struct clk_init_data){
2409 &g12a_mpll_prediv.hw
2420 .hw.init = &(struct clk_init_data){
2423 .parent_hws = (const struct clk_hw *[]) { &g12a_mpll3_div.hw },
2432 { .hw = &g12a_fclk_div7.hw },
2433 { .hw = &g12a_mpll1.hw },
2434 { .hw = &g12a_mpll2.hw },
2435 { .hw = &g12a_fclk_div4.hw },
2436 { .hw = &g12a_fclk_div3.hw },
2437 { .hw = &g12a_fclk_div5.hw },
2447 .hw.init = &(struct clk_init_data){
2461 .hw.init = &(struct clk_init_data){
2465 &g12a_mpeg_clk_sel.hw
2477 .hw.init = &(struct clk_init_data){
2481 &g12a_mpeg_clk_div.hw
2490 { .hw = &g12a_fclk_div2.hw },
2491 { .hw = &g12a_fclk_div3.hw },
2492 { .hw = &g12a_fclk_div5.hw },
2493 { .hw = &g12a_fclk_div7.hw },
2509 .hw.init = &(struct clk_init_data) {
2524 .hw.init = &(struct clk_init_data) {
2528 &g12a_sd_emmc_a_clk0_sel.hw
2540 .hw.init = &(struct clk_init_data){
2544 &g12a_sd_emmc_a_clk0_div.hw
2558 .hw.init = &(struct clk_init_data) {
2573 .hw.init = &(struct clk_init_data) {
2577 &g12a_sd_emmc_b_clk0_sel.hw
2589 .hw.init = &(struct clk_init_data){
2593 &g12a_sd_emmc_b_clk0_div.hw
2607 .hw.init = &(struct clk_init_data) {
2622 .hw.init = &(struct clk_init_data) {
2626 &g12a_sd_emmc_c_clk0_sel.hw
2638 .hw.init = &(struct clk_init_data){
2642 &g12a_sd_emmc_c_clk0_div.hw
2664 .hw.init = &(struct clk_init_data) {
2667 .parent_hws = (const struct clk_hw *[]) { &g12a_hdmi_pll.hw },
2674 &g12a_vid_pll_div.hw,
2675 &g12a_hdmi_pll.hw,
2684 .hw.init = &(struct clk_init_data){
2702 .hw.init = &(struct clk_init_data) {
2706 &g12a_vid_pll_sel.hw
2716 &g12a_fclk_div3.hw,
2717 &g12a_fclk_div4.hw,
2718 &g12a_fclk_div5.hw,
2719 &g12a_fclk_div7.hw,
2720 &g12a_mpll1.hw,
2721 &g12a_vid_pll.hw,
2722 &g12a_hifi_pll.hw,
2723 &g12a_gp0_pll.hw,
2732 .hw.init = &(struct clk_init_data){
2747 .hw.init = &(struct clk_init_data){
2750 .parent_hws = (const struct clk_hw *[]) { &g12a_vpu_0_sel.hw },
2761 .hw.init = &(struct clk_init_data) {
2764 .parent_hws = (const struct clk_hw *[]) { &g12a_vpu_0_div.hw },
2776 .hw.init = &(struct clk_init_data){
2791 .hw.init = &(struct clk_init_data){
2794 .parent_hws = (const struct clk_hw *[]) { &g12a_vpu_1_sel.hw },
2805 .hw.init = &(struct clk_init_data) {
2808 .parent_hws = (const struct clk_hw *[]) { &g12a_vpu_1_div.hw },
2820 .hw.init = &(struct clk_init_data){
2828 &g12a_vpu_0.hw,
2829 &g12a_vpu_1.hw,
2839 &g12a_fclk_div2p5.hw,
2840 &g12a_fclk_div3.hw,
2841 &g12a_fclk_div4.hw,
2842 &g12a_fclk_div5.hw,
2843 &g12a_fclk_div7.hw,
2844 &g12a_hifi_pll.hw,
2845 &g12a_gp0_pll.hw,
2855 .hw.init = &(struct clk_init_data){
2871 .hw.init = &(struct clk_init_data){
2875 &g12a_vdec_1_sel.hw
2887 .hw.init = &(struct clk_init_data) {
2891 &g12a_vdec_1_div.hw
2905 .hw.init = &(struct clk_init_data){
2921 .hw.init = &(struct clk_init_data){
2925 &g12a_vdec_hevcf_sel.hw
2937 .hw.init = &(struct clk_init_data) {
2941 &g12a_vdec_hevcf_div.hw
2955 .hw.init = &(struct clk_init_data){
2971 .hw.init = &(struct clk_init_data){
2975 &g12a_vdec_hevc_sel.hw
2987 .hw.init = &(struct clk_init_data) {
2991 &g12a_vdec_hevc_div.hw
3001 &g12a_fclk_div4.hw,
3002 &g12a_fclk_div3.hw,
3003 &g12a_fclk_div5.hw,
3004 &g12a_fclk_div7.hw,
3005 &g12a_mpll1.hw,
3006 &g12a_vid_pll.hw,
3007 &g12a_mpll2.hw,
3008 &g12a_fclk_div2p5.hw,
3017 .hw.init = &(struct clk_init_data){
3032 .hw.init = &(struct clk_init_data){
3036 &g12a_vapb_0_sel.hw
3048 .hw.init = &(struct clk_init_data) {
3052 &g12a_vapb_0_div.hw
3065 .hw.init = &(struct clk_init_data){
3080 .hw.init = &(struct clk_init_data){
3084 &g12a_vapb_1_sel.hw
3096 .hw.init = &(struct clk_init_data) {
3100 &g12a_vapb_1_div.hw
3113 .hw.init = &(struct clk_init_data){
3121 &g12a_vapb_0.hw,
3122 &g12a_vapb_1.hw,
3134 .hw.init = &(struct clk_init_data) {
3137 .parent_hws = (const struct clk_hw *[]) { &g12a_vapb_sel.hw },
3144 &g12a_vid_pll.hw,
3145 &g12a_gp0_pll.hw,
3146 &g12a_hifi_pll.hw,
3147 &g12a_mpll1.hw,
3148 &g12a_fclk_div3.hw,
3149 &g12a_fclk_div4.hw,
3150 &g12a_fclk_div5.hw,
3151 &g12a_fclk_div7.hw,
3160 .hw.init = &(struct clk_init_data){
3175 .hw.init = &(struct clk_init_data){
3189 .hw.init = &(struct clk_init_data) {
3192 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk_sel.hw },
3203 .hw.init = &(struct clk_init_data) {
3206 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2_sel.hw },
3218 .hw.init = &(struct clk_init_data){
3222 &g12a_vclk_input.hw
3235 .hw.init = &(struct clk_init_data){
3239 &g12a_vclk2_input.hw
3251 .hw.init = &(struct clk_init_data) {
3254 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk_div.hw },
3265 .hw.init = &(struct clk_init_data) {
3268 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2_div.hw },
3279 .hw.init = &(struct clk_init_data) {
3282 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk.hw },
3293 .hw.init = &(struct clk_init_data) {
3296 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk.hw },
3307 .hw.init = &(struct clk_init_data) {
3310 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk.hw },
3321 .hw.init = &(struct clk_init_data) {
3324 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk.hw },
3335 .hw.init = &(struct clk_init_data) {
3338 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk.hw },
3349 .hw.init = &(struct clk_init_data) {
3352 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
3363 .hw.init = &(struct clk_init_data) {
3366 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
3377 .hw.init = &(struct clk_init_data) {
3380 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
3391 .hw.init = &(struct clk_init_data) {
3394 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
3405 .hw.init = &(struct clk_init_data) {
3408 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
3417 .hw.init = &(struct clk_init_data){
3421 &g12a_vclk_div2_en.hw
3430 .hw.init = &(struct clk_init_data){
3434 &g12a_vclk_div4_en.hw
3443 .hw.init = &(struct clk_init_data){
3447 &g12a_vclk_div6_en.hw
3456 .hw.init = &(struct clk_init_data){
3460 &g12a_vclk_div12_en.hw
3469 .hw.init = &(struct clk_init_data){
3473 &g12a_vclk2_div2_en.hw
3482 .hw.init = &(struct clk_init_data){
3486 &g12a_vclk2_div4_en.hw
3495 .hw.init = &(struct clk_init_data){
3499 &g12a_vclk2_div6_en.hw
3508 .hw.init = &(struct clk_init_data){
3512 &g12a_vclk2_div12_en.hw
3520 &g12a_vclk_div1.hw,
3521 &g12a_vclk_div2.hw,
3522 &g12a_vclk_div4.hw,
3523 &g12a_vclk_div6.hw,
3524 &g12a_vclk_div12.hw,
3525 &g12a_vclk2_div1.hw,
3526 &g12a_vclk2_div2.hw,
3527 &g12a_vclk2_div4.hw,
3528 &g12a_vclk2_div6.hw,
3529 &g12a_vclk2_div12.hw,
3539 .hw.init = &(struct clk_init_data){
3555 .hw.init = &(struct clk_init_data){
3571 .hw.init = &(struct clk_init_data){
3583 &g12a_vclk_div1.hw,
3584 &g12a_vclk_div2.hw,
3585 &g12a_vclk_div4.hw,
3586 &g12a_vclk_div6.hw,
3587 &g12a_vclk_div12.hw,
3588 &g12a_vclk2_div1.hw,
3589 &g12a_vclk2_div2.hw,
3590 &g12a_vclk2_div4.hw,
3591 &g12a_vclk2_div6.hw,
3592 &g12a_vclk2_div12.hw,
3602 .hw.init = &(struct clk_init_data){
3616 .hw.init = &(struct clk_init_data) {
3620 &g12a_cts_enci_sel.hw
3632 .hw.init = &(struct clk_init_data) {
3636 &g12a_cts_encp_sel.hw
3648 .hw.init = &(struct clk_init_data) {
3652 &g12a_cts_vdac_sel.hw
3664 .hw.init = &(struct clk_init_data) {
3668 &g12a_hdmi_tx_sel.hw
3678 &g12a_vid_pll.hw,
3679 &g12a_gp0_pll.hw,
3680 &g12a_hifi_pll.hw,
3681 &g12a_mpll1.hw,
3682 &g12a_fclk_div2.hw,
3683 &g12a_fclk_div2p5.hw,
3684 &g12a_fclk_div3.hw,
3685 &g12a_fclk_div7.hw,
3695 .hw.init = &(struct clk_init_data){
3710 .hw.init = &(struct clk_init_data){
3714 &g12a_mipi_dsi_pxclk_sel.hw
3726 .hw.init = &(struct clk_init_data) {
3730 &g12a_mipi_dsi_pxclk_div.hw
3741 { .hw = &g12a_fclk_div4.hw },
3742 { .hw = &g12a_fclk_div3.hw },
3743 { .hw = &g12a_fclk_div5.hw },
3753 .hw.init = &(struct clk_init_data){
3768 .hw.init = &(struct clk_init_data){
3771 .parent_hws = (const struct clk_hw *[]) { &g12a_hdmi_sel.hw },
3782 .hw.init = &(struct clk_init_data) {
3785 .parent_hws = (const struct clk_hw *[]) { &g12a_hdmi_div.hw },
3799 { .hw = &g12a_gp0_pll.hw },
3800 { .hw = &g12a_hifi_pll.hw },
3801 { .hw = &g12a_fclk_div2p5.hw },
3802 { .hw = &g12a_fclk_div3.hw },
3803 { .hw = &g12a_fclk_div4.hw },
3804 { .hw = &g12a_fclk_div5.hw },
3805 { .hw = &g12a_fclk_div7.hw },
3814 .hw.init = &(struct clk_init_data){
3835 .hw.init = &(struct clk_init_data){
3839 &g12a_mali_0_sel.hw
3851 .hw.init = &(struct clk_init_data){
3855 &g12a_mali_0_div.hw
3868 .hw.init = &(struct clk_init_data){
3889 .hw.init = &(struct clk_init_data){
3893 &g12a_mali_1_sel.hw
3905 .hw.init = &(struct clk_init_data){
3909 &g12a_mali_1_div.hw
3917 &g12a_mali_0.hw,
3918 &g12a_mali_1.hw,
3927 .hw.init = &(struct clk_init_data){
3942 .hw.init = &(struct clk_init_data){
3957 .hw.init = &(struct clk_init_data){
3961 &g12a_ts_div.hw
3971 { .hw = &g12a_clk81.hw },
3972 { .hw = &g12a_fclk_div4.hw },
3973 { .hw = &g12a_fclk_div3.hw },
3974 { .hw = &g12a_fclk_div2.hw },
3975 { .hw = &g12a_fclk_div5.hw },
3976 { .hw = &g12a_fclk_div7.hw },
3985 .hw.init = &(struct clk_init_data){
3999 .hw.init = &(struct clk_init_data){
4003 &g12a_spicc0_sclk_sel.hw
4015 .hw.init = &(struct clk_init_data){
4019 &g12a_spicc0_sclk_div.hw
4032 .hw.init = &(struct clk_init_data){
4046 .hw.init = &(struct clk_init_data){
4050 &g12a_spicc1_sclk_sel.hw
4062 .hw.init = &(struct clk_init_data){
4066 &g12a_spicc1_sclk_div.hw
4077 { .hw = &g12a_gp0_pll.hw, },
4078 { .hw = &g12a_hifi_pll.hw, },
4079 { .hw = &g12a_fclk_div2p5.hw, },
4080 { .hw = &g12a_fclk_div3.hw, },
4081 { .hw = &g12a_fclk_div4.hw, },
4082 { .hw = &g12a_fclk_div5.hw, },
4083 { .hw = &g12a_fclk_div7.hw },
4092 .hw.init = &(struct clk_init_data){
4106 .hw.init = &(struct clk_init_data){
4110 &sm1_nna_axi_clk_sel.hw
4122 .hw.init = &(struct clk_init_data){
4126 &sm1_nna_axi_clk_div.hw
4139 .hw.init = &(struct clk_init_data){
4153 .hw.init = &(struct clk_init_data){
4157 &sm1_nna_core_clk_sel.hw
4169 .hw.init = &(struct clk_init_data){
4173 &sm1_nna_core_clk_div.hw
4181 MESON_PCLK(_name, _reg, _bit, &g12a_clk81.hw)
4184 MESON_PCLK_RO(_name, _reg, _bit, &g12a_clk81.hw)
4263 [CLKID_SYS_PLL] = &g12a_sys_pll.hw,
4264 [CLKID_FIXED_PLL] = &g12a_fixed_pll.hw,
4265 [CLKID_FCLK_DIV2] = &g12a_fclk_div2.hw,
4266 [CLKID_FCLK_DIV3] = &g12a_fclk_div3.hw,
4267 [CLKID_FCLK_DIV4] = &g12a_fclk_div4.hw,
4268 [CLKID_FCLK_DIV5] = &g12a_fclk_div5.hw,
4269 [CLKID_FCLK_DIV7] = &g12a_fclk_div7.hw,
4270 [CLKID_FCLK_DIV2P5] = &g12a_fclk_div2p5.hw,
4271 [CLKID_GP0_PLL] = &g12a_gp0_pll.hw,
4272 [CLKID_MPEG_SEL] = &g12a_mpeg_clk_sel.hw,
4273 [CLKID_MPEG_DIV] = &g12a_mpeg_clk_div.hw,
4274 [CLKID_CLK81] = &g12a_clk81.hw,
4275 [CLKID_MPLL0] = &g12a_mpll0.hw,
4276 [CLKID_MPLL1] = &g12a_mpll1.hw,
4277 [CLKID_MPLL2] = &g12a_mpll2.hw,
4278 [CLKID_MPLL3] = &g12a_mpll3.hw,
4279 [CLKID_DDR] = &g12a_ddr.hw,
4280 [CLKID_DOS] = &g12a_dos.hw,
4281 [CLKID_AUDIO_LOCKER] = &g12a_audio_locker.hw,
4282 [CLKID_MIPI_DSI_HOST] = &g12a_mipi_dsi_host.hw,
4283 [CLKID_ETH_PHY] = &g12a_eth_phy.hw,
4284 [CLKID_ISA] = &g12a_isa.hw,
4285 [CLKID_PL301] = &g12a_pl301.hw,
4286 [CLKID_PERIPHS] = &g12a_periphs.hw,
4287 [CLKID_SPICC0] = &g12a_spicc_0.hw,
4288 [CLKID_I2C] = &g12a_i2c.hw,
4289 [CLKID_SANA] = &g12a_sana.hw,
4290 [CLKID_SD] = &g12a_sd.hw,
4291 [CLKID_RNG0] = &g12a_rng0.hw,
4292 [CLKID_UART0] = &g12a_uart0.hw,
4293 [CLKID_SPICC1] = &g12a_spicc_1.hw,
4294 [CLKID_HIU_IFACE] = &g12a_hiu_reg.hw,
4295 [CLKID_MIPI_DSI_PHY] = &g12a_mipi_dsi_phy.hw,
4296 [CLKID_ASSIST_MISC] = &g12a_assist_misc.hw,
4297 [CLKID_SD_EMMC_A] = &g12a_emmc_a.hw,
4298 [CLKID_SD_EMMC_B] = &g12a_emmc_b.hw,
4299 [CLKID_SD_EMMC_C] = &g12a_emmc_c.hw,
4300 [CLKID_AUDIO_CODEC] = &g12a_audio_codec.hw,
4301 [CLKID_AUDIO] = &g12a_audio.hw,
4302 [CLKID_ETH] = &g12a_eth_core.hw,
4303 [CLKID_DEMUX] = &g12a_demux.hw,
4304 [CLKID_AUDIO_IFIFO] = &g12a_audio_ififo.hw,
4305 [CLKID_ADC] = &g12a_adc.hw,
4306 [CLKID_UART1] = &g12a_uart1.hw,
4307 [CLKID_G2D] = &g12a_g2d.hw,
4308 [CLKID_RESET] = &g12a_reset.hw,
4309 [CLKID_PCIE_COMB] = &g12a_pcie_comb.hw,
4310 [CLKID_PARSER] = &g12a_parser.hw,
4311 [CLKID_USB] = &g12a_usb_general.hw,
4312 [CLKID_PCIE_PHY] = &g12a_pcie_phy.hw,
4313 [CLKID_AHB_ARB0] = &g12a_ahb_arb0.hw,
4314 [CLKID_AHB_DATA_BUS] = &g12a_ahb_data_bus.hw,
4315 [CLKID_AHB_CTRL_BUS] = &g12a_ahb_ctrl_bus.hw,
4316 [CLKID_HTX_HDCP22] = &g12a_htx_hdcp22.hw,
4317 [CLKID_HTX_PCLK] = &g12a_htx_pclk.hw,
4318 [CLKID_BT656] = &g12a_bt656.hw,
4319 [CLKID_USB1_DDR_BRIDGE] = &g12a_usb1_to_ddr.hw,
4320 [CLKID_MMC_PCLK] = &g12a_mmc_pclk.hw,
4321 [CLKID_UART2] = &g12a_uart2.hw,
4322 [CLKID_VPU_INTR] = &g12a_vpu_intr.hw,
4323 [CLKID_GIC] = &g12a_gic.hw,
4324 [CLKID_SD_EMMC_A_CLK0_SEL] = &g12a_sd_emmc_a_clk0_sel.hw,
4325 [CLKID_SD_EMMC_A_CLK0_DIV] = &g12a_sd_emmc_a_clk0_div.hw,
4326 [CLKID_SD_EMMC_A_CLK0] = &g12a_sd_emmc_a_clk0.hw,
4327 [CLKID_SD_EMMC_B_CLK0_SEL] = &g12a_sd_emmc_b_clk0_sel.hw,
4328 [CLKID_SD_EMMC_B_CLK0_DIV] = &g12a_sd_emmc_b_clk0_div.hw,
4329 [CLKID_SD_EMMC_B_CLK0] = &g12a_sd_emmc_b_clk0.hw,
4330 [CLKID_SD_EMMC_C_CLK0_SEL] = &g12a_sd_emmc_c_clk0_sel.hw,
4331 [CLKID_SD_EMMC_C_CLK0_DIV] = &g12a_sd_emmc_c_clk0_div.hw,
4332 [CLKID_SD_EMMC_C_CLK0] = &g12a_sd_emmc_c_clk0.hw,
4333 [CLKID_MPLL0_DIV] = &g12a_mpll0_div.hw,
4334 [CLKID_MPLL1_DIV] = &g12a_mpll1_div.hw,
4335 [CLKID_MPLL2_DIV] = &g12a_mpll2_div.hw,
4336 [CLKID_MPLL3_DIV] = &g12a_mpll3_div.hw,
4337 [CLKID_FCLK_DIV2_DIV] = &g12a_fclk_div2_div.hw,
4338 [CLKID_FCLK_DIV3_DIV] = &g12a_fclk_div3_div.hw,
4339 [CLKID_FCLK_DIV4_DIV] = &g12a_fclk_div4_div.hw,
4340 [CLKID_FCLK_DIV5_DIV] = &g12a_fclk_div5_div.hw,
4341 [CLKID_FCLK_DIV7_DIV] = &g12a_fclk_div7_div.hw,
4342 [CLKID_FCLK_DIV2P5_DIV] = &g12a_fclk_div2p5_div.hw,
4343 [CLKID_HIFI_PLL] = &g12a_hifi_pll.hw,
4344 [CLKID_VCLK2_VENCI0] = &g12a_vclk2_venci0.hw,
4345 [CLKID_VCLK2_VENCI1] = &g12a_vclk2_venci1.hw,
4346 [CLKID_VCLK2_VENCP0] = &g12a_vclk2_vencp0.hw,
4347 [CLKID_VCLK2_VENCP1] = &g12a_vclk2_vencp1.hw,
4348 [CLKID_VCLK2_VENCT0] = &g12a_vclk2_venct0.hw,
4349 [CLKID_VCLK2_VENCT1] = &g12a_vclk2_venct1.hw,
4350 [CLKID_VCLK2_OTHER] = &g12a_vclk2_other.hw,
4351 [CLKID_VCLK2_ENCI] = &g12a_vclk2_enci.hw,
4352 [CLKID_VCLK2_ENCP] = &g12a_vclk2_encp.hw,
4353 [CLKID_DAC_CLK] = &g12a_dac_clk.hw,
4354 [CLKID_AOCLK] = &g12a_aoclk_gate.hw,
4355 [CLKID_IEC958] = &g12a_iec958_gate.hw,
4356 [CLKID_ENC480P] = &g12a_enc480p.hw,
4357 [CLKID_RNG1] = &g12a_rng1.hw,
4358 [CLKID_VCLK2_ENCT] = &g12a_vclk2_enct.hw,
4359 [CLKID_VCLK2_ENCL] = &g12a_vclk2_encl.hw,
4360 [CLKID_VCLK2_VENCLMMC] = &g12a_vclk2_venclmmc.hw,
4361 [CLKID_VCLK2_VENCL] = &g12a_vclk2_vencl.hw,
4362 [CLKID_VCLK2_OTHER1] = &g12a_vclk2_other1.hw,
4363 [CLKID_FIXED_PLL_DCO] = &g12a_fixed_pll_dco.hw,
4364 [CLKID_SYS_PLL_DCO] = &g12a_sys_pll_dco.hw,
4365 [CLKID_GP0_PLL_DCO] = &g12a_gp0_pll_dco.hw,
4366 [CLKID_HIFI_PLL_DCO] = &g12a_hifi_pll_dco.hw,
4367 [CLKID_DMA] = &g12a_dma.hw,
4368 [CLKID_EFUSE] = &g12a_efuse.hw,
4369 [CLKID_ROM_BOOT] = &g12a_rom_boot.hw,
4370 [CLKID_RESET_SEC] = &g12a_reset_sec.hw,
4371 [CLKID_SEC_AHB_APB3] = &g12a_sec_ahb_apb3.hw,
4372 [CLKID_MPLL_PREDIV] = &g12a_mpll_prediv.hw,
4373 [CLKID_VPU_0_SEL] = &g12a_vpu_0_sel.hw,
4374 [CLKID_VPU_0_DIV] = &g12a_vpu_0_div.hw,
4375 [CLKID_VPU_0] = &g12a_vpu_0.hw,
4376 [CLKID_VPU_1_SEL] = &g12a_vpu_1_sel.hw,
4377 [CLKID_VPU_1_DIV] = &g12a_vpu_1_div.hw,
4378 [CLKID_VPU_1] = &g12a_vpu_1.hw,
4379 [CLKID_VPU] = &g12a_vpu.hw,
4380 [CLKID_VAPB_0_SEL] = &g12a_vapb_0_sel.hw,
4381 [CLKID_VAPB_0_DIV] = &g12a_vapb_0_div.hw,
4382 [CLKID_VAPB_0] = &g12a_vapb_0.hw,
4383 [CLKID_VAPB_1_SEL] = &g12a_vapb_1_sel.hw,
4384 [CLKID_VAPB_1_DIV] = &g12a_vapb_1_div.hw,
4385 [CLKID_VAPB_1] = &g12a_vapb_1.hw,
4386 [CLKID_VAPB_SEL] = &g12a_vapb_sel.hw,
4387 [CLKID_VAPB] = &g12a_vapb.hw,
4388 [CLKID_HDMI_PLL_DCO] = &g12a_hdmi_pll_dco.hw,
4389 [CLKID_HDMI_PLL_OD] = &g12a_hdmi_pll_od.hw,
4390 [CLKID_HDMI_PLL_OD2] = &g12a_hdmi_pll_od2.hw,
4391 [CLKID_HDMI_PLL] = &g12a_hdmi_pll.hw,
4392 [CLKID_VID_PLL] = &g12a_vid_pll_div.hw,
4393 [CLKID_VID_PLL_SEL] = &g12a_vid_pll_sel.hw,
4394 [CLKID_VID_PLL_DIV] = &g12a_vid_pll.hw,
4395 [CLKID_VCLK_SEL] = &g12a_vclk_sel.hw,
4396 [CLKID_VCLK2_SEL] = &g12a_vclk2_sel.hw,
4397 [CLKID_VCLK_INPUT] = &g12a_vclk_input.hw,
4398 [CLKID_VCLK2_INPUT] = &g12a_vclk2_input.hw,
4399 [CLKID_VCLK_DIV] = &g12a_vclk_div.hw,
4400 [CLKID_VCLK2_DIV] = &g12a_vclk2_div.hw,
4401 [CLKID_VCLK] = &g12a_vclk.hw,
4402 [CLKID_VCLK2] = &g12a_vclk2.hw,
4403 [CLKID_VCLK_DIV1] = &g12a_vclk_div1.hw,
4404 [CLKID_VCLK_DIV2_EN] = &g12a_vclk_div2_en.hw,
4405 [CLKID_VCLK_DIV4_EN] = &g12a_vclk_div4_en.hw,
4406 [CLKID_VCLK_DIV6_EN] = &g12a_vclk_div6_en.hw,
4407 [CLKID_VCLK_DIV12_EN] = &g12a_vclk_div12_en.hw,
4408 [CLKID_VCLK2_DIV1] = &g12a_vclk2_div1.hw,
4409 [CLKID_VCLK2_DIV2_EN] = &g12a_vclk2_div2_en.hw,
4410 [CLKID_VCLK2_DIV4_EN] = &g12a_vclk2_div4_en.hw,
4411 [CLKID_VCLK2_DIV6_EN] = &g12a_vclk2_div6_en.hw,
4412 [CLKID_VCLK2_DIV12_EN] = &g12a_vclk2_div12_en.hw,
4413 [CLKID_VCLK_DIV2] = &g12a_vclk_div2.hw,
4414 [CLKID_VCLK_DIV4] = &g12a_vclk_div4.hw,
4415 [CLKID_VCLK_DIV6] = &g12a_vclk_div6.hw,
4416 [CLKID_VCLK_DIV12] = &g12a_vclk_div12.hw,
4417 [CLKID_VCLK2_DIV2] = &g12a_vclk2_div2.hw,
4418 [CLKID_VCLK2_DIV4] = &g12a_vclk2_div4.hw,
4419 [CLKID_VCLK2_DIV6] = &g12a_vclk2_div6.hw,
4420 [CLKID_VCLK2_DIV12] = &g12a_vclk2_div12.hw,
4421 [CLKID_CTS_ENCI_SEL] = &g12a_cts_enci_sel.hw,
4422 [CLKID_CTS_ENCP_SEL] = &g12a_cts_encp_sel.hw,
4423 [CLKID_CTS_VDAC_SEL] = &g12a_cts_vdac_sel.hw,
4424 [CLKID_HDMI_TX_SEL] = &g12a_hdmi_tx_sel.hw,
4425 [CLKID_CTS_ENCI] = &g12a_cts_enci.hw,
4426 [CLKID_CTS_ENCP] = &g12a_cts_encp.hw,
4427 [CLKID_CTS_VDAC] = &g12a_cts_vdac.hw,
4428 [CLKID_HDMI_TX] = &g12a_hdmi_tx.hw,
4429 [CLKID_HDMI_SEL] = &g12a_hdmi_sel.hw,
4430 [CLKID_HDMI_DIV] = &g12a_hdmi_div.hw,
4431 [CLKID_HDMI] = &g12a_hdmi.hw,
4432 [CLKID_MALI_0_SEL] = &g12a_mali_0_sel.hw,
4433 [CLKID_MALI_0_DIV] = &g12a_mali_0_div.hw,
4434 [CLKID_MALI_0] = &g12a_mali_0.hw,
4435 [CLKID_MALI_1_SEL] = &g12a_mali_1_sel.hw,
4436 [CLKID_MALI_1_DIV] = &g12a_mali_1_div.hw,
4437 [CLKID_MALI_1] = &g12a_mali_1.hw,
4438 [CLKID_MALI] = &g12a_mali.hw,
4439 [CLKID_MPLL_50M_DIV] = &g12a_mpll_50m_div.hw,
4440 [CLKID_MPLL_50M] = &g12a_mpll_50m.hw,
4441 [CLKID_SYS_PLL_DIV16_EN] = &g12a_sys_pll_div16_en.hw,
4442 [CLKID_SYS_PLL_DIV16] = &g12a_sys_pll_div16.hw,
4443 [CLKID_CPU_CLK_DYN0_SEL] = &g12a_cpu_clk_premux0.hw,
4444 [CLKID_CPU_CLK_DYN0_DIV] = &g12a_cpu_clk_mux0_div.hw,
4445 [CLKID_CPU_CLK_DYN0] = &g12a_cpu_clk_postmux0.hw,
4446 [CLKID_CPU_CLK_DYN1_SEL] = &g12a_cpu_clk_premux1.hw,
4447 [CLKID_CPU_CLK_DYN1_DIV] = &g12a_cpu_clk_mux1_div.hw,
4448 [CLKID_CPU_CLK_DYN1] = &g12a_cpu_clk_postmux1.hw,
4449 [CLKID_CPU_CLK_DYN] = &g12a_cpu_clk_dyn.hw,
4450 [CLKID_CPU_CLK] = &g12a_cpu_clk.hw,
4451 [CLKID_CPU_CLK_DIV16_EN] = &g12a_cpu_clk_div16_en.hw,
4452 [CLKID_CPU_CLK_DIV16] = &g12a_cpu_clk_div16.hw,
4453 [CLKID_CPU_CLK_APB_DIV] = &g12a_cpu_clk_apb_div.hw,
4454 [CLKID_CPU_CLK_APB] = &g12a_cpu_clk_apb.hw,
4455 [CLKID_CPU_CLK_ATB_DIV] = &g12a_cpu_clk_atb_div.hw,
4456 [CLKID_CPU_CLK_ATB] = &g12a_cpu_clk_atb.hw,
4457 [CLKID_CPU_CLK_AXI_DIV] = &g12a_cpu_clk_axi_div.hw,
4458 [CLKID_CPU_CLK_AXI] = &g12a_cpu_clk_axi.hw,
4459 [CLKID_CPU_CLK_TRACE_DIV] = &g12a_cpu_clk_trace_div.hw,
4460 [CLKID_CPU_CLK_TRACE] = &g12a_cpu_clk_trace.hw,
4461 [CLKID_PCIE_PLL_DCO] = &g12a_pcie_pll_dco.hw,
4462 [CLKID_PCIE_PLL_DCO_DIV2] = &g12a_pcie_pll_dco_div2.hw,
4463 [CLKID_PCIE_PLL_OD] = &g12a_pcie_pll_od.hw,
4464 [CLKID_PCIE_PLL] = &g12a_pcie_pll.hw,
4465 [CLKID_VDEC_1_SEL] = &g12a_vdec_1_sel.hw,
4466 [CLKID_VDEC_1_DIV] = &g12a_vdec_1_div.hw,
4467 [CLKID_VDEC_1] = &g12a_vdec_1.hw,
4468 [CLKID_VDEC_HEVC_SEL] = &g12a_vdec_hevc_sel.hw,
4469 [CLKID_VDEC_HEVC_DIV] = &g12a_vdec_hevc_div.hw,
4470 [CLKID_VDEC_HEVC] = &g12a_vdec_hevc.hw,
4471 [CLKID_VDEC_HEVCF_SEL] = &g12a_vdec_hevcf_sel.hw,
4472 [CLKID_VDEC_HEVCF_DIV] = &g12a_vdec_hevcf_div.hw,
4473 [CLKID_VDEC_HEVCF] = &g12a_vdec_hevcf.hw,
4474 [CLKID_TS_DIV] = &g12a_ts_div.hw,
4475 [CLKID_TS] = &g12a_ts.hw,
4476 [CLKID_SPICC0_SCLK_SEL] = &g12a_spicc0_sclk_sel.hw,
4477 [CLKID_SPICC0_SCLK_DIV] = &g12a_spicc0_sclk_div.hw,
4478 [CLKID_SPICC0_SCLK] = &g12a_spicc0_sclk.hw,
4479 [CLKID_SPICC1_SCLK_SEL] = &g12a_spicc1_sclk_sel.hw,
4480 [CLKID_SPICC1_SCLK_DIV] = &g12a_spicc1_sclk_div.hw,
4481 [CLKID_SPICC1_SCLK] = &g12a_spicc1_sclk.hw,
4482 [CLKID_MIPI_DSI_PXCLK_SEL] = &g12a_mipi_dsi_pxclk_sel.hw,
4483 [CLKID_MIPI_DSI_PXCLK_DIV] = &g12a_mipi_dsi_pxclk_div.hw,
4484 [CLKID_MIPI_DSI_PXCLK] = &g12a_mipi_dsi_pxclk.hw,
4488 [CLKID_SYS_PLL] = &g12a_sys_pll.hw,
4489 [CLKID_FIXED_PLL] = &g12a_fixed_pll.hw,
4490 [CLKID_FCLK_DIV2] = &g12a_fclk_div2.hw,
4491 [CLKID_FCLK_DIV3] = &g12a_fclk_div3.hw,
4492 [CLKID_FCLK_DIV4] = &g12a_fclk_div4.hw,
4493 [CLKID_FCLK_DIV5] = &g12a_fclk_div5.hw,
4494 [CLKID_FCLK_DIV7] = &g12a_fclk_div7.hw,
4495 [CLKID_FCLK_DIV2P5] = &g12a_fclk_div2p5.hw,
4496 [CLKID_GP0_PLL] = &g12a_gp0_pll.hw,
4497 [CLKID_MPEG_SEL] = &g12a_mpeg_clk_sel.hw,
4498 [CLKID_MPEG_DIV] = &g12a_mpeg_clk_div.hw,
4499 [CLKID_CLK81] = &g12a_clk81.hw,
4500 [CLKID_MPLL0] = &g12a_mpll0.hw,
4501 [CLKID_MPLL1] = &g12a_mpll1.hw,
4502 [CLKID_MPLL2] = &g12a_mpll2.hw,
4503 [CLKID_MPLL3] = &g12a_mpll3.hw,
4504 [CLKID_DDR] = &g12a_ddr.hw,
4505 [CLKID_DOS] = &g12a_dos.hw,
4506 [CLKID_AUDIO_LOCKER] = &g12a_audio_locker.hw,
4507 [CLKID_MIPI_DSI_HOST] = &g12a_mipi_dsi_host.hw,
4508 [CLKID_ETH_PHY] = &g12a_eth_phy.hw,
4509 [CLKID_ISA] = &g12a_isa.hw,
4510 [CLKID_PL301] = &g12a_pl301.hw,
4511 [CLKID_PERIPHS] = &g12a_periphs.hw,
4512 [CLKID_SPICC0] = &g12a_spicc_0.hw,
4513 [CLKID_I2C] = &g12a_i2c.hw,
4514 [CLKID_SANA] = &g12a_sana.hw,
4515 [CLKID_SD] = &g12a_sd.hw,
4516 [CLKID_RNG0] = &g12a_rng0.hw,
4517 [CLKID_UART0] = &g12a_uart0.hw,
4518 [CLKID_SPICC1] = &g12a_spicc_1.hw,
4519 [CLKID_HIU_IFACE] = &g12a_hiu_reg.hw,
4520 [CLKID_MIPI_DSI_PHY] = &g12a_mipi_dsi_phy.hw,
4521 [CLKID_ASSIST_MISC] = &g12a_assist_misc.hw,
4522 [CLKID_SD_EMMC_A] = &g12a_emmc_a.hw,
4523 [CLKID_SD_EMMC_B] = &g12a_emmc_b.hw,
4524 [CLKID_SD_EMMC_C] = &g12a_emmc_c.hw,
4525 [CLKID_AUDIO_CODEC] = &g12a_audio_codec.hw,
4526 [CLKID_AUDIO] = &g12a_audio.hw,
4527 [CLKID_ETH] = &g12a_eth_core.hw,
4528 [CLKID_DEMUX] = &g12a_demux.hw,
4529 [CLKID_AUDIO_IFIFO] = &g12a_audio_ififo.hw,
4530 [CLKID_ADC] = &g12a_adc.hw,
4531 [CLKID_UART1] = &g12a_uart1.hw,
4532 [CLKID_G2D] = &g12a_g2d.hw,
4533 [CLKID_RESET] = &g12a_reset.hw,
4534 [CLKID_PCIE_COMB] = &g12a_pcie_comb.hw,
4535 [CLKID_PARSER] = &g12a_parser.hw,
4536 [CLKID_USB] = &g12a_usb_general.hw,
4537 [CLKID_PCIE_PHY] = &g12a_pcie_phy.hw,
4538 [CLKID_AHB_ARB0] = &g12a_ahb_arb0.hw,
4539 [CLKID_AHB_DATA_BUS] = &g12a_ahb_data_bus.hw,
4540 [CLKID_AHB_CTRL_BUS] = &g12a_ahb_ctrl_bus.hw,
4541 [CLKID_HTX_HDCP22] = &g12a_htx_hdcp22.hw,
4542 [CLKID_HTX_PCLK] = &g12a_htx_pclk.hw,
4543 [CLKID_BT656] = &g12a_bt656.hw,
4544 [CLKID_USB1_DDR_BRIDGE] = &g12a_usb1_to_ddr.hw,
4545 [CLKID_MMC_PCLK] = &g12a_mmc_pclk.hw,
4546 [CLKID_UART2] = &g12a_uart2.hw,
4547 [CLKID_VPU_INTR] = &g12a_vpu_intr.hw,
4548 [CLKID_GIC] = &g12a_gic.hw,
4549 [CLKID_SD_EMMC_A_CLK0_SEL] = &g12a_sd_emmc_a_clk0_sel.hw,
4550 [CLKID_SD_EMMC_A_CLK0_DIV] = &g12a_sd_emmc_a_clk0_div.hw,
4551 [CLKID_SD_EMMC_A_CLK0] = &g12a_sd_emmc_a_clk0.hw,
4552 [CLKID_SD_EMMC_B_CLK0_SEL] = &g12a_sd_emmc_b_clk0_sel.hw,
4553 [CLKID_SD_EMMC_B_CLK0_DIV] = &g12a_sd_emmc_b_clk0_div.hw,
4554 [CLKID_SD_EMMC_B_CLK0] = &g12a_sd_emmc_b_clk0.hw,
4555 [CLKID_SD_EMMC_C_CLK0_SEL] = &g12a_sd_emmc_c_clk0_sel.hw,
4556 [CLKID_SD_EMMC_C_CLK0_DIV] = &g12a_sd_emmc_c_clk0_div.hw,
4557 [CLKID_SD_EMMC_C_CLK0] = &g12a_sd_emmc_c_clk0.hw,
4558 [CLKID_MPLL0_DIV] = &g12a_mpll0_div.hw,
4559 [CLKID_MPLL1_DIV] = &g12a_mpll1_div.hw,
4560 [CLKID_MPLL2_DIV] = &g12a_mpll2_div.hw,
4561 [CLKID_MPLL3_DIV] = &g12a_mpll3_div.hw,
4562 [CLKID_FCLK_DIV2_DIV] = &g12a_fclk_div2_div.hw,
4563 [CLKID_FCLK_DIV3_DIV] = &g12a_fclk_div3_div.hw,
4564 [CLKID_FCLK_DIV4_DIV] = &g12a_fclk_div4_div.hw,
4565 [CLKID_FCLK_DIV5_DIV] = &g12a_fclk_div5_div.hw,
4566 [CLKID_FCLK_DIV7_DIV] = &g12a_fclk_div7_div.hw,
4567 [CLKID_FCLK_DIV2P5_DIV] = &g12a_fclk_div2p5_div.hw,
4568 [CLKID_HIFI_PLL] = &g12a_hifi_pll.hw,
4569 [CLKID_VCLK2_VENCI0] = &g12a_vclk2_venci0.hw,
4570 [CLKID_VCLK2_VENCI1] = &g12a_vclk2_venci1.hw,
4571 [CLKID_VCLK2_VENCP0] = &g12a_vclk2_vencp0.hw,
4572 [CLKID_VCLK2_VENCP1] = &g12a_vclk2_vencp1.hw,
4573 [CLKID_VCLK2_VENCT0] = &g12a_vclk2_venct0.hw,
4574 [CLKID_VCLK2_VENCT1] = &g12a_vclk2_venct1.hw,
4575 [CLKID_VCLK2_OTHER] = &g12a_vclk2_other.hw,
4576 [CLKID_VCLK2_ENCI] = &g12a_vclk2_enci.hw,
4577 [CLKID_VCLK2_ENCP] = &g12a_vclk2_encp.hw,
4578 [CLKID_DAC_CLK] = &g12a_dac_clk.hw,
4579 [CLKID_AOCLK] = &g12a_aoclk_gate.hw,
4580 [CLKID_IEC958] = &g12a_iec958_gate.hw,
4581 [CLKID_ENC480P] = &g12a_enc480p.hw,
4582 [CLKID_RNG1] = &g12a_rng1.hw,
4583 [CLKID_VCLK2_ENCT] = &g12a_vclk2_enct.hw,
4584 [CLKID_VCLK2_ENCL] = &g12a_vclk2_encl.hw,
4585 [CLKID_VCLK2_VENCLMMC] = &g12a_vclk2_venclmmc.hw,
4586 [CLKID_VCLK2_VENCL] = &g12a_vclk2_vencl.hw,
4587 [CLKID_VCLK2_OTHER1] = &g12a_vclk2_other1.hw,
4588 [CLKID_FIXED_PLL_DCO] = &g12a_fixed_pll_dco.hw,
4589 [CLKID_SYS_PLL_DCO] = &g12a_sys_pll_dco.hw,
4590 [CLKID_GP0_PLL_DCO] = &g12a_gp0_pll_dco.hw,
4591 [CLKID_HIFI_PLL_DCO] = &g12a_hifi_pll_dco.hw,
4592 [CLKID_DMA] = &g12a_dma.hw,
4593 [CLKID_EFUSE] = &g12a_efuse.hw,
4594 [CLKID_ROM_BOOT] = &g12a_rom_boot.hw,
4595 [CLKID_RESET_SEC] = &g12a_reset_sec.hw,
4596 [CLKID_SEC_AHB_APB3] = &g12a_sec_ahb_apb3.hw,
4597 [CLKID_MPLL_PREDIV] = &g12a_mpll_prediv.hw,
4598 [CLKID_VPU_0_SEL] = &g12a_vpu_0_sel.hw,
4599 [CLKID_VPU_0_DIV] = &g12a_vpu_0_div.hw,
4600 [CLKID_VPU_0] = &g12a_vpu_0.hw,
4601 [CLKID_VPU_1_SEL] = &g12a_vpu_1_sel.hw,
4602 [CLKID_VPU_1_DIV] = &g12a_vpu_1_div.hw,
4603 [CLKID_VPU_1] = &g12a_vpu_1.hw,
4604 [CLKID_VPU] = &g12a_vpu.hw,
4605 [CLKID_VAPB_0_SEL] = &g12a_vapb_0_sel.hw,
4606 [CLKID_VAPB_0_DIV] = &g12a_vapb_0_div.hw,
4607 [CLKID_VAPB_0] = &g12a_vapb_0.hw,
4608 [CLKID_VAPB_1_SEL] = &g12a_vapb_1_sel.hw,
4609 [CLKID_VAPB_1_DIV] = &g12a_vapb_1_div.hw,
4610 [CLKID_VAPB_1] = &g12a_vapb_1.hw,
4611 [CLKID_VAPB_SEL] = &g12a_vapb_sel.hw,
4612 [CLKID_VAPB] = &g12a_vapb.hw,
4613 [CLKID_HDMI_PLL_DCO] = &g12a_hdmi_pll_dco.hw,
4614 [CLKID_HDMI_PLL_OD] = &g12a_hdmi_pll_od.hw,
4615 [CLKID_HDMI_PLL_OD2] = &g12a_hdmi_pll_od2.hw,
4616 [CLKID_HDMI_PLL] = &g12a_hdmi_pll.hw,
4617 [CLKID_VID_PLL] = &g12a_vid_pll_div.hw,
4618 [CLKID_VID_PLL_SEL] = &g12a_vid_pll_sel.hw,
4619 [CLKID_VID_PLL_DIV] = &g12a_vid_pll.hw,
4620 [CLKID_VCLK_SEL] = &g12a_vclk_sel.hw,
4621 [CLKID_VCLK2_SEL] = &g12a_vclk2_sel.hw,
4622 [CLKID_VCLK_INPUT] = &g12a_vclk_input.hw,
4623 [CLKID_VCLK2_INPUT] = &g12a_vclk2_input.hw,
4624 [CLKID_VCLK_DIV] = &g12a_vclk_div.hw,
4625 [CLKID_VCLK2_DIV] = &g12a_vclk2_div.hw,
4626 [CLKID_VCLK] = &g12a_vclk.hw,
4627 [CLKID_VCLK2] = &g12a_vclk2.hw,
4628 [CLKID_VCLK_DIV1] = &g12a_vclk_div1.hw,
4629 [CLKID_VCLK_DIV2_EN] = &g12a_vclk_div2_en.hw,
4630 [CLKID_VCLK_DIV4_EN] = &g12a_vclk_div4_en.hw,
4631 [CLKID_VCLK_DIV6_EN] = &g12a_vclk_div6_en.hw,
4632 [CLKID_VCLK_DIV12_EN] = &g12a_vclk_div12_en.hw,
4633 [CLKID_VCLK2_DIV1] = &g12a_vclk2_div1.hw,
4634 [CLKID_VCLK2_DIV2_EN] = &g12a_vclk2_div2_en.hw,
4635 [CLKID_VCLK2_DIV4_EN] = &g12a_vclk2_div4_en.hw,
4636 [CLKID_VCLK2_DIV6_EN] = &g12a_vclk2_div6_en.hw,
4637 [CLKID_VCLK2_DIV12_EN] = &g12a_vclk2_div12_en.hw,
4638 [CLKID_VCLK_DIV2] = &g12a_vclk_div2.hw,
4639 [CLKID_VCLK_DIV4] = &g12a_vclk_div4.hw,
4640 [CLKID_VCLK_DIV6] = &g12a_vclk_div6.hw,
4641 [CLKID_VCLK_DIV12] = &g12a_vclk_div12.hw,
4642 [CLKID_VCLK2_DIV2] = &g12a_vclk2_div2.hw,
4643 [CLKID_VCLK2_DIV4] = &g12a_vclk2_div4.hw,
4644 [CLKID_VCLK2_DIV6] = &g12a_vclk2_div6.hw,
4645 [CLKID_VCLK2_DIV12] = &g12a_vclk2_div12.hw,
4646 [CLKID_CTS_ENCI_SEL] = &g12a_cts_enci_sel.hw,
4647 [CLKID_CTS_ENCP_SEL] = &g12a_cts_encp_sel.hw,
4648 [CLKID_CTS_VDAC_SEL] = &g12a_cts_vdac_sel.hw,
4649 [CLKID_HDMI_TX_SEL] = &g12a_hdmi_tx_sel.hw,
4650 [CLKID_CTS_ENCI] = &g12a_cts_enci.hw,
4651 [CLKID_CTS_ENCP] = &g12a_cts_encp.hw,
4652 [CLKID_CTS_VDAC] = &g12a_cts_vdac.hw,
4653 [CLKID_HDMI_TX] = &g12a_hdmi_tx.hw,
4654 [CLKID_HDMI_SEL] = &g12a_hdmi_sel.hw,
4655 [CLKID_HDMI_DIV] = &g12a_hdmi_div.hw,
4656 [CLKID_HDMI] = &g12a_hdmi.hw,
4657 [CLKID_MALI_0_SEL] = &g12a_mali_0_sel.hw,
4658 [CLKID_MALI_0_DIV] = &g12a_mali_0_div.hw,
4659 [CLKID_MALI_0] = &g12a_mali_0.hw,
4660 [CLKID_MALI_1_SEL] = &g12a_mali_1_sel.hw,
4661 [CLKID_MALI_1_DIV] = &g12a_mali_1_div.hw,
4662 [CLKID_MALI_1] = &g12a_mali_1.hw,
4663 [CLKID_MALI] = &g12a_mali.hw,
4664 [CLKID_MPLL_50M_DIV] = &g12a_mpll_50m_div.hw,
4665 [CLKID_MPLL_50M] = &g12a_mpll_50m.hw,
4666 [CLKID_SYS_PLL_DIV16_EN] = &g12a_sys_pll_div16_en.hw,
4667 [CLKID_SYS_PLL_DIV16] = &g12a_sys_pll_div16.hw,
4668 [CLKID_CPU_CLK_DYN0_SEL] = &g12a_cpu_clk_premux0.hw,
4669 [CLKID_CPU_CLK_DYN0_DIV] = &g12a_cpu_clk_mux0_div.hw,
4670 [CLKID_CPU_CLK_DYN0] = &g12a_cpu_clk_postmux0.hw,
4671 [CLKID_CPU_CLK_DYN1_SEL] = &g12a_cpu_clk_premux1.hw,
4672 [CLKID_CPU_CLK_DYN1_DIV] = &g12a_cpu_clk_mux1_div.hw,
4673 [CLKID_CPU_CLK_DYN1] = &g12a_cpu_clk_postmux1.hw,
4674 [CLKID_CPU_CLK_DYN] = &g12a_cpu_clk_dyn.hw,
4675 [CLKID_CPU_CLK] = &g12b_cpu_clk.hw,
4676 [CLKID_CPU_CLK_DIV16_EN] = &g12a_cpu_clk_div16_en.hw,
4677 [CLKID_CPU_CLK_DIV16] = &g12a_cpu_clk_div16.hw,
4678 [CLKID_CPU_CLK_APB_DIV] = &g12a_cpu_clk_apb_div.hw,
4679 [CLKID_CPU_CLK_APB] = &g12a_cpu_clk_apb.hw,
4680 [CLKID_CPU_CLK_ATB_DIV] = &g12a_cpu_clk_atb_div.hw,
4681 [CLKID_CPU_CLK_ATB] = &g12a_cpu_clk_atb.hw,
4682 [CLKID_CPU_CLK_AXI_DIV] = &g12a_cpu_clk_axi_div.hw,
4683 [CLKID_CPU_CLK_AXI] = &g12a_cpu_clk_axi.hw,
4684 [CLKID_CPU_CLK_TRACE_DIV] = &g12a_cpu_clk_trace_div.hw,
4685 [CLKID_CPU_CLK_TRACE] = &g12a_cpu_clk_trace.hw,
4686 [CLKID_PCIE_PLL_DCO] = &g12a_pcie_pll_dco.hw,
4687 [CLKID_PCIE_PLL_DCO_DIV2] = &g12a_pcie_pll_dco_div2.hw,
4688 [CLKID_PCIE_PLL_OD] = &g12a_pcie_pll_od.hw,
4689 [CLKID_PCIE_PLL] = &g12a_pcie_pll.hw,
4690 [CLKID_VDEC_1_SEL] = &g12a_vdec_1_sel.hw,
4691 [CLKID_VDEC_1_DIV] = &g12a_vdec_1_div.hw,
4692 [CLKID_VDEC_1] = &g12a_vdec_1.hw,
4693 [CLKID_VDEC_HEVC_SEL] = &g12a_vdec_hevc_sel.hw,
4694 [CLKID_VDEC_HEVC_DIV] = &g12a_vdec_hevc_div.hw,
4695 [CLKID_VDEC_HEVC] = &g12a_vdec_hevc.hw,
4696 [CLKID_VDEC_HEVCF_SEL] = &g12a_vdec_hevcf_sel.hw,
4697 [CLKID_VDEC_HEVCF_DIV] = &g12a_vdec_hevcf_div.hw,
4698 [CLKID_VDEC_HEVCF] = &g12a_vdec_hevcf.hw,
4699 [CLKID_TS_DIV] = &g12a_ts_div.hw,
4700 [CLKID_TS] = &g12a_ts.hw,
4701 [CLKID_SYS1_PLL_DCO] = &g12b_sys1_pll_dco.hw,
4702 [CLKID_SYS1_PLL] = &g12b_sys1_pll.hw,
4703 [CLKID_SYS1_PLL_DIV16_EN] = &g12b_sys1_pll_div16_en.hw,
4704 [CLKID_SYS1_PLL_DIV16] = &g12b_sys1_pll_div16.hw,
4705 [CLKID_CPUB_CLK_DYN0_SEL] = &g12b_cpub_clk_premux0.hw,
4706 [CLKID_CPUB_CLK_DYN0_DIV] = &g12b_cpub_clk_mux0_div.hw,
4707 [CLKID_CPUB_CLK_DYN0] = &g12b_cpub_clk_postmux0.hw,
4708 [CLKID_CPUB_CLK_DYN1_SEL] = &g12b_cpub_clk_premux1.hw,
4709 [CLKID_CPUB_CLK_DYN1_DIV] = &g12b_cpub_clk_mux1_div.hw,
4710 [CLKID_CPUB_CLK_DYN1] = &g12b_cpub_clk_postmux1.hw,
4711 [CLKID_CPUB_CLK_DYN] = &g12b_cpub_clk_dyn.hw,
4712 [CLKID_CPUB_CLK] = &g12b_cpub_clk.hw,
4713 [CLKID_CPUB_CLK_DIV16_EN] = &g12b_cpub_clk_div16_en.hw,
4714 [CLKID_CPUB_CLK_DIV16] = &g12b_cpub_clk_div16.hw,
4715 [CLKID_CPUB_CLK_DIV2] = &g12b_cpub_clk_div2.hw,
4716 [CLKID_CPUB_CLK_DIV3] = &g12b_cpub_clk_div3.hw,
4717 [CLKID_CPUB_CLK_DIV4] = &g12b_cpub_clk_div4.hw,
4718 [CLKID_CPUB_CLK_DIV5] = &g12b_cpub_clk_div5.hw,
4719 [CLKID_CPUB_CLK_DIV6] = &g12b_cpub_clk_div6.hw,
4720 [CLKID_CPUB_CLK_DIV7] = &g12b_cpub_clk_div7.hw,
4721 [CLKID_CPUB_CLK_DIV8] = &g12b_cpub_clk_div8.hw,
4722 [CLKID_CPUB_CLK_APB_SEL] = &g12b_cpub_clk_apb_sel.hw,
4723 [CLKID_CPUB_CLK_APB] = &g12b_cpub_clk_apb.hw,
4724 [CLKID_CPUB_CLK_ATB_SEL] = &g12b_cpub_clk_atb_sel.hw,
4725 [CLKID_CPUB_CLK_ATB] = &g12b_cpub_clk_atb.hw,
4726 [CLKID_CPUB_CLK_AXI_SEL] = &g12b_cpub_clk_axi_sel.hw,
4727 [CLKID_CPUB_CLK_AXI] = &g12b_cpub_clk_axi.hw,
4728 [CLKID_CPUB_CLK_TRACE_SEL] = &g12b_cpub_clk_trace_sel.hw,
4729 [CLKID_CPUB_CLK_TRACE] = &g12b_cpub_clk_trace.hw,
4730 [CLKID_SPICC0_SCLK_SEL] = &g12a_spicc0_sclk_sel.hw,
4731 [CLKID_SPICC0_SCLK_DIV] = &g12a_spicc0_sclk_div.hw,
4732 [CLKID_SPICC0_SCLK] = &g12a_spicc0_sclk.hw,
4733 [CLKID_SPICC1_SCLK_SEL] = &g12a_spicc1_sclk_sel.hw,
4734 [CLKID_SPICC1_SCLK_DIV] = &g12a_spicc1_sclk_div.hw,
4735 [CLKID_SPICC1_SCLK] = &g12a_spicc1_sclk.hw,
4736 [CLKID_NNA_AXI_CLK_SEL] = &sm1_nna_axi_clk_sel.hw,
4737 [CLKID_NNA_AXI_CLK_DIV] = &sm1_nna_axi_clk_div.hw,
4738 [CLKID_NNA_AXI_CLK] = &sm1_nna_axi_clk.hw,
4739 [CLKID_NNA_CORE_CLK_SEL] = &sm1_nna_core_clk_sel.hw,
4740 [CLKID_NNA_CORE_CLK_DIV] = &sm1_nna_core_clk_div.hw,
4741 [CLKID_NNA_CORE_CLK] = &sm1_nna_core_clk.hw,
4742 [CLKID_MIPI_DSI_PXCLK_SEL] = &g12a_mipi_dsi_pxclk_sel.hw,
4743 [CLKID_MIPI_DSI_PXCLK_DIV] = &g12a_mipi_dsi_pxclk_div.hw,
4744 [CLKID_MIPI_DSI_PXCLK] = &g12a_mipi_dsi_pxclk.hw,
4748 [CLKID_SYS_PLL] = &g12a_sys_pll.hw,
4749 [CLKID_FIXED_PLL] = &g12a_fixed_pll.hw,
4750 [CLKID_FCLK_DIV2] = &g12a_fclk_div2.hw,
4751 [CLKID_FCLK_DIV3] = &g12a_fclk_div3.hw,
4752 [CLKID_FCLK_DIV4] = &g12a_fclk_div4.hw,
4753 [CLKID_FCLK_DIV5] = &g12a_fclk_div5.hw,
4754 [CLKID_FCLK_DIV7] = &g12a_fclk_div7.hw,
4755 [CLKID_FCLK_DIV2P5] = &g12a_fclk_div2p5.hw,
4756 [CLKID_GP0_PLL] = &g12a_gp0_pll.hw,
4757 [CLKID_MPEG_SEL] = &g12a_mpeg_clk_sel.hw,
4758 [CLKID_MPEG_DIV] = &g12a_mpeg_clk_div.hw,
4759 [CLKID_CLK81] = &g12a_clk81.hw,
4760 [CLKID_MPLL0] = &g12a_mpll0.hw,
4761 [CLKID_MPLL1] = &g12a_mpll1.hw,
4762 [CLKID_MPLL2] = &g12a_mpll2.hw,
4763 [CLKID_MPLL3] = &g12a_mpll3.hw,
4764 [CLKID_DDR] = &g12a_ddr.hw,
4765 [CLKID_DOS] = &g12a_dos.hw,
4766 [CLKID_AUDIO_LOCKER] = &g12a_audio_locker.hw,
4767 [CLKID_MIPI_DSI_HOST] = &g12a_mipi_dsi_host.hw,
4768 [CLKID_ETH_PHY] = &g12a_eth_phy.hw,
4769 [CLKID_ISA] = &g12a_isa.hw,
4770 [CLKID_PL301] = &g12a_pl301.hw,
4771 [CLKID_PERIPHS] = &g12a_periphs.hw,
4772 [CLKID_SPICC0] = &g12a_spicc_0.hw,
4773 [CLKID_I2C] = &g12a_i2c.hw,
4774 [CLKID_SANA] = &g12a_sana.hw,
4775 [CLKID_SD] = &g12a_sd.hw,
4776 [CLKID_RNG0] = &g12a_rng0.hw,
4777 [CLKID_UART0] = &g12a_uart0.hw,
4778 [CLKID_SPICC1] = &g12a_spicc_1.hw,
4779 [CLKID_HIU_IFACE] = &g12a_hiu_reg.hw,
4780 [CLKID_MIPI_DSI_PHY] = &g12a_mipi_dsi_phy.hw,
4781 [CLKID_ASSIST_MISC] = &g12a_assist_misc.hw,
4782 [CLKID_SD_EMMC_A] = &g12a_emmc_a.hw,
4783 [CLKID_SD_EMMC_B] = &g12a_emmc_b.hw,
4784 [CLKID_SD_EMMC_C] = &g12a_emmc_c.hw,
4785 [CLKID_AUDIO_CODEC] = &g12a_audio_codec.hw,
4786 [CLKID_AUDIO] = &g12a_audio.hw,
4787 [CLKID_ETH] = &g12a_eth_core.hw,
4788 [CLKID_DEMUX] = &g12a_demux.hw,
4789 [CLKID_AUDIO_IFIFO] = &g12a_audio_ififo.hw,
4790 [CLKID_ADC] = &g12a_adc.hw,
4791 [CLKID_UART1] = &g12a_uart1.hw,
4792 [CLKID_G2D] = &g12a_g2d.hw,
4793 [CLKID_RESET] = &g12a_reset.hw,
4794 [CLKID_PCIE_COMB] = &g12a_pcie_comb.hw,
4795 [CLKID_PARSER] = &g12a_parser.hw,
4796 [CLKID_USB] = &g12a_usb_general.hw,
4797 [CLKID_PCIE_PHY] = &g12a_pcie_phy.hw,
4798 [CLKID_AHB_ARB0] = &g12a_ahb_arb0.hw,
4799 [CLKID_AHB_DATA_BUS] = &g12a_ahb_data_bus.hw,
4800 [CLKID_AHB_CTRL_BUS] = &g12a_ahb_ctrl_bus.hw,
4801 [CLKID_HTX_HDCP22] = &g12a_htx_hdcp22.hw,
4802 [CLKID_HTX_PCLK] = &g12a_htx_pclk.hw,
4803 [CLKID_BT656] = &g12a_bt656.hw,
4804 [CLKID_USB1_DDR_BRIDGE] = &g12a_usb1_to_ddr.hw,
4805 [CLKID_MMC_PCLK] = &g12a_mmc_pclk.hw,
4806 [CLKID_UART2] = &g12a_uart2.hw,
4807 [CLKID_VPU_INTR] = &g12a_vpu_intr.hw,
4808 [CLKID_GIC] = &g12a_gic.hw,
4809 [CLKID_SD_EMMC_A_CLK0_SEL] = &g12a_sd_emmc_a_clk0_sel.hw,
4810 [CLKID_SD_EMMC_A_CLK0_DIV] = &g12a_sd_emmc_a_clk0_div.hw,
4811 [CLKID_SD_EMMC_A_CLK0] = &g12a_sd_emmc_a_clk0.hw,
4812 [CLKID_SD_EMMC_B_CLK0_SEL] = &g12a_sd_emmc_b_clk0_sel.hw,
4813 [CLKID_SD_EMMC_B_CLK0_DIV] = &g12a_sd_emmc_b_clk0_div.hw,
4814 [CLKID_SD_EMMC_B_CLK0] = &g12a_sd_emmc_b_clk0.hw,
4815 [CLKID_SD_EMMC_C_CLK0_SEL] = &g12a_sd_emmc_c_clk0_sel.hw,
4816 [CLKID_SD_EMMC_C_CLK0_DIV] = &g12a_sd_emmc_c_clk0_div.hw,
4817 [CLKID_SD_EMMC_C_CLK0] = &g12a_sd_emmc_c_clk0.hw,
4818 [CLKID_MPLL0_DIV] = &g12a_mpll0_div.hw,
4819 [CLKID_MPLL1_DIV] = &g12a_mpll1_div.hw,
4820 [CLKID_MPLL2_DIV] = &g12a_mpll2_div.hw,
4821 [CLKID_MPLL3_DIV] = &g12a_mpll3_div.hw,
4822 [CLKID_FCLK_DIV2_DIV] = &g12a_fclk_div2_div.hw,
4823 [CLKID_FCLK_DIV3_DIV] = &g12a_fclk_div3_div.hw,
4824 [CLKID_FCLK_DIV4_DIV] = &g12a_fclk_div4_div.hw,
4825 [CLKID_FCLK_DIV5_DIV] = &g12a_fclk_div5_div.hw,
4826 [CLKID_FCLK_DIV7_DIV] = &g12a_fclk_div7_div.hw,
4827 [CLKID_FCLK_DIV2P5_DIV] = &g12a_fclk_div2p5_div.hw,
4828 [CLKID_HIFI_PLL] = &g12a_hifi_pll.hw,
4829 [CLKID_VCLK2_VENCI0] = &g12a_vclk2_venci0.hw,
4830 [CLKID_VCLK2_VENCI1] = &g12a_vclk2_venci1.hw,
4831 [CLKID_VCLK2_VENCP0] = &g12a_vclk2_vencp0.hw,
4832 [CLKID_VCLK2_VENCP1] = &g12a_vclk2_vencp1.hw,
4833 [CLKID_VCLK2_VENCT0] = &g12a_vclk2_venct0.hw,
4834 [CLKID_VCLK2_VENCT1] = &g12a_vclk2_venct1.hw,
4835 [CLKID_VCLK2_OTHER] = &g12a_vclk2_other.hw,
4836 [CLKID_VCLK2_ENCI] = &g12a_vclk2_enci.hw,
4837 [CLKID_VCLK2_ENCP] = &g12a_vclk2_encp.hw,
4838 [CLKID_DAC_CLK] = &g12a_dac_clk.hw,
4839 [CLKID_AOCLK] = &g12a_aoclk_gate.hw,
4840 [CLKID_IEC958] = &g12a_iec958_gate.hw,
4841 [CLKID_ENC480P] = &g12a_enc480p.hw,
4842 [CLKID_RNG1] = &g12a_rng1.hw,
4843 [CLKID_VCLK2_ENCT] = &g12a_vclk2_enct.hw,
4844 [CLKID_VCLK2_ENCL] = &g12a_vclk2_encl.hw,
4845 [CLKID_VCLK2_VENCLMMC] = &g12a_vclk2_venclmmc.hw,
4846 [CLKID_VCLK2_VENCL] = &g12a_vclk2_vencl.hw,
4847 [CLKID_VCLK2_OTHER1] = &g12a_vclk2_other1.hw,
4848 [CLKID_FIXED_PLL_DCO] = &g12a_fixed_pll_dco.hw,
4849 [CLKID_SYS_PLL_DCO] = &g12a_sys_pll_dco.hw,
4850 [CLKID_GP0_PLL_DCO] = &g12a_gp0_pll_dco.hw,
4851 [CLKID_HIFI_PLL_DCO] = &g12a_hifi_pll_dco.hw,
4852 [CLKID_DMA] = &g12a_dma.hw,
4853 [CLKID_EFUSE] = &g12a_efuse.hw,
4854 [CLKID_ROM_BOOT] = &g12a_rom_boot.hw,
4855 [CLKID_RESET_SEC] = &g12a_reset_sec.hw,
4856 [CLKID_SEC_AHB_APB3] = &g12a_sec_ahb_apb3.hw,
4857 [CLKID_MPLL_PREDIV] = &g12a_mpll_prediv.hw,
4858 [CLKID_VPU_0_SEL] = &g12a_vpu_0_sel.hw,
4859 [CLKID_VPU_0_DIV] = &g12a_vpu_0_div.hw,
4860 [CLKID_VPU_0] = &g12a_vpu_0.hw,
4861 [CLKID_VPU_1_SEL] = &g12a_vpu_1_sel.hw,
4862 [CLKID_VPU_1_DIV] = &g12a_vpu_1_div.hw,
4863 [CLKID_VPU_1] = &g12a_vpu_1.hw,
4864 [CLKID_VPU] = &g12a_vpu.hw,
4865 [CLKID_VAPB_0_SEL] = &g12a_vapb_0_sel.hw,
4866 [CLKID_VAPB_0_DIV] = &g12a_vapb_0_div.hw,
4867 [CLKID_VAPB_0] = &g12a_vapb_0.hw,
4868 [CLKID_VAPB_1_SEL] = &g12a_vapb_1_sel.hw,
4869 [CLKID_VAPB_1_DIV] = &g12a_vapb_1_div.hw,
4870 [CLKID_VAPB_1] = &g12a_vapb_1.hw,
4871 [CLKID_VAPB_SEL] = &g12a_vapb_sel.hw,
4872 [CLKID_VAPB] = &g12a_vapb.hw,
4873 [CLKID_HDMI_PLL_DCO] = &g12a_hdmi_pll_dco.hw,
4874 [CLKID_HDMI_PLL_OD] = &g12a_hdmi_pll_od.hw,
4875 [CLKID_HDMI_PLL_OD2] = &g12a_hdmi_pll_od2.hw,
4876 [CLKID_HDMI_PLL] = &g12a_hdmi_pll.hw,
4877 [CLKID_VID_PLL] = &g12a_vid_pll_div.hw,
4878 [CLKID_VID_PLL_SEL] = &g12a_vid_pll_sel.hw,
4879 [CLKID_VID_PLL_DIV] = &g12a_vid_pll.hw,
4880 [CLKID_VCLK_SEL] = &g12a_vclk_sel.hw,
4881 [CLKID_VCLK2_SEL] = &g12a_vclk2_sel.hw,
4882 [CLKID_VCLK_INPUT] = &g12a_vclk_input.hw,
4883 [CLKID_VCLK2_INPUT] = &g12a_vclk2_input.hw,
4884 [CLKID_VCLK_DIV] = &g12a_vclk_div.hw,
4885 [CLKID_VCLK2_DIV] = &g12a_vclk2_div.hw,
4886 [CLKID_VCLK] = &g12a_vclk.hw,
4887 [CLKID_VCLK2] = &g12a_vclk2.hw,
4888 [CLKID_VCLK_DIV1] = &g12a_vclk_div1.hw,
4889 [CLKID_VCLK_DIV2_EN] = &g12a_vclk_div2_en.hw,
4890 [CLKID_VCLK_DIV4_EN] = &g12a_vclk_div4_en.hw,
4891 [CLKID_VCLK_DIV6_EN] = &g12a_vclk_div6_en.hw,
4892 [CLKID_VCLK_DIV12_EN] = &g12a_vclk_div12_en.hw,
4893 [CLKID_VCLK2_DIV1] = &g12a_vclk2_div1.hw,
4894 [CLKID_VCLK2_DIV2_EN] = &g12a_vclk2_div2_en.hw,
4895 [CLKID_VCLK2_DIV4_EN] = &g12a_vclk2_div4_en.hw,
4896 [CLKID_VCLK2_DIV6_EN] = &g12a_vclk2_div6_en.hw,
4897 [CLKID_VCLK2_DIV12_EN] = &g12a_vclk2_div12_en.hw,
4898 [CLKID_VCLK_DIV2] = &g12a_vclk_div2.hw,
4899 [CLKID_VCLK_DIV4] = &g12a_vclk_div4.hw,
4900 [CLKID_VCLK_DIV6] = &g12a_vclk_div6.hw,
4901 [CLKID_VCLK_DIV12] = &g12a_vclk_div12.hw,
4902 [CLKID_VCLK2_DIV2] = &g12a_vclk2_div2.hw,
4903 [CLKID_VCLK2_DIV4] = &g12a_vclk2_div4.hw,
4904 [CLKID_VCLK2_DIV6] = &g12a_vclk2_div6.hw,
4905 [CLKID_VCLK2_DIV12] = &g12a_vclk2_div12.hw,
4906 [CLKID_CTS_ENCI_SEL] = &g12a_cts_enci_sel.hw,
4907 [CLKID_CTS_ENCP_SEL] = &g12a_cts_encp_sel.hw,
4908 [CLKID_CTS_VDAC_SEL] = &g12a_cts_vdac_sel.hw,
4909 [CLKID_HDMI_TX_SEL] = &g12a_hdmi_tx_sel.hw,
4910 [CLKID_CTS_ENCI] = &g12a_cts_enci.hw,
4911 [CLKID_CTS_ENCP] = &g12a_cts_encp.hw,
4912 [CLKID_CTS_VDAC] = &g12a_cts_vdac.hw,
4913 [CLKID_HDMI_TX] = &g12a_hdmi_tx.hw,
4914 [CLKID_HDMI_SEL] = &g12a_hdmi_sel.hw,
4915 [CLKID_HDMI_DIV] = &g12a_hdmi_div.hw,
4916 [CLKID_HDMI] = &g12a_hdmi.hw,
4917 [CLKID_MALI_0_SEL] = &g12a_mali_0_sel.hw,
4918 [CLKID_MALI_0_DIV] = &g12a_mali_0_div.hw,
4919 [CLKID_MALI_0] = &g12a_mali_0.hw,
4920 [CLKID_MALI_1_SEL] = &g12a_mali_1_sel.hw,
4921 [CLKID_MALI_1_DIV] = &g12a_mali_1_div.hw,
4922 [CLKID_MALI_1] = &g12a_mali_1.hw,
4923 [CLKID_MALI] = &g12a_mali.hw,
4924 [CLKID_MPLL_50M_DIV] = &g12a_mpll_50m_div.hw,
4925 [CLKID_MPLL_50M] = &g12a_mpll_50m.hw,
4926 [CLKID_SYS_PLL_DIV16_EN] = &g12a_sys_pll_div16_en.hw,
4927 [CLKID_SYS_PLL_DIV16] = &g12a_sys_pll_div16.hw,
4928 [CLKID_CPU_CLK_DYN0_SEL] = &g12a_cpu_clk_premux0.hw,
4929 [CLKID_CPU_CLK_DYN0_DIV] = &g12a_cpu_clk_mux0_div.hw,
4930 [CLKID_CPU_CLK_DYN0] = &g12a_cpu_clk_postmux0.hw,
4931 [CLKID_CPU_CLK_DYN1_SEL] = &g12a_cpu_clk_premux1.hw,
4932 [CLKID_CPU_CLK_DYN1_DIV] = &g12a_cpu_clk_mux1_div.hw,
4933 [CLKID_CPU_CLK_DYN1] = &g12a_cpu_clk_postmux1.hw,
4934 [CLKID_CPU_CLK_DYN] = &g12a_cpu_clk_dyn.hw,
4935 [CLKID_CPU_CLK] = &g12a_cpu_clk.hw,
4936 [CLKID_CPU_CLK_DIV16_EN] = &g12a_cpu_clk_div16_en.hw,
4937 [CLKID_CPU_CLK_DIV16] = &g12a_cpu_clk_div16.hw,
4938 [CLKID_CPU_CLK_APB_DIV] = &g12a_cpu_clk_apb_div.hw,
4939 [CLKID_CPU_CLK_APB] = &g12a_cpu_clk_apb.hw,
4940 [CLKID_CPU_CLK_ATB_DIV] = &g12a_cpu_clk_atb_div.hw,
4941 [CLKID_CPU_CLK_ATB] = &g12a_cpu_clk_atb.hw,
4942 [CLKID_CPU_CLK_AXI_DIV] = &g12a_cpu_clk_axi_div.hw,
4943 [CLKID_CPU_CLK_AXI] = &g12a_cpu_clk_axi.hw,
4944 [CLKID_CPU_CLK_TRACE_DIV] = &g12a_cpu_clk_trace_div.hw,
4945 [CLKID_CPU_CLK_TRACE] = &g12a_cpu_clk_trace.hw,
4946 [CLKID_PCIE_PLL_DCO] = &g12a_pcie_pll_dco.hw,
4947 [CLKID_PCIE_PLL_DCO_DIV2] = &g12a_pcie_pll_dco_div2.hw,
4948 [CLKID_PCIE_PLL_OD] = &g12a_pcie_pll_od.hw,
4949 [CLKID_PCIE_PLL] = &g12a_pcie_pll.hw,
4950 [CLKID_VDEC_1_SEL] = &g12a_vdec_1_sel.hw,
4951 [CLKID_VDEC_1_DIV] = &g12a_vdec_1_div.hw,
4952 [CLKID_VDEC_1] = &g12a_vdec_1.hw,
4953 [CLKID_VDEC_HEVC_SEL] = &g12a_vdec_hevc_sel.hw,
4954 [CLKID_VDEC_HEVC_DIV] = &g12a_vdec_hevc_div.hw,
4955 [CLKID_VDEC_HEVC] = &g12a_vdec_hevc.hw,
4956 [CLKID_VDEC_HEVCF_SEL] = &g12a_vdec_hevcf_sel.hw,
4957 [CLKID_VDEC_HEVCF_DIV] = &g12a_vdec_hevcf_div.hw,
4958 [CLKID_VDEC_HEVCF] = &g12a_vdec_hevcf.hw,
4959 [CLKID_TS_DIV] = &g12a_ts_div.hw,
4960 [CLKID_TS] = &g12a_ts.hw,
4961 [CLKID_GP1_PLL_DCO] = &sm1_gp1_pll_dco.hw,
4962 [CLKID_GP1_PLL] = &sm1_gp1_pll.hw,
4963 [CLKID_DSU_CLK_DYN0_SEL] = &sm1_dsu_clk_premux0.hw,
4964 [CLKID_DSU_CLK_DYN0_DIV] = &sm1_dsu_clk_premux1.hw,
4965 [CLKID_DSU_CLK_DYN0] = &sm1_dsu_clk_mux0_div.hw,
4966 [CLKID_DSU_CLK_DYN1_SEL] = &sm1_dsu_clk_postmux0.hw,
4967 [CLKID_DSU_CLK_DYN1_DIV] = &sm1_dsu_clk_mux1_div.hw,
4968 [CLKID_DSU_CLK_DYN1] = &sm1_dsu_clk_postmux1.hw,
4969 [CLKID_DSU_CLK_DYN] = &sm1_dsu_clk_dyn.hw,
4970 [CLKID_DSU_CLK_FINAL] = &sm1_dsu_final_clk.hw,
4971 [CLKID_DSU_CLK] = &sm1_dsu_clk.hw,
4972 [CLKID_CPU1_CLK] = &sm1_cpu1_clk.hw,
4973 [CLKID_CPU2_CLK] = &sm1_cpu2_clk.hw,
4974 [CLKID_CPU3_CLK] = &sm1_cpu3_clk.hw,
4975 [CLKID_SPICC0_SCLK_SEL] = &g12a_spicc0_sclk_sel.hw,
4976 [CLKID_SPICC0_SCLK_DIV] = &g12a_spicc0_sclk_div.hw,
4977 [CLKID_SPICC0_SCLK] = &g12a_spicc0_sclk.hw,
4978 [CLKID_SPICC1_SCLK_SEL] = &g12a_spicc1_sclk_sel.hw,
4979 [CLKID_SPICC1_SCLK_DIV] = &g12a_spicc1_sclk_div.hw,
4980 [CLKID_SPICC1_SCLK] = &g12a_spicc1_sclk.hw,
4981 [CLKID_NNA_AXI_CLK_SEL] = &sm1_nna_axi_clk_sel.hw,
4982 [CLKID_NNA_AXI_CLK_DIV] = &sm1_nna_axi_clk_div.hw,
4983 [CLKID_NNA_AXI_CLK] = &sm1_nna_axi_clk.hw,
4984 [CLKID_NNA_CORE_CLK_SEL] = &sm1_nna_core_clk_sel.hw,
4985 [CLKID_NNA_CORE_CLK_DIV] = &sm1_nna_core_clk_div.hw,
4986 [CLKID_NNA_CORE_CLK] = &sm1_nna_core_clk.hw,
4987 [CLKID_MIPI_DSI_PXCLK_SEL] = &g12a_mipi_dsi_pxclk_sel.hw,
4988 [CLKID_MIPI_DSI_PXCLK_DIV] = &g12a_mipi_dsi_pxclk_div.hw,
4989 [CLKID_MIPI_DSI_PXCLK] = &g12a_mipi_dsi_pxclk.hw,
5256 notifier_clk = devm_clk_hw_get_clk(dev, &g12a_cpu_clk_postmux0.hw, in meson_g12a_dvfs_setup_common()
5266 notifier_clk = devm_clk_hw_get_clk(dev, &g12a_cpu_clk_dyn.hw, in meson_g12a_dvfs_setup_common()
5293 notifier_clk = devm_clk_hw_get_clk(dev, &g12b_cpu_clk.hw, in meson_g12b_dvfs_setup()
5303 notifier_clk = devm_clk_hw_get_clk(dev, &g12b_sys1_pll.hw, in meson_g12b_dvfs_setup()
5316 notifier_clk = devm_clk_hw_get_clk(dev, &g12b_cpub_clk_postmux0.hw, in meson_g12b_dvfs_setup()
5326 notifier_clk = devm_clk_hw_get_clk(dev, &g12b_cpub_clk_dyn.hw, "dvfs"); in meson_g12b_dvfs_setup()
5335 notifier_clk = devm_clk_hw_get_clk(dev, &g12b_cpub_clk.hw, DVFS_CON_ID); in meson_g12b_dvfs_setup()
5344 notifier_clk = devm_clk_hw_get_clk(dev, &g12a_sys_pll.hw, DVFS_CON_ID); in meson_g12b_dvfs_setup()
5367 notifier_clk = devm_clk_hw_get_clk(dev, &g12a_cpu_clk.hw, DVFS_CON_ID); in meson_g12a_dvfs_setup()
5376 notifier_clk = devm_clk_hw_get_clk(dev, &g12a_sys_pll.hw, DVFS_CON_ID); in meson_g12a_dvfs_setup()