1 // SPDX-License-Identifier: GPL-2.0+
3  * Amlogic Meson-G12A Clock Controller Driver
13 #include <linux/clk-provider.h>
20 #include "clk-mpll.h"
21 #include "clk-pll.h"
22 #include "clk-regmap.h"
23 #include "clk-cpu-dyndiv.h"
24 #include "vid-pll-div.h"
25 #include "meson-eeclk.h"
26 #include "g12a.h"
28 #include <dt-bindings/clock/g12a-clkc.h>
311 		 * b) CCF has a clock hand-off mechanism to make the sure the
347 		 * b) CCF has a clock hand-off mechanism to make the sure the
391 		/* This sub-tree is used a parking clock */
473 		/* This sub-tree is used a parking clock */
620 		/* This sub-tree is used a parking clock */
657 		/* This sub-tree is used a parking clock */
959 		 *    \- cpu_clk_dyn  in g12a_cpu_clk_postmux_notifier_cb()
960 		 *          \- cpu_clk_postmux0  in g12a_cpu_clk_postmux_notifier_cb()
961 		 *                \- cpu_clk_muxX_div  in g12a_cpu_clk_postmux_notifier_cb()
962 		 *                      \- cpu_clk_premux0  in g12a_cpu_clk_postmux_notifier_cb()
963 		 *				\- fclk_div3 or fclk_div2  in g12a_cpu_clk_postmux_notifier_cb()
965 		 *                \- cpu_clk_premux0  in g12a_cpu_clk_postmux_notifier_cb()
966 		 *			\- fclk_div3 or fclk_div2  in g12a_cpu_clk_postmux_notifier_cb()
970 		clk_hw_set_parent(nb_data->cpu_clk_premux1,  in g12a_cpu_clk_postmux_notifier_cb()
971 				  nb_data->xtal);  in g12a_cpu_clk_postmux_notifier_cb()
974 		clk_hw_set_parent(nb_data->cpu_clk_postmux1,  in g12a_cpu_clk_postmux_notifier_cb()
975 				  nb_data->cpu_clk_premux1);  in g12a_cpu_clk_postmux_notifier_cb()
978 		clk_hw_set_parent(nb_data->cpu_clk_dyn,  in g12a_cpu_clk_postmux_notifier_cb()
979 				  nb_data->cpu_clk_postmux1);  in g12a_cpu_clk_postmux_notifier_cb()
984 		 *    \- cpu_clk_dyn  in g12a_cpu_clk_postmux_notifier_cb()
985 		 *          \- cpu_clk_postmux1  in g12a_cpu_clk_postmux_notifier_cb()
986 		 *                \- cpu_clk_premux1  in g12a_cpu_clk_postmux_notifier_cb()
987 		 *                      \- xtal  in g12a_cpu_clk_postmux_notifier_cb()
1002 		clk_hw_set_parent(nb_data->cpu_clk_dyn,  in g12a_cpu_clk_postmux_notifier_cb()
1003 				  nb_data->cpu_clk_postmux0);  in g12a_cpu_clk_postmux_notifier_cb()
1008 		 *    \- cpu_clk_dyn  in g12a_cpu_clk_postmux_notifier_cb()
1009 		 *          \- cpu_clk_postmux0  in g12a_cpu_clk_postmux_notifier_cb()
1010 		 *                \- cpu_clk_muxX_div  in g12a_cpu_clk_postmux_notifier_cb()
1011 		 *                      \- cpu_clk_premux0  in g12a_cpu_clk_postmux_notifier_cb()
1012 		 *				\- fclk_div3 or fclk_div2  in g12a_cpu_clk_postmux_notifier_cb()
1014 		 *                \- cpu_clk_premux0  in g12a_cpu_clk_postmux_notifier_cb()
1015 		 *			\- fclk_div3 or fclk_div2  in g12a_cpu_clk_postmux_notifier_cb()
1062 		 *    \- sys_pll  in g12a_sys_pll_notifier_cb()
1063 		 *          \- sys_pll_dco  in g12a_sys_pll_notifier_cb()
1067 		clk_hw_set_parent(nb_data->cpu_clk,  in g12a_sys_pll_notifier_cb()
1068 				  nb_data->cpu_clk_dyn);  in g12a_sys_pll_notifier_cb()
1073 		 *    \- cpu_clk_dyn  in g12a_sys_pll_notifier_cb()
1074 		 *          \- cpu_clk_dynX  in g12a_sys_pll_notifier_cb()
1075 		 *                \- cpu_clk_dynX_sel  in g12a_sys_pll_notifier_cb()
1076 		 *		     \- cpu_clk_dynX_div  in g12a_sys_pll_notifier_cb()
1077 		 *                      \- xtal/fclk_div2/fclk_div3  in g12a_sys_pll_notifier_cb()
1078 		 *                   \- xtal/fclk_div2/fclk_div3  in g12a_sys_pll_notifier_cb()
1092 		clk_hw_set_parent(nb_data->cpu_clk,  in g12a_sys_pll_notifier_cb()
1093 				  nb_data->sys_pll);  in g12a_sys_pll_notifier_cb()
1099 		 *    \- sys_pll  in g12a_sys_pll_notifier_cb()
1100 		 *          \- sys_pll_dco  in g12a_sys_pll_notifier_cb()
1144 			 * G12A and G12B have different cpu clocks (with
1152 			.index = -1,
1219 			.index = -1,
1256 			.index = -1,
1293 			.index = -1,
1330 			.index = -1,
1843  * The Meson G12A PCIE PLL is fined tuned to deliver a very precise
3792  * The MALI IP is clocked by two identical clocks (mali_0 and mali_1)
3793  * muxed by a glitch-free switch. The CCF can manage this glitch-free
3794  * mux because it does top-to-bottom updates the each clock tree and
3928 		.name = "mali",
5281 	struct device *dev = &pdev->dev;  in meson_g12b_dvfs_setup()
5358 	struct device *dev = &pdev->dev;  in meson_g12a_dvfs_setup()
5398 	eeclkc_data = of_device_get_match_data(&pdev->dev);  in meson_g12a_probe()
5400 		return -EINVAL;  in meson_g12a_probe()
5409 	if (g12a_data->dvfs_setup)  in meson_g12a_probe()
5410 		return g12a_data->dvfs_setup(pdev);  in meson_g12a_probe()
5455 		.compatible = "amlogic,g12a-clkc",
5459 		.compatible = "amlogic,g12b-clkc",
5463 		.compatible = "amlogic,sm1-clkc",
5473 		.name	= "g12a-clkc",