Lines Matching +full:11 +full:- +full:bit
1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Register descriptions for NI DAQ-STC chip
5 * COMEDI - Linux Control and Measurement Device Interface
6 * Copyright (C) 1998-9 David A. Schleef <ds@schleef.org>
11 * DAQ-STC Technical Reference Manual
21 * Registers in the National Instruments DAQ-STC chip
25 #define NISTC_INTA_ACK_G0_GATE BIT(15)
26 #define NISTC_INTA_ACK_G0_TC BIT(14)
27 #define NISTC_INTA_ACK_AI_ERR BIT(13)
28 #define NISTC_INTA_ACK_AI_STOP BIT(12)
29 #define NISTC_INTA_ACK_AI_START BIT(11)
30 #define NISTC_INTA_ACK_AI_START2 BIT(10)
31 #define NISTC_INTA_ACK_AI_START1 BIT(9)
32 #define NISTC_INTA_ACK_AI_SC_TC BIT(8)
33 #define NISTC_INTA_ACK_AI_SC_TC_ERR BIT(7)
34 #define NISTC_INTA_ACK_G0_TC_ERR BIT(6)
35 #define NISTC_INTA_ACK_G0_GATE_ERR BIT(5)
45 #define NISTC_INTB_ACK_G1_GATE BIT(15)
46 #define NISTC_INTB_ACK_G1_TC BIT(14)
47 #define NISTC_INTB_ACK_AO_ERR BIT(13)
48 #define NISTC_INTB_ACK_AO_STOP BIT(12)
49 #define NISTC_INTB_ACK_AO_START BIT(11)
50 #define NISTC_INTB_ACK_AO_UPDATE BIT(10)
51 #define NISTC_INTB_ACK_AO_START1 BIT(9)
52 #define NISTC_INTB_ACK_AO_BC_TC BIT(8)
53 #define NISTC_INTB_ACK_AO_UC_TC BIT(7)
54 #define NISTC_INTB_ACK_AO_UI2_TC BIT(6)
55 #define NISTC_INTB_ACK_AO_UI2_TC_ERR BIT(5)
56 #define NISTC_INTB_ACK_AO_BC_TC_ERR BIT(4)
57 #define NISTC_INTB_ACK_AO_BC_TC_TRIG_ERR BIT(3)
58 #define NISTC_INTB_ACK_G1_TC_ERR BIT(2)
59 #define NISTC_INTB_ACK_G1_GATE_ERR BIT(1)
71 #define NISTC_AI_CMD2_END_ON_SC_TC BIT(15)
72 #define NISTC_AI_CMD2_END_ON_EOS BIT(14)
73 #define NISTC_AI_CMD2_START1_DISABLE BIT(11)
74 #define NISTC_AI_CMD2_SC_SAVE_TRACE BIT(10)
75 #define NISTC_AI_CMD2_SI_SW_ON_SC_TC BIT(9)
76 #define NISTC_AI_CMD2_SI_SW_ON_STOP BIT(8)
77 #define NISTC_AI_CMD2_SI_SW_ON_TC BIT(7)
78 #define NISTC_AI_CMD2_SC_SW_ON_TC BIT(4)
79 #define NISTC_AI_CMD2_STOP_PULSE BIT(3)
80 #define NISTC_AI_CMD2_START_PULSE BIT(2)
81 #define NISTC_AI_CMD2_START2_PULSE BIT(1)
82 #define NISTC_AI_CMD2_START1_PULSE BIT(0)
86 #define NISTC_AO_CMD2_START_STOP_GATE_ENA BIT(13)
87 #define NISTC_AO_CMD2_UC_SAVE_TRACE BIT(12)
88 #define NISTC_AO_CMD2_BC_GATE_ENA BIT(11)
89 #define NISTC_AO_CMD2_BC_SAVE_TRACE BIT(10)
90 #define NISTC_AO_CMD2_UI_SW_ON_BC_TC BIT(9)
91 #define NISTC_AO_CMD2_UI_SW_ON_STOP BIT(8)
92 #define NISTC_AO_CMD2_UI_SW_ON_TC BIT(7)
93 #define NISTC_AO_CMD2_UC_SW_ON_BC_TC BIT(6)
94 #define NISTC_AO_CMD2_UC_SW_ON_TC BIT(5)
95 #define NISTC_AO_CMD2_BC_SW_ON_TC BIT(4)
96 #define NISTC_AO_CMD2_MUTE_B BIT(3)
97 #define NISTC_AO_CMD2_MUTE_A BIT(2)
98 #define NISTC_AO_CMD2_UPDATE2_PULSE BIT(1)
99 #define NISTC_AO_CMD2_START1_PULSE BIT(0)
105 #define NISTC_AI_CMD1_ATRIG_RESET BIT(14)
106 #define NISTC_AI_CMD1_DISARM BIT(13)
107 #define NISTC_AI_CMD1_SI2_ARM BIT(12)
108 #define NISTC_AI_CMD1_SI2_LOAD BIT(11)
109 #define NISTC_AI_CMD1_SI_ARM BIT(10)
110 #define NISTC_AI_CMD1_SI_LOAD BIT(9)
111 #define NISTC_AI_CMD1_DIV_ARM BIT(8)
112 #define NISTC_AI_CMD1_DIV_LOAD BIT(7)
113 #define NISTC_AI_CMD1_SC_ARM BIT(6)
114 #define NISTC_AI_CMD1_SC_LOAD BIT(5)
115 #define NISTC_AI_CMD1_SCAN_IN_PROG_PULSE BIT(4)
116 #define NISTC_AI_CMD1_EXTMUX_CLK_PULSE BIT(3)
117 #define NISTC_AI_CMD1_LOCALMUX_CLK_PULSE BIT(2)
118 #define NISTC_AI_CMD1_SC_TC_PULSE BIT(1)
119 #define NISTC_AI_CMD1_CONVERT_PULSE BIT(0)
122 #define NISTC_AO_CMD1_ATRIG_RESET BIT(15)
123 #define NISTC_AO_CMD1_START_PULSE BIT(14)
124 #define NISTC_AO_CMD1_DISARM BIT(13)
125 #define NISTC_AO_CMD1_UI2_ARM_DISARM BIT(12)
126 #define NISTC_AO_CMD1_UI2_LOAD BIT(11)
127 #define NISTC_AO_CMD1_UI_ARM BIT(10)
128 #define NISTC_AO_CMD1_UI_LOAD BIT(9)
129 #define NISTC_AO_CMD1_UC_ARM BIT(8)
130 #define NISTC_AO_CMD1_UC_LOAD BIT(7)
131 #define NISTC_AO_CMD1_BC_ARM BIT(6)
132 #define NISTC_AO_CMD1_BC_LOAD BIT(5)
133 #define NISTC_AO_CMD1_DAC1_UPDATE_MODE BIT(4)
134 #define NISTC_AO_CMD1_LDAC1_SRC_SEL BIT(3)
135 #define NISTC_AO_CMD1_DAC0_UPDATE_MODE BIT(2)
136 #define NISTC_AO_CMD1_LDAC0_SRC_SEL BIT(1)
137 #define NISTC_AO_CMD1_UPDATE_PULSE BIT(0)
144 #define NISTC_DIO_SDIN BIT(4)
145 #define NISTC_DIO_SDOUT BIT(0)
147 #define NISTC_DIO_CTRL_REG 11
148 #define NISTC_DIO_SDCLK BIT(11)
149 #define NISTC_DIO_CTRL_HW_SER_TIMEBASE BIT(10)
150 #define NISTC_DIO_CTRL_HW_SER_ENA BIT(9)
151 #define NISTC_DIO_CTRL_HW_SER_START BIT(8)
156 #define NISTC_AI_MODE1_CONVERT_SRC(x) (((x) & 0x1f) << 11)
158 #define NISTC_AI_MODE1_CONVERT_POLARITY BIT(5)
159 #define NISTC_AI_MODE1_SI_POLARITY BIT(4)
160 #define NISTC_AI_MODE1_START_STOP BIT(3)
161 #define NISTC_AI_MODE1_RSVD BIT(2)
162 #define NISTC_AI_MODE1_CONTINUOUS BIT(1)
163 #define NISTC_AI_MODE1_TRIGGER_ONCE BIT(0)
166 #define NISTC_AI_MODE2_SC_GATE_ENA BIT(15)
167 #define NISTC_AI_MODE2_START_STOP_GATE_ENA BIT(14)
168 #define NISTC_AI_MODE2_PRE_TRIGGER BIT(13)
169 #define NISTC_AI_MODE2_EXTMUX_PRESENT BIT(12)
170 #define NISTC_AI_MODE2_SI2_INIT_LOAD_SRC BIT(9)
171 #define NISTC_AI_MODE2_SI2_RELOAD_MODE BIT(8)
172 #define NISTC_AI_MODE2_SI_INIT_LOAD_SRC BIT(7)
174 #define NISTC_AI_MODE2_SI_WR_SWITCH BIT(3)
175 #define NISTC_AI_MODE2_SC_INIT_LOAD_SRC BIT(2)
176 #define NISTC_AI_MODE2_SC_RELOAD_MODE BIT(1)
177 #define NISTC_AI_MODE2_SC_WR_SWITCH BIT(0)
196 #define NISTC_AO_MODE1_UPDATE_SRC(x) (((x) & 0x1f) << 11)
200 #define NISTC_AO_MODE1_MULTI_CHAN BIT(5)
201 #define NISTC_AO_MODE1_UPDATE_SRC_POLARITY BIT(4)
202 #define NISTC_AO_MODE1_UI_SRC_POLARITY BIT(3)
203 #define NISTC_AO_MODE1_UC_SW_EVERY_TC BIT(2)
204 #define NISTC_AO_MODE1_CONTINUOUS BIT(1)
205 #define NISTC_AO_MODE1_TRIGGER_ONCE BIT(0)
214 #define NISTC_AO_MODE2_FIFO_REXMIT_ENA BIT(13)
215 #define NISTC_AO_MODE2_START1_DISABLE BIT(12)
216 #define NISTC_AO_MODE2_UC_INIT_LOAD_SRC BIT(11)
217 #define NISTC_AO_MODE2_UC_WR_SWITCH BIT(10)
218 #define NISTC_AO_MODE2_UI2_INIT_LOAD_SRC BIT(9)
219 #define NISTC_AO_MODE2_UI2_RELOAD_MODE BIT(8)
220 #define NISTC_AO_MODE2_UI_INIT_LOAD_SRC BIT(7)
222 #define NISTC_AO_MODE2_UI_WR_SWITCH BIT(3)
223 #define NISTC_AO_MODE2_BC_INIT_LOAD_SRC BIT(2)
224 #define NISTC_AO_MODE2_BC_RELOAD_MODE BIT(1)
225 #define NISTC_AO_MODE2_BC_WR_SWITCH BIT(0)
235 #define NISTC_CLK_FOUT_ENA BIT(15)
236 #define NISTC_CLK_FOUT_TIMEBASE_SEL BIT(14)
237 #define NISTC_CLK_FOUT_DIO_SER_OUT_DIV2 BIT(13)
238 #define NISTC_CLK_FOUT_SLOW_DIV2 BIT(12)
239 #define NISTC_CLK_FOUT_SLOW_TIMEBASE BIT(11)
240 #define NISTC_CLK_FOUT_G_SRC_DIV2 BIT(10)
241 #define NISTC_CLK_FOUT_TO_BOARD_DIV2 BIT(9)
242 #define NISTC_CLK_FOUT_TO_BOARD BIT(8)
243 #define NISTC_CLK_FOUT_AI_OUT_DIV2 BIT(7)
244 #define NISTC_CLK_FOUT_AI_SRC_DIV2 BIT(6)
245 #define NISTC_CLK_FOUT_AO_OUT_DIV2 BIT(5)
246 #define NISTC_CLK_FOUT_AO_SRC_DIV2 BIT(4)
256 #define NISTC_RTSI_TRIG_DIR(_c, _m) ((_m) ? BIT(8 + (_c)) : BIT(7 + (_c)))
257 #define NISTC_RTSI_TRIG_DIR_SUB_SEL1 BIT(2) /* only for M-Series */
258 #define NISTC_RTSI_TRIG_DIR_SUB_SEL1_SHIFT 2 /* only for M-Series */
259 #define NISTC_RTSI_TRIG_USE_CLK BIT(1)
260 #define NISTC_RTSI_TRIG_DRV_CLK BIT(0)
263 #define NISTC_INT_CTRL_INTB_ENA BIT(15)
265 #define NISTC_INT_CTRL_INTA_ENA BIT(11)
267 #define NISTC_INT_CTRL_PASSTHRU0_POL BIT(3)
268 #define NISTC_INT_CTRL_PASSTHRU1_POL BIT(2)
269 #define NISTC_INT_CTRL_3PIN_INT BIT(1)
270 #define NISTC_INT_CTRL_INT_POL BIT(0)
273 #define NISTC_AI_OUT_CTRL_START_SEL BIT(10)
285 #define NISTC_ATRIG_ETC_GPFO_1_ENA BIT(15)
286 #define NISTC_ATRIG_ETC_GPFO_0_ENA BIT(14)
287 #define NISTC_ATRIG_ETC_GPFO_0_SEL(x) (((x) & 0x7) << 11)
288 #define NISTC_ATRIG_ETC_GPFO_0_SEL_TO_SRC(x) (((x) >> 11) & 0x7)
289 #define NISTC_ATRIG_ETC_GPFO_1_SEL BIT(7)
291 #define NISTC_ATRIG_ETC_DRV BIT(4)
292 #define NISTC_ATRIG_ETC_ENA BIT(3)
298 #define NISTC_AI_START_POLARITY BIT(15)
299 #define NISTC_AI_STOP_POLARITY BIT(14)
300 #define NISTC_AI_STOP_SYNC BIT(13)
301 #define NISTC_AI_STOP_EDGE BIT(12)
303 #define NISTC_AI_START_SYNC BIT(6)
304 #define NISTC_AI_START_EDGE BIT(5)
308 #define NISTC_AI_TRIG_START1_POLARITY BIT(15)
309 #define NISTC_AI_TRIG_START2_POLARITY BIT(14)
310 #define NISTC_AI_TRIG_START2_SYNC BIT(13)
311 #define NISTC_AI_TRIG_START2_EDGE BIT(12)
313 #define NISTC_AI_TRIG_START1_SYNC BIT(6)
314 #define NISTC_AI_TRIG_START1_EDGE BIT(5)
320 #define NISTC_AO_START_UI2_SW_GATE BIT(15)
321 #define NISTC_AO_START_UI2_EXT_GATE_POL BIT(14)
322 #define NISTC_AO_START_POLARITY BIT(13)
323 #define NISTC_AO_START_AOFREQ_ENA BIT(12)
325 #define NISTC_AO_START_SYNC BIT(6)
326 #define NISTC_AO_START_EDGE BIT(5)
330 #define NISTC_AO_TRIG_UI2_EXT_GATE_ENA BIT(15)
331 #define NISTC_AO_TRIG_DELAYED_START1 BIT(14)
332 #define NISTC_AO_TRIG_START1_POLARITY BIT(13)
333 #define NISTC_AO_TRIG_UI2_SRC_POLARITY BIT(12)
335 #define NISTC_AO_TRIG_START1_SYNC BIT(6)
336 #define NISTC_AO_TRIG_START1_EDGE BIT(5)
344 #define NISTC_AO_MODE3_UI2_SW_NEXT_TC BIT(13)
345 #define NISTC_AO_MODE3_UC_SW_EVERY_BC_TC BIT(12)
346 #define NISTC_AO_MODE3_TRIG_LEN BIT(11)
347 #define NISTC_AO_MODE3_STOP_ON_OVERRUN_ERR BIT(5)
348 #define NISTC_AO_MODE3_STOP_ON_BC_TC_TRIG_ERR BIT(4)
349 #define NISTC_AO_MODE3_STOP_ON_BC_TC_ERR BIT(3)
350 #define NISTC_AO_MODE3_NOT_AN_UPDATE BIT(2)
351 #define NISTC_AO_MODE3_SW_GATE BIT(1)
352 #define NISTC_AO_MODE3_LAST_GATE_DISABLE BIT(0) /* M-Series only */
355 #define NISTC_RESET_SOFTWARE BIT(11)
356 #define NISTC_RESET_AO_CFG_END BIT(9)
357 #define NISTC_RESET_AI_CFG_END BIT(8)
358 #define NISTC_RESET_AO_CFG_START BIT(5)
359 #define NISTC_RESET_AI_CFG_START BIT(4)
360 #define NISTC_RESET_G1 BIT(3)
361 #define NISTC_RESET_G0 BIT(2)
362 #define NISTC_RESET_AO BIT(1)
363 #define NISTC_RESET_AI BIT(0)
367 #define NISTC_INTA_ENA_PASSTHRU0 BIT(9)
368 #define NISTC_INTA_ENA_G0_GATE BIT(8)
369 #define NISTC_INTA_ENA_AI_FIFO BIT(7)
370 #define NISTC_INTA_ENA_G0_TC BIT(6)
371 #define NISTC_INTA_ENA_AI_ERR BIT(5)
372 #define NISTC_INTA_ENA_AI_STOP BIT(4)
373 #define NISTC_INTA_ENA_AI_START BIT(3)
374 #define NISTC_INTA_ENA_AI_START2 BIT(2)
375 #define NISTC_INTA_ENA_AI_START1 BIT(1)
376 #define NISTC_INTA_ENA_AI_SC_TC BIT(0)
387 #define NISTC_INTB_ENA_PASSTHRU1 BIT(11)
388 #define NISTC_INTB_ENA_G1_GATE BIT(10)
389 #define NISTC_INTB_ENA_G1_TC BIT(9)
390 #define NISTC_INTB_ENA_AO_FIFO BIT(8)
391 #define NISTC_INTB_ENA_AO_UI2_TC BIT(7)
392 #define NISTC_INTB_ENA_AO_UC_TC BIT(6)
393 #define NISTC_INTB_ENA_AO_ERR BIT(5)
394 #define NISTC_INTB_ENA_AO_STOP BIT(4)
395 #define NISTC_INTB_ENA_AO_START BIT(3)
396 #define NISTC_INTB_ENA_AO_UPDATE BIT(2)
397 #define NISTC_INTB_ENA_AO_START1 BIT(1)
398 #define NISTC_INTB_ENA_AO_BC_TC BIT(0)
401 #define NISTC_AI_PERSONAL_SHIFTIN_PW BIT(15)
402 #define NISTC_AI_PERSONAL_EOC_POLARITY BIT(14)
403 #define NISTC_AI_PERSONAL_SOC_POLARITY BIT(13)
404 #define NISTC_AI_PERSONAL_SHIFTIN_POL BIT(12)
405 #define NISTC_AI_PERSONAL_CONVERT_TIMEBASE BIT(11)
406 #define NISTC_AI_PERSONAL_CONVERT_PW BIT(10)
407 #define NISTC_AI_PERSONAL_CONVERT_ORIG_PULSE BIT(9)
408 #define NISTC_AI_PERSONAL_FIFO_FLAGS_POL BIT(8)
409 #define NISTC_AI_PERSONAL_OVERRUN_MODE BIT(7)
410 #define NISTC_AI_PERSONAL_EXTMUX_CLK_PW BIT(6)
411 #define NISTC_AI_PERSONAL_LOCALMUX_CLK_PW BIT(5)
412 #define NISTC_AI_PERSONAL_AIFREQ_POL BIT(4)
415 #define NISTC_AO_PERSONAL_MULTI_DACS BIT(15) /* M-Series only */
416 #define NISTC_AO_PERSONAL_NUM_DAC BIT(14) /* 1:single; 0:dual */
417 #define NISTC_AO_PERSONAL_FAST_CPU BIT(13) /* M-Series reserved */
418 #define NISTC_AO_PERSONAL_TMRDACWR_PW BIT(12)
419 #define NISTC_AO_PERSONAL_FIFO_FLAGS_POL BIT(11) /* M-Series reserved */
420 #define NISTC_AO_PERSONAL_FIFO_ENA BIT(10)
421 #define NISTC_AO_PERSONAL_AOFREQ_POL BIT(9) /* M-Series reserved */
422 #define NISTC_AO_PERSONAL_DMA_PIO_CTRL BIT(8) /* M-Series reserved */
423 #define NISTC_AO_PERSONAL_UPDATE_ORIG_PULSE BIT(7)
424 #define NISTC_AO_PERSONAL_UPDATE_TIMEBASE BIT(6)
425 #define NISTC_AO_PERSONAL_UPDATE_PW BIT(5)
426 #define NISTC_AO_PERSONAL_BC_SRC_SEL BIT(4)
427 #define NISTC_AO_PERSONAL_INTERVAL_BUFFER_MODE BIT(3)
431 #define NISTC_RTSI_TRIGB_SUB_SEL1 BIT(15) /* not for M-Series */
432 #define NISTC_RTSI_TRIGB_SUB_SEL1_SHIFT 15 /* not for M-Series */
445 #define NISTC_AO_OUT_CTRL_EXT_GATE_ENA BIT(15)
449 #define NISTC_AO_OUT_CTRL_EXT_GATE_POL BIT(3)
450 #define NISTC_AO_OUT_CTRL_UPDATE2_TOGGLE BIT(2)
458 #define NISTC_AI_MODE3_TRIG_LEN BIT(15)
459 #define NISTC_AI_MODE3_DELAY_START BIT(14)
460 #define NISTC_AI_MODE3_SOFTWARE_GATE BIT(13)
461 #define NISTC_AI_MODE3_SI_TRIG_DELAY BIT(12)
462 #define NISTC_AI_MODE3_SI2_SRC_SEL BIT(11)
463 #define NISTC_AI_MODE3_DELAYED_START2 BIT(10)
464 #define NISTC_AI_MODE3_DELAYED_START1 BIT(9)
465 #define NISTC_AI_MODE3_EXT_GATE_MODE BIT(8)
471 #define NISTC_AI_MODE3_EXT_GATE_POL BIT(5)
475 #define NISTC_AI_STATUS1_INTA BIT(15)
476 #define NISTC_AI_STATUS1_FIFO_F BIT(14)
477 #define NISTC_AI_STATUS1_FIFO_HF BIT(13)
478 #define NISTC_AI_STATUS1_FIFO_E BIT(12)
479 #define NISTC_AI_STATUS1_OVERRUN BIT(11)
480 #define NISTC_AI_STATUS1_OVERFLOW BIT(10)
481 #define NISTC_AI_STATUS1_SC_TC_ERR BIT(9)
486 #define NISTC_AI_STATUS1_START2 BIT(8)
487 #define NISTC_AI_STATUS1_START1 BIT(7)
488 #define NISTC_AI_STATUS1_SC_TC BIT(6)
489 #define NISTC_AI_STATUS1_START BIT(5)
490 #define NISTC_AI_STATUS1_STOP BIT(4)
491 #define NISTC_AI_STATUS1_G0_TC BIT(3)
492 #define NISTC_AI_STATUS1_G0_GATE BIT(2)
493 #define NISTC_AI_STATUS1_FIFO_REQ BIT(1)
494 #define NISTC_AI_STATUS1_PASSTHRU0 BIT(0)
497 #define NISTC_AO_STATUS1_INTB BIT(15)
498 #define NISTC_AO_STATUS1_FIFO_F BIT(14)
499 #define NISTC_AO_STATUS1_FIFO_HF BIT(13)
500 #define NISTC_AO_STATUS1_FIFO_E BIT(12)
501 #define NISTC_AO_STATUS1_BC_TC_ERR BIT(11)
502 #define NISTC_AO_STATUS1_START BIT(10)
503 #define NISTC_AO_STATUS1_OVERRUN BIT(9)
504 #define NISTC_AO_STATUS1_START1 BIT(8)
505 #define NISTC_AO_STATUS1_BC_TC BIT(7)
506 #define NISTC_AO_STATUS1_UC_TC BIT(6)
507 #define NISTC_AO_STATUS1_UPDATE BIT(5)
508 #define NISTC_AO_STATUS1_UI2_TC BIT(4)
509 #define NISTC_AO_STATUS1_G1_TC BIT(3)
510 #define NISTC_AO_STATUS1_G1_GATE BIT(2)
511 #define NISTC_AO_STATUS1_FIFO_REQ BIT(1)
512 #define NISTC_AO_STATUS1_PASSTHRU1 BIT(0)
533 #define NISTC_STATUS1_SERIO_IN_PROG BIT(12)
538 #define NISTC_STATUS2_AO_TMRDACWRS_IN_PROGRESS BIT(5)
550 #define NI_E_STATUS_AI_FIFO_LOWER_NE BIT(3)
551 #define NI_E_STATUS_PROMOUT BIT(0)
564 #define NI_E_SERIAL_CMD_DAC_LD(x) BIT(3 + (x))
565 #define NI_E_SERIAL_CMD_EEPROM_CS BIT(2)
566 #define NI_E_SERIAL_CMD_SDATA BIT(1)
567 #define NI_E_SERIAL_CMD_SCLK BIT(0)
575 #define NI_E_AI_CFG_LO_LAST_CHAN BIT(15)
576 #define NI_E_AI_CFG_LO_GEN_TRIG BIT(12)
577 #define NI_E_AI_CFG_LO_DITHER BIT(9)
578 #define NI_E_AI_CFG_LO_UNI BIT(8)
586 #define NI_E_AI_CFG_HI_AC_COUPLE BIT(11)
591 #define NI_E_AO_GROUND_REF BIT(3)
592 #define NI_E_AO_EXT_REF BIT(2)
593 #define NI_E_AO_DEGLITCH BIT(1)
594 #define NI_E_AO_CFG_BIP BIT(0)
605 * 611x registers (these boards differ from the e-series)
633 #define NI6143_CALIB_CHAN_RELAY_ON BIT(15)
634 #define NI6143_CALIB_CHAN_RELAY_OFF BIT(14)
638 #define NI6143_CALIB_CHAN_PWM_GND NI6143_CALIB_CHAN(5) /* +-5V Self Cal */
659 #define NI611X_AO_MISC_CLEAR_WG BIT(0)
664 #define NI67XX_CAL_STATUS_BUSY BIT(0)
665 #define NI67XX_CAL_STATUS_OSC_DETECT BIT(1)
666 #define NI67XX_CAL_STATUS_OVERRANGE BIT(2)
671 #define CS5529_CMD_CB BIT(7)
672 #define CS5529_CMD_SINGLE_CONV BIT(6)
673 #define CS5529_CMD_CONT_CONV BIT(5)
674 #define CS5529_CMD_READ BIT(4)
677 #define CS5529_CMD_PWR_SAVE BIT(0)
685 #define CS5529_CFG_AOUT(x) BIT(22 + (x))
686 #define CS5529_CFG_DOUT(x) BIT(18 + (x))
687 #define CS5529_CFG_LOW_PWR_MODE BIT(16)
698 #define CS5529_CFG_UNIPOLAR BIT(12)
699 #define CS5529_CFG_RESET BIT(7)
700 #define CS5529_CFG_RESET_VALID BIT(6)
701 #define CS5529_CFG_PORT_FLAG BIT(5)
702 #define CS5529_CFG_PWR_SAVE_SEL BIT(4)
703 #define CS5529_CFG_DONE_FLAG BIT(3)
713 * M-Series specific registers not handled by the DAQ-STC and GPCT register
736 #define NI_M_AI_CFG_LAST_CHAN BIT(14)
737 #define NI_M_AI_CFG_DITHER BIT(13)
738 #define NI_M_AI_CFG_POLARITY BIT(12)
751 #define NI_M_INTC_ENA BIT(0)
753 #define NI_M_INTC_STATUS BIT(0)
768 #define NI_M_AO_CFG_BANK_BIPOLAR BIT(7)
769 #define NI_M_AO_CFG_BANK_UPDATE_TIMED BIT(6)
780 #define NI_M_CLK_FOUT2_RTSI_10MHZ BIT(7)
781 #define NI_M_CLK_FOUT2_TIMEBASE3_PLL BIT(6)
782 #define NI_M_CLK_FOUT2_TIMEBASE1_PLL BIT(5)
797 #define NI_M_PLL_CTRL_ENA BIT(12)
803 #define NI_M_PLL_STATUS_LOCKED BIT(0)
812 #define NI_M_CFG_BYPASS_FIFO BIT(31)
813 #define NI_M_CFG_BYPASS_AI_POLARITY BIT(22)
814 #define NI_M_CFG_BYPASS_AI_DITHER BIT(21)
836 #define NI_M_CDIO_STATUS_CDI_OVERFLOW BIT(20)
837 #define NI_M_CDIO_STATUS_CDI_OVERRUN BIT(19)
840 #define NI_M_CDIO_STATUS_CDI_FIFO_REQ BIT(18)
841 #define NI_M_CDIO_STATUS_CDI_FIFO_FULL BIT(17)
842 #define NI_M_CDIO_STATUS_CDI_FIFO_EMPTY BIT(16)
843 #define NI_M_CDIO_STATUS_CDO_UNDERFLOW BIT(4)
844 #define NI_M_CDIO_STATUS_CDO_OVERRUN BIT(3)
847 #define NI_M_CDIO_STATUS_CDO_FIFO_REQ BIT(2)
848 #define NI_M_CDIO_STATUS_CDO_FIFO_FULL BIT(1)
849 #define NI_M_CDIO_STATUS_CDO_FIFO_EMPTY BIT(0)
851 #define NI_M_CDI_CMD_SW_UPDATE BIT(20)
852 #define NI_M_CDO_CMD_SW_UPDATE BIT(19)
853 #define NI_M_CDO_CMD_F_E_INT_ENA_CLR BIT(17)
854 #define NI_M_CDO_CMD_F_E_INT_ENA_SET BIT(16)
855 #define NI_M_CDI_CMD_ERR_INT_CONFIRM BIT(15)
856 #define NI_M_CDO_CMD_ERR_INT_CONFIRM BIT(14)
857 #define NI_M_CDI_CMD_F_REQ_INT_ENA_CLR BIT(13)
858 #define NI_M_CDI_CMD_F_REQ_INT_ENA_SET BIT(12)
859 #define NI_M_CDO_CMD_F_REQ_INT_ENA_CLR BIT(11)
860 #define NI_M_CDO_CMD_F_REQ_INT_ENA_SET BIT(10)
861 #define NI_M_CDI_CMD_ERR_INT_ENA_CLR BIT(9)
862 #define NI_M_CDI_CMD_ERR_INT_ENA_SET BIT(8)
863 #define NI_M_CDO_CMD_ERR_INT_ENA_CLR BIT(7)
864 #define NI_M_CDO_CMD_ERR_INT_ENA_SET BIT(6)
865 #define NI_M_CDI_CMD_RESET BIT(5)
866 #define NI_M_CDO_CMD_RESET BIT(4)
867 #define NI_M_CDI_CMD_ARM BIT(3)
868 #define NI_M_CDI_CMD_DISARM BIT(2)
869 #define NI_M_CDO_CMD_ARM BIT(1)
870 #define NI_M_CDO_CMD_DISARM BIT(0)
880 #define NI_M_CDI_MODE_FIFO_MODE BIT(11)
881 #define NI_M_CDI_MODE_POLARITY BIT(10)
882 #define NI_M_CDI_MODE_HALT_ON_ERROR BIT(9)
894 #define NI_M_CDO_MODE_FIFO_MODE BIT(11)
895 #define NI_M_CDO_MODE_POLARITY BIT(10)
896 #define NI_M_CDO_MODE_HALT_ON_ERROR BIT(9)
897 #define NI_M_CDO_MODE_RETRANSMIT BIT(8)
904 #define NI_M_AO_REF_ATTENUATION_X5 BIT(0)
965 unsigned int dio_speed; /* not for e-series */
975 #define NUM_RTSI_SHARED_MUXS (NI_RTSI_BRD(-1) - NI_RTSI_BRD(0) + 1)
1081 * route requested. Furthermore, the only way that this auto-allocation
1082 * and configuration works is via the globally-named ni signal/terminal
1089 * For e-series, the bit layout of this register is
1091 * DAQ-STC, Jan 1999, 340934B-01):
1092 * bits 0:2 -- NI_RTSI_BRD(0) source selection
1093 * bits 3:5 -- NI_RTSI_BRD(1) source selection
1094 * bits 6:8 -- NI_RTSI_BRD(2) source selection
1095 * bits 9:11 -- NI_RTSI_BRD(3) source selection
1096 * bit 12 -- NI_RTSI_BRD(0) direction, 0:input, 1:output
1097 * bit 13 -- NI_RTSI_BRD(1) direction, 0:input, 1:output
1098 * bit 14 -- NI_RTSI_BRD(2) direction, 0:input, 1:output
1099 * bit 15 -- NI_RTSI_BRD(3) direction, 0:input, 1:output
1100 * According to DAQ-STC:
1101 * RTSI Board Interface--Configured as an input, each bidirectional
1105 * These pins provide a mechanism for additional board-level signals
1108 * - Neither the DAQ-STC nor the MHDDK is clear on what the direction
1113 * - The DAQ-STC also indicates that the NI_RTSI_BRD lines can be
1116 * NI-MAX, there appears to be only one family (so far) that has the
1120 * For m-series, the bit layout of this register is
1122 * bits 0:3 -- NI_RTSI_BRD(0) source selection
1123 * bits 4:7 -- NI_RTSI_BRD(1) source selection
1124 * bits 8:11 -- NI_RTSI_BRD(2) source selection
1125 * bits 12:15 -- NI_RTSI_BRD(3) source selection
1126 * Note: The m-series does not have any option to change direction of