1 // SPDX-License-Identifier: GPL-2.0-only
5  * Copyright (c) 2010-2013, NVIDIA Corporation.
15 #define pr_fmt(fmt)	"tegra-cpuidle: " fmt
68 	while (retries--) {  in tegra_cpuidle_wait_for_secondary_cpus_parking()
74 		 * shutdown in order to power-off CPU's cluster safely.  in tegra_cpuidle_wait_for_secondary_cpus_parking()
76 		 * it takes about 40-150us in average and over 1000us in  in tegra_cpuidle_wait_for_secondary_cpus_parking()
85 		} while (timeout_us--);  in tegra_cpuidle_wait_for_secondary_cpus_parking()
94 	return -ETIMEDOUT;  in tegra_cpuidle_wait_for_secondary_cpus_parking()
134 	if (err && err != -ENOSYS)  in tegra_cpuidle_c7_enter()
146 		 * pending SGI state across CPU cluster PM.  Abort and retry  in tegra_cpuidle_coupled_barrier()
157 		return -EINTR;  in tegra_cpuidle_coupled_barrier()
164 					       int index, unsigned int cpu)  in tegra_cpuidle_state_enter()  argument
169 	 * CC6 state is the "CPU cluster power-off" state.  In order to  in tegra_cpuidle_state_enter()
173 	 * logic that turns off the cluster's power domain (which includes  in tegra_cpuidle_state_enter()
176 	if (index == TEGRA_CC6) {  in tegra_cpuidle_state_enter()
188 	switch (index) {  in tegra_cpuidle_state_enter()
198 		err = -EINVAL;  in tegra_cpuidle_state_enter()
208 	return err ?: index;  in tegra_cpuidle_state_enter()
211 static int tegra_cpuidle_adjust_state_index(int index, unsigned int cpu)  in tegra_cpuidle_adjust_state_index()  argument
214 	 * On Tegra30 CPU0 can't be power-gated separately from secondary  in tegra_cpuidle_adjust_state_index()
215 	 * cores because it gates the whole CPU cluster.  in tegra_cpuidle_adjust_state_index()
217 	if (cpu > 0 || index != TEGRA_C7 || tegra_get_chip_id() != TEGRA30)  in tegra_cpuidle_adjust_state_index()
218 		return index;  in tegra_cpuidle_adjust_state_index()
222 		index = TEGRA_C1;  in tegra_cpuidle_adjust_state_index()
224 		index = TEGRA_CC6;  in tegra_cpuidle_adjust_state_index()
226 	return index;  in tegra_cpuidle_adjust_state_index()
231 					 int index)  in tegra_cpuidle_enter()  argument
233 	bool do_rcu = drv->states[index].flags & CPUIDLE_FLAG_RCU_IDLE;  in tegra_cpuidle_enter()
234 	unsigned int cpu = cpu_logical_map(dev->cpu);  in tegra_cpuidle_enter()
237 	index = tegra_cpuidle_adjust_state_index(index, cpu);  in tegra_cpuidle_enter()
238 	if (dev->states_usage[index].disable)  in tegra_cpuidle_enter()
239 		return -1;  in tegra_cpuidle_enter()
241 	if (index == TEGRA_C1) {  in tegra_cpuidle_enter()
244 		ret = arm_cpuidle_simple_enter(dev, drv, index);  in tegra_cpuidle_enter()
248 		ret = tegra_cpuidle_state_enter(dev, index, cpu);  in tegra_cpuidle_enter()
251 		if (ret != -EINTR || index != TEGRA_CC6)  in tegra_cpuidle_enter()
253 				    index, ret);  in tegra_cpuidle_enter()
254 		index = -1;  in tegra_cpuidle_enter()
256 		index = ret;  in tegra_cpuidle_enter()
259 	return index;  in tegra_cpuidle_enter()
264 				 int index)  in tegra114_enter_s2idle()  argument
266 	tegra_cpuidle_enter(dev, drv, index);  in tegra114_enter_s2idle()
279  * ---------
282  * LP2 | CC6	(CPU cluster power gating)
311 			.desc			= "CPU cluster powered off",
332 	if ((state_cc6->flags & CPUIDLE_FLAG_UNUSABLE) ||  in tegra_cpuidle_pcie_irqs_in_use()
344 	s->enter_s2idle = tegra114_enter_s2idle;  in tegra_cpuidle_setup_tegra114_c7_state()
345 	s->target_residency = 1000;  in tegra_cpuidle_setup_tegra114_c7_state()
346 	s->exit_latency = 500;  in tegra_cpuidle_setup_tegra114_c7_state()
352 		return -EPROBE_DEFER;  in tegra_cpuidle_probe()
354 	/* LP2 could be disabled in device-tree */  in tegra_cpuidle_probe()
359 	 * Required suspend-resume functionality, which is provided by the  in tegra_cpuidle_probe()
360 	 * Tegra-arch core and PMC driver, is unavailable if PM-sleep option  in tegra_cpuidle_probe()
370 	 * cluster power-off (CC6 or LP2) states are common for all Tegra SoCs.  in tegra_cpuidle_probe()
374 		/* Tegra20 isn't capable to power-off individual CPU cores */  in tegra_cpuidle_probe()
390 		return -EINVAL;  in tegra_cpuidle_probe()
399 		.name = "tegra-cpuidle",