Lines Matching +full:at91sam9g46 +full:- +full:sha
1 // SPDX-License-Identifier: GPL-2.0
7 * Copyright (c) 2012 Eukréa Electromatique - ATMEL
10 * Some ideas are from omap-aes.c driver.
30 #include <linux/dma-mapping.h>
41 #include "atmel-aes-regs.h"
42 #include "atmel-authenc.h"
265 snprintf(tmp, sz, "KEYWR[%u]", (offset - AES_KEYWR(0)) >> 2); in atmel_aes_reg_name()
272 snprintf(tmp, sz, "IDATAR[%u]", (offset - AES_IDATAR(0)) >> 2); in atmel_aes_reg_name()
279 snprintf(tmp, sz, "ODATAR[%u]", (offset - AES_ODATAR(0)) >> 2); in atmel_aes_reg_name()
286 snprintf(tmp, sz, "IVR[%u]", (offset - AES_IVR(0)) >> 2); in atmel_aes_reg_name()
299 snprintf(tmp, sz, "GHASHR[%u]", (offset - AES_GHASHR(0)) >> 2); in atmel_aes_reg_name()
306 snprintf(tmp, sz, "TAGR[%u]", (offset - AES_TAGR(0)) >> 2); in atmel_aes_reg_name()
316 snprintf(tmp, sz, "GCMHR[%u]", (offset - AES_GCMHR(0)) >> 2); in atmel_aes_reg_name()
326 snprintf(tmp, sz, "TWR[%u]", (offset - AES_TWR(0)) >> 2); in atmel_aes_reg_name()
333 snprintf(tmp, sz, "ALPHAR[%u]", (offset - AES_ALPHAR(0)) >> 2); in atmel_aes_reg_name()
349 u32 value = readl_relaxed(dd->io_base + offset); in atmel_aes_read()
352 if (dd->flags & AES_FLAGS_DUMP_REG) { in atmel_aes_read()
355 dev_vdbg(dd->dev, "read 0x%08x from %s\n", value, in atmel_aes_read()
367 if (dd->flags & AES_FLAGS_DUMP_REG) { in atmel_aes_write()
370 dev_vdbg(dd->dev, "write 0x%08x into %s\n", value, in atmel_aes_write()
375 writel_relaxed(value, dd->io_base + offset); in atmel_aes_write()
381 for (; count--; value++, offset += 4) in atmel_aes_read_n()
388 for (; count--; value++, offset += 4) in atmel_aes_write_n()
412 dd->resume = resume; in atmel_aes_wait_for_data_ready()
414 return -EINPROGRESS; in atmel_aes_wait_for_data_ready()
419 len &= block_size - 1; in atmel_aes_padlen()
420 return len ? block_size - len : 0; in atmel_aes_padlen()
439 err = clk_enable(dd->iclk); in atmel_aes_hw_init()
462 dd->hw_version = atmel_aes_get_version(dd); in atmel_aes_hw_version_init()
464 dev_info(dd->dev, "version: 0x%x\n", dd->hw_version); in atmel_aes_hw_version_init()
466 clk_disable(dd->iclk); in atmel_aes_hw_version_init()
474 dd->flags = (dd->flags & AES_FLAGS_PERSISTENT) | rctx->mode; in atmel_aes_set_mode()
479 return (dd->flags & AES_FLAGS_ENCRYPT); in atmel_aes_is_encrypt()
488 struct skcipher_request *req = skcipher_request_cast(dd->areq); in atmel_aes_set_iv_as_last_ciphertext_block()
493 if (req->cryptlen < ivsize) in atmel_aes_set_iv_as_last_ciphertext_block()
496 if (rctx->mode & AES_FLAGS_ENCRYPT) in atmel_aes_set_iv_as_last_ciphertext_block()
497 scatterwalk_map_and_copy(req->iv, req->dst, in atmel_aes_set_iv_as_last_ciphertext_block()
498 req->cryptlen - ivsize, ivsize, 0); in atmel_aes_set_iv_as_last_ciphertext_block()
500 memcpy(req->iv, rctx->lastc, ivsize); in atmel_aes_set_iv_as_last_ciphertext_block()
511 struct atmel_aes_ctr_ctx *ctx = atmel_aes_ctr_ctx_cast(dd->ctx); in atmel_aes_ctr_update_req_iv()
512 struct skcipher_request *req = skcipher_request_cast(dd->areq); in atmel_aes_ctr_update_req_iv()
520 * here, ctx->blocks contains the number of blocks of the last fragment in atmel_aes_ctr_update_req_iv()
523 for (i = 0; i < ctx->blocks; i++) in atmel_aes_ctr_update_req_iv()
524 crypto_inc((u8 *)ctx->iv, AES_BLOCK_SIZE); in atmel_aes_ctr_update_req_iv()
526 memcpy(req->iv, ctx->iv, ivsize); in atmel_aes_ctr_update_req_iv()
531 struct skcipher_request *req = skcipher_request_cast(dd->areq); in atmel_aes_complete()
535 if (dd->ctx->is_aead) in atmel_aes_complete()
539 clk_disable(dd->iclk); in atmel_aes_complete()
540 dd->flags &= ~AES_FLAGS_BUSY; in atmel_aes_complete()
542 if (!err && !dd->ctx->is_aead && in atmel_aes_complete()
543 (rctx->mode & AES_FLAGS_OPMODE_MASK) != AES_FLAGS_ECB) { in atmel_aes_complete()
544 if ((rctx->mode & AES_FLAGS_OPMODE_MASK) != AES_FLAGS_CTR) in atmel_aes_complete()
550 if (dd->is_async) in atmel_aes_complete()
551 crypto_request_complete(dd->areq, err); in atmel_aes_complete()
553 tasklet_schedule(&dd->queue_task); in atmel_aes_complete()
571 valmr |= dd->flags & AES_FLAGS_MODE_MASK; in atmel_aes_write_ctrl_key()
575 if (dd->caps.has_dualbuff) in atmel_aes_write_ctrl_key()
594 dd->ctx->key, dd->ctx->keylen); in atmel_aes_write_ctrl()
605 atmel_aes_read_block(dd, AES_ODATAR(0), dd->data); in atmel_aes_cpu_transfer()
606 dd->data += 4; in atmel_aes_cpu_transfer()
607 dd->datalen -= AES_BLOCK_SIZE; in atmel_aes_cpu_transfer()
609 if (dd->datalen < AES_BLOCK_SIZE) in atmel_aes_cpu_transfer()
612 atmel_aes_write_block(dd, AES_IDATAR(0), dd->data); in atmel_aes_cpu_transfer()
616 dd->resume = atmel_aes_cpu_transfer; in atmel_aes_cpu_transfer()
618 return -EINPROGRESS; in atmel_aes_cpu_transfer()
622 if (!sg_copy_from_buffer(dd->real_dst, sg_nents(dd->real_dst), in atmel_aes_cpu_transfer()
623 dd->buf, dd->total)) in atmel_aes_cpu_transfer()
624 err = -EINVAL; in atmel_aes_cpu_transfer()
629 return dd->cpu_transfer_complete(dd); in atmel_aes_cpu_transfer()
641 return -EINVAL; in atmel_aes_cpu_start()
643 sg_copy_to_buffer(src, sg_nents(src), dd->buf, len); in atmel_aes_cpu_start()
645 dd->total = len; in atmel_aes_cpu_start()
646 dd->real_dst = dst; in atmel_aes_cpu_start()
647 dd->cpu_transfer_complete = resume; in atmel_aes_cpu_start()
648 dd->datalen = len + padlen; in atmel_aes_cpu_start()
649 dd->data = (u32 *)dd->buf; in atmel_aes_cpu_start()
650 atmel_aes_write_block(dd, AES_IDATAR(0), dd->data); in atmel_aes_cpu_start()
666 if (!IS_ALIGNED(len, dd->ctx->block_size)) in atmel_aes_check_aligned()
670 if (!IS_ALIGNED(sg->offset, sizeof(u32))) in atmel_aes_check_aligned()
673 if (len <= sg->length) { in atmel_aes_check_aligned()
674 if (!IS_ALIGNED(len, dd->ctx->block_size)) in atmel_aes_check_aligned()
677 dma->nents = nents+1; in atmel_aes_check_aligned()
678 dma->remainder = sg->length - len; in atmel_aes_check_aligned()
679 sg->length = len; in atmel_aes_check_aligned()
683 if (!IS_ALIGNED(sg->length, dd->ctx->block_size)) in atmel_aes_check_aligned()
686 len -= sg->length; in atmel_aes_check_aligned()
694 struct scatterlist *sg = dma->sg; in atmel_aes_restore_sg()
695 int nents = dma->nents; in atmel_aes_restore_sg()
697 if (!dma->remainder) in atmel_aes_restore_sg()
700 while (--nents > 0 && sg) in atmel_aes_restore_sg()
706 sg->length += dma->remainder; in atmel_aes_restore_sg()
717 dd->total = len; in atmel_aes_map()
718 dd->src.sg = src; in atmel_aes_map()
719 dd->dst.sg = dst; in atmel_aes_map()
720 dd->real_dst = dst; in atmel_aes_map()
722 src_aligned = atmel_aes_check_aligned(dd, src, len, &dd->src); in atmel_aes_map()
726 dst_aligned = atmel_aes_check_aligned(dd, dst, len, &dd->dst); in atmel_aes_map()
728 padlen = atmel_aes_padlen(len, dd->ctx->block_size); in atmel_aes_map()
730 if (dd->buflen < len + padlen) in atmel_aes_map()
731 return -ENOMEM; in atmel_aes_map()
734 sg_copy_to_buffer(src, sg_nents(src), dd->buf, len); in atmel_aes_map()
735 dd->src.sg = &dd->aligned_sg; in atmel_aes_map()
736 dd->src.nents = 1; in atmel_aes_map()
737 dd->src.remainder = 0; in atmel_aes_map()
741 dd->dst.sg = &dd->aligned_sg; in atmel_aes_map()
742 dd->dst.nents = 1; in atmel_aes_map()
743 dd->dst.remainder = 0; in atmel_aes_map()
746 sg_init_table(&dd->aligned_sg, 1); in atmel_aes_map()
747 sg_set_buf(&dd->aligned_sg, dd->buf, len + padlen); in atmel_aes_map()
750 if (dd->src.sg == dd->dst.sg) { in atmel_aes_map()
751 dd->src.sg_len = dma_map_sg(dd->dev, dd->src.sg, dd->src.nents, in atmel_aes_map()
753 dd->dst.sg_len = dd->src.sg_len; in atmel_aes_map()
754 if (!dd->src.sg_len) in atmel_aes_map()
755 return -EFAULT; in atmel_aes_map()
757 dd->src.sg_len = dma_map_sg(dd->dev, dd->src.sg, dd->src.nents, in atmel_aes_map()
759 if (!dd->src.sg_len) in atmel_aes_map()
760 return -EFAULT; in atmel_aes_map()
762 dd->dst.sg_len = dma_map_sg(dd->dev, dd->dst.sg, dd->dst.nents, in atmel_aes_map()
764 if (!dd->dst.sg_len) { in atmel_aes_map()
765 dma_unmap_sg(dd->dev, dd->src.sg, dd->src.nents, in atmel_aes_map()
767 return -EFAULT; in atmel_aes_map()
776 if (dd->src.sg == dd->dst.sg) { in atmel_aes_unmap()
777 dma_unmap_sg(dd->dev, dd->src.sg, dd->src.nents, in atmel_aes_unmap()
780 if (dd->src.sg != &dd->aligned_sg) in atmel_aes_unmap()
781 atmel_aes_restore_sg(&dd->src); in atmel_aes_unmap()
783 dma_unmap_sg(dd->dev, dd->dst.sg, dd->dst.nents, in atmel_aes_unmap()
786 if (dd->dst.sg != &dd->aligned_sg) in atmel_aes_unmap()
787 atmel_aes_restore_sg(&dd->dst); in atmel_aes_unmap()
789 dma_unmap_sg(dd->dev, dd->src.sg, dd->src.nents, in atmel_aes_unmap()
792 if (dd->src.sg != &dd->aligned_sg) in atmel_aes_unmap()
793 atmel_aes_restore_sg(&dd->src); in atmel_aes_unmap()
796 if (dd->dst.sg == &dd->aligned_sg) in atmel_aes_unmap()
797 sg_copy_from_buffer(dd->real_dst, sg_nents(dd->real_dst), in atmel_aes_unmap()
798 dd->buf, dd->total); in atmel_aes_unmap()
820 dma = &dd->src; in atmel_aes_dma_transfer_start()
822 config.dst_addr = dd->phys_base + AES_IDATAR(0); in atmel_aes_dma_transfer_start()
826 dma = &dd->dst; in atmel_aes_dma_transfer_start()
828 config.src_addr = dd->phys_base + AES_ODATAR(0); in atmel_aes_dma_transfer_start()
832 return -EINVAL; in atmel_aes_dma_transfer_start()
835 err = dmaengine_slave_config(dma->chan, &config); in atmel_aes_dma_transfer_start()
839 desc = dmaengine_prep_slave_sg(dma->chan, dma->sg, dma->sg_len, dir, in atmel_aes_dma_transfer_start()
842 return -ENOMEM; in atmel_aes_dma_transfer_start()
844 desc->callback = callback; in atmel_aes_dma_transfer_start()
845 desc->callback_param = dd; in atmel_aes_dma_transfer_start()
847 dma_async_issue_pending(dma->chan); in atmel_aes_dma_transfer_start()
862 switch (dd->ctx->block_size) { in atmel_aes_dma_start()
881 maxburst = dd->caps.max_burst_size; in atmel_aes_dma_start()
885 err = -EINVAL; in atmel_aes_dma_start()
893 dd->resume = resume; in atmel_aes_dma_start()
907 return -EINPROGRESS; in atmel_aes_dma_start()
910 dmaengine_terminate_sync(dd->dst.chan); in atmel_aes_dma_start()
922 dd->is_async = true; in atmel_aes_dma_callback()
923 (void)dd->resume(dd); in atmel_aes_dma_callback()
935 spin_lock_irqsave(&dd->lock, flags); in atmel_aes_handle_queue()
937 ret = crypto_enqueue_request(&dd->queue, new_areq); in atmel_aes_handle_queue()
938 if (dd->flags & AES_FLAGS_BUSY) { in atmel_aes_handle_queue()
939 spin_unlock_irqrestore(&dd->lock, flags); in atmel_aes_handle_queue()
942 backlog = crypto_get_backlog(&dd->queue); in atmel_aes_handle_queue()
943 areq = crypto_dequeue_request(&dd->queue); in atmel_aes_handle_queue()
945 dd->flags |= AES_FLAGS_BUSY; in atmel_aes_handle_queue()
946 spin_unlock_irqrestore(&dd->lock, flags); in atmel_aes_handle_queue()
952 crypto_request_complete(backlog, -EINPROGRESS); in atmel_aes_handle_queue()
954 ctx = crypto_tfm_ctx(areq->tfm); in atmel_aes_handle_queue()
956 dd->areq = areq; in atmel_aes_handle_queue()
957 dd->ctx = ctx; in atmel_aes_handle_queue()
959 dd->is_async = start_async; in atmel_aes_handle_queue()
961 /* WARNING: ctx->start() MAY change dd->is_async. */ in atmel_aes_handle_queue()
962 err = ctx->start(dd); in atmel_aes_handle_queue()
976 struct skcipher_request *req = skcipher_request_cast(dd->areq); in atmel_aes_start()
978 bool use_dma = (req->cryptlen >= ATMEL_AES_DMA_THRESHOLD || in atmel_aes_start()
979 dd->ctx->block_size != AES_BLOCK_SIZE); in atmel_aes_start()
988 atmel_aes_write_ctrl(dd, use_dma, (void *)req->iv); in atmel_aes_start()
990 return atmel_aes_dma_start(dd, req->src, req->dst, in atmel_aes_start()
991 req->cryptlen, in atmel_aes_start()
994 return atmel_aes_cpu_start(dd, req->src, req->dst, req->cryptlen, in atmel_aes_start()
1000 struct atmel_aes_ctr_ctx *ctx = atmel_aes_ctr_ctx_cast(dd->ctx); in atmel_aes_ctr_transfer()
1001 struct skcipher_request *req = skcipher_request_cast(dd->areq); in atmel_aes_ctr_transfer()
1009 ctx->offset += dd->total; in atmel_aes_ctr_transfer()
1010 if (ctx->offset >= req->cryptlen) in atmel_aes_ctr_transfer()
1014 datalen = req->cryptlen - ctx->offset; in atmel_aes_ctr_transfer()
1015 ctx->blocks = DIV_ROUND_UP(datalen, AES_BLOCK_SIZE); in atmel_aes_ctr_transfer()
1016 ctr = be32_to_cpu(ctx->iv[3]); in atmel_aes_ctr_transfer()
1020 end = start + ctx->blocks - 1; in atmel_aes_ctr_transfer()
1022 if (ctx->blocks >> 16 || end < start) { in atmel_aes_ctr_transfer()
1024 datalen = AES_BLOCK_SIZE * (0x10000 - start); in atmel_aes_ctr_transfer()
1031 src = scatterwalk_ffwd(ctx->src, req->src, ctx->offset); in atmel_aes_ctr_transfer()
1032 dst = ((req->src == req->dst) ? src : in atmel_aes_ctr_transfer()
1033 scatterwalk_ffwd(ctx->dst, req->dst, ctx->offset)); in atmel_aes_ctr_transfer()
1036 atmel_aes_write_ctrl(dd, use_dma, ctx->iv); in atmel_aes_ctr_transfer()
1042 ctx->iv[3] = cpu_to_be32(ctr); in atmel_aes_ctr_transfer()
1043 crypto_inc((u8 *)ctx->iv, AES_BLOCK_SIZE); in atmel_aes_ctr_transfer()
1056 struct atmel_aes_ctr_ctx *ctx = atmel_aes_ctr_ctx_cast(dd->ctx); in atmel_aes_ctr_start()
1057 struct skcipher_request *req = skcipher_request_cast(dd->areq); in atmel_aes_ctr_start()
1067 memcpy(ctx->iv, req->iv, AES_BLOCK_SIZE); in atmel_aes_ctr_start()
1068 ctx->offset = 0; in atmel_aes_ctr_start()
1069 dd->total = 0; in atmel_aes_ctr_start()
1079 skcipher_request_set_tfm(&rctx->fallback_req, ctx->fallback_tfm); in atmel_aes_xts_fallback()
1080 skcipher_request_set_callback(&rctx->fallback_req, req->base.flags, in atmel_aes_xts_fallback()
1081 req->base.complete, req->base.data); in atmel_aes_xts_fallback()
1082 skcipher_request_set_crypt(&rctx->fallback_req, req->src, req->dst, in atmel_aes_xts_fallback()
1083 req->cryptlen, req->iv); in atmel_aes_xts_fallback()
1085 return enc ? crypto_skcipher_encrypt(&rctx->fallback_req) : in atmel_aes_xts_fallback()
1086 crypto_skcipher_decrypt(&rctx->fallback_req); in atmel_aes_xts_fallback()
1097 if (req->cryptlen < XTS_BLOCK_SIZE) in atmel_aes_crypt()
1098 return -EINVAL; in atmel_aes_crypt()
1100 if (!IS_ALIGNED(req->cryptlen, XTS_BLOCK_SIZE)) in atmel_aes_crypt()
1109 if (!req->cryptlen && opmode != AES_FLAGS_XTS) in atmel_aes_crypt()
1113 !IS_ALIGNED(req->cryptlen, crypto_skcipher_blocksize(skcipher))) in atmel_aes_crypt()
1114 return -EINVAL; in atmel_aes_crypt()
1118 ctx->block_size = CFB8_BLOCK_SIZE; in atmel_aes_crypt()
1122 ctx->block_size = CFB16_BLOCK_SIZE; in atmel_aes_crypt()
1126 ctx->block_size = CFB32_BLOCK_SIZE; in atmel_aes_crypt()
1130 ctx->block_size = CFB64_BLOCK_SIZE; in atmel_aes_crypt()
1134 ctx->block_size = AES_BLOCK_SIZE; in atmel_aes_crypt()
1137 ctx->is_aead = false; in atmel_aes_crypt()
1140 rctx->mode = mode; in atmel_aes_crypt()
1146 if (req->cryptlen >= ivsize) in atmel_aes_crypt()
1147 scatterwalk_map_and_copy(rctx->lastc, req->src, in atmel_aes_crypt()
1148 req->cryptlen - ivsize, in atmel_aes_crypt()
1152 return atmel_aes_handle_queue(ctx->dd, &req->base); in atmel_aes_crypt()
1163 return -EINVAL; in atmel_aes_setkey()
1165 memcpy(ctx->key, key, keylen); in atmel_aes_setkey()
1166 ctx->keylen = keylen; in atmel_aes_setkey()
1266 dd = atmel_aes_dev_alloc(&ctx->base); in atmel_aes_init_tfm()
1268 return -ENODEV; in atmel_aes_init_tfm()
1271 ctx->base.dd = dd; in atmel_aes_init_tfm()
1272 ctx->base.start = atmel_aes_start; in atmel_aes_init_tfm()
1282 dd = atmel_aes_dev_alloc(&ctx->base); in atmel_aes_ctr_init_tfm()
1284 return -ENODEV; in atmel_aes_ctr_init_tfm()
1287 ctx->base.dd = dd; in atmel_aes_ctr_init_tfm()
1288 ctx->base.start = atmel_aes_ctr_start; in atmel_aes_ctr_init_tfm()
1296 .base.cra_driver_name = "atmel-ecb-aes",
1309 .base.cra_driver_name = "atmel-cbc-aes",
1323 .base.cra_driver_name = "atmel-ofb-aes",
1337 .base.cra_driver_name = "atmel-cfb-aes",
1351 .base.cra_driver_name = "atmel-cfb32-aes",
1365 .base.cra_driver_name = "atmel-cfb16-aes",
1379 .base.cra_driver_name = "atmel-cfb8-aes",
1393 .base.cra_driver_name = "atmel-ctr-aes",
1409 .base.cra_driver_name = "atmel-cfb64-aes",
1451 struct atmel_aes_gcm_ctx *ctx = atmel_aes_gcm_ctx_cast(dd->ctx); in atmel_aes_gcm_ghash()
1453 dd->data = (u32 *)data; in atmel_aes_gcm_ghash()
1454 dd->datalen = datalen; in atmel_aes_gcm_ghash()
1455 ctx->ghash_in = ghash_in; in atmel_aes_gcm_ghash()
1456 ctx->ghash_out = ghash_out; in atmel_aes_gcm_ghash()
1457 ctx->ghash_resume = resume; in atmel_aes_gcm_ghash()
1465 struct atmel_aes_gcm_ctx *ctx = atmel_aes_gcm_ctx_cast(dd->ctx); in atmel_aes_gcm_ghash_init()
1468 atmel_aes_write(dd, AES_AADLENR, dd->total); in atmel_aes_gcm_ghash_init()
1472 if (ctx->ghash_in) in atmel_aes_gcm_ghash_init()
1473 atmel_aes_write_block(dd, AES_GHASHR(0), ctx->ghash_in); in atmel_aes_gcm_ghash_init()
1480 struct atmel_aes_gcm_ctx *ctx = atmel_aes_gcm_ctx_cast(dd->ctx); in atmel_aes_gcm_ghash_finalize()
1484 while (dd->datalen > 0) { in atmel_aes_gcm_ghash_finalize()
1485 atmel_aes_write_block(dd, AES_IDATAR(0), dd->data); in atmel_aes_gcm_ghash_finalize()
1486 dd->data += 4; in atmel_aes_gcm_ghash_finalize()
1487 dd->datalen -= AES_BLOCK_SIZE; in atmel_aes_gcm_ghash_finalize()
1491 dd->resume = atmel_aes_gcm_ghash_finalize; in atmel_aes_gcm_ghash_finalize()
1493 return -EINPROGRESS; in atmel_aes_gcm_ghash_finalize()
1498 atmel_aes_read_block(dd, AES_GHASHR(0), ctx->ghash_out); in atmel_aes_gcm_ghash_finalize()
1500 return ctx->ghash_resume(dd); in atmel_aes_gcm_ghash_finalize()
1506 struct atmel_aes_gcm_ctx *ctx = atmel_aes_gcm_ctx_cast(dd->ctx); in atmel_aes_gcm_start()
1507 struct aead_request *req = aead_request_cast(dd->areq); in atmel_aes_gcm_start()
1512 const void *iv = req->iv; in atmel_aes_gcm_start()
1513 u8 *data = dd->buf; in atmel_aes_gcm_start()
1523 memcpy(ctx->j0, iv, ivsize); in atmel_aes_gcm_start()
1524 ctx->j0[3] = cpu_to_be32(1); in atmel_aes_gcm_start()
1530 if (datalen > dd->buflen) in atmel_aes_gcm_start()
1531 return atmel_aes_complete(dd, -EINVAL); in atmel_aes_gcm_start()
1535 ((__be64 *)(data + datalen))[-1] = cpu_to_be64(ivsize * 8); in atmel_aes_gcm_start()
1538 NULL, ctx->j0, atmel_aes_gcm_process); in atmel_aes_gcm_start()
1543 struct atmel_aes_gcm_ctx *ctx = atmel_aes_gcm_ctx_cast(dd->ctx); in atmel_aes_gcm_process()
1544 struct aead_request *req = aead_request_cast(dd->areq); in atmel_aes_gcm_process()
1551 ctx->textlen = req->cryptlen - (enc ? 0 : authsize); in atmel_aes_gcm_process()
1557 if (likely(req->assoclen != 0 || ctx->textlen != 0)) in atmel_aes_gcm_process()
1558 dd->flags |= AES_FLAGS_GTAGEN; in atmel_aes_gcm_process()
1566 struct atmel_aes_gcm_ctx *ctx = atmel_aes_gcm_ctx_cast(dd->ctx); in atmel_aes_gcm_length()
1567 struct aead_request *req = aead_request_cast(dd->areq); in atmel_aes_gcm_length()
1568 __be32 j0_lsw, *j0 = ctx->j0; in atmel_aes_gcm_length()
1578 atmel_aes_write(dd, AES_AADLENR, req->assoclen); in atmel_aes_gcm_length()
1579 atmel_aes_write(dd, AES_CLENR, ctx->textlen); in atmel_aes_gcm_length()
1582 if (unlikely(req->assoclen == 0)) { in atmel_aes_gcm_length()
1583 dd->datalen = 0; in atmel_aes_gcm_length()
1588 padlen = atmel_aes_padlen(req->assoclen, AES_BLOCK_SIZE); in atmel_aes_gcm_length()
1589 if (unlikely(req->assoclen + padlen > dd->buflen)) in atmel_aes_gcm_length()
1590 return atmel_aes_complete(dd, -EINVAL); in atmel_aes_gcm_length()
1591 sg_copy_to_buffer(req->src, sg_nents(req->src), dd->buf, req->assoclen); in atmel_aes_gcm_length()
1594 dd->data = (u32 *)dd->buf; in atmel_aes_gcm_length()
1595 dd->datalen = req->assoclen + padlen; in atmel_aes_gcm_length()
1601 struct atmel_aes_gcm_ctx *ctx = atmel_aes_gcm_ctx_cast(dd->ctx); in atmel_aes_gcm_data()
1602 struct aead_request *req = aead_request_cast(dd->areq); in atmel_aes_gcm_data()
1603 bool use_dma = (ctx->textlen >= ATMEL_AES_DMA_THRESHOLD); in atmel_aes_gcm_data()
1608 while (dd->datalen > 0) { in atmel_aes_gcm_data()
1609 atmel_aes_write_block(dd, AES_IDATAR(0), dd->data); in atmel_aes_gcm_data()
1610 dd->data += 4; in atmel_aes_gcm_data()
1611 dd->datalen -= AES_BLOCK_SIZE; in atmel_aes_gcm_data()
1615 dd->resume = atmel_aes_gcm_data; in atmel_aes_gcm_data()
1617 return -EINPROGRESS; in atmel_aes_gcm_data()
1622 if (unlikely(ctx->textlen == 0)) in atmel_aes_gcm_data()
1626 src = scatterwalk_ffwd(ctx->src, req->src, req->assoclen); in atmel_aes_gcm_data()
1627 dst = ((req->src == req->dst) ? src : in atmel_aes_gcm_data()
1628 scatterwalk_ffwd(ctx->dst, req->dst, req->assoclen)); in atmel_aes_gcm_data()
1635 if (dd->caps.has_dualbuff) in atmel_aes_gcm_data()
1639 return atmel_aes_dma_start(dd, src, dst, ctx->textlen, in atmel_aes_gcm_data()
1643 return atmel_aes_cpu_start(dd, src, dst, ctx->textlen, in atmel_aes_gcm_data()
1649 struct atmel_aes_gcm_ctx *ctx = atmel_aes_gcm_ctx_cast(dd->ctx); in atmel_aes_gcm_tag_init()
1650 struct aead_request *req = aead_request_cast(dd->areq); in atmel_aes_gcm_tag_init()
1651 __be64 *data = dd->buf; in atmel_aes_gcm_tag_init()
1653 if (likely(dd->flags & AES_FLAGS_GTAGEN)) { in atmel_aes_gcm_tag_init()
1655 dd->resume = atmel_aes_gcm_tag_init; in atmel_aes_gcm_tag_init()
1657 return -EINPROGRESS; in atmel_aes_gcm_tag_init()
1664 atmel_aes_read_block(dd, AES_GHASHR(0), ctx->ghash); in atmel_aes_gcm_tag_init()
1666 data[0] = cpu_to_be64(req->assoclen * 8); in atmel_aes_gcm_tag_init()
1667 data[1] = cpu_to_be64(ctx->textlen * 8); in atmel_aes_gcm_tag_init()
1670 ctx->ghash, ctx->ghash, atmel_aes_gcm_tag); in atmel_aes_gcm_tag_init()
1675 struct atmel_aes_gcm_ctx *ctx = atmel_aes_gcm_ctx_cast(dd->ctx); in atmel_aes_gcm_tag()
1682 flags = dd->flags; in atmel_aes_gcm_tag()
1683 dd->flags &= ~(AES_FLAGS_OPMODE_MASK | AES_FLAGS_GTAGEN); in atmel_aes_gcm_tag()
1684 dd->flags |= AES_FLAGS_CTR; in atmel_aes_gcm_tag()
1685 atmel_aes_write_ctrl(dd, false, ctx->j0); in atmel_aes_gcm_tag()
1686 dd->flags = flags; in atmel_aes_gcm_tag()
1688 atmel_aes_write_block(dd, AES_IDATAR(0), ctx->ghash); in atmel_aes_gcm_tag()
1694 struct atmel_aes_gcm_ctx *ctx = atmel_aes_gcm_ctx_cast(dd->ctx); in atmel_aes_gcm_finalize()
1695 struct aead_request *req = aead_request_cast(dd->areq); in atmel_aes_gcm_finalize()
1698 u32 offset, authsize, itag[4], *otag = ctx->tag; in atmel_aes_gcm_finalize()
1702 if (likely(dd->flags & AES_FLAGS_GTAGEN)) in atmel_aes_gcm_finalize()
1703 atmel_aes_read_block(dd, AES_TAGR(0), ctx->tag); in atmel_aes_gcm_finalize()
1705 atmel_aes_read_block(dd, AES_ODATAR(0), ctx->tag); in atmel_aes_gcm_finalize()
1707 offset = req->assoclen + ctx->textlen; in atmel_aes_gcm_finalize()
1710 scatterwalk_map_and_copy(otag, req->dst, offset, authsize, 1); in atmel_aes_gcm_finalize()
1713 scatterwalk_map_and_copy(itag, req->src, offset, authsize, 0); in atmel_aes_gcm_finalize()
1714 err = crypto_memneq(itag, otag, authsize) ? -EBADMSG : 0; in atmel_aes_gcm_finalize()
1727 ctx->block_size = AES_BLOCK_SIZE; in atmel_aes_gcm_crypt()
1728 ctx->is_aead = true; in atmel_aes_gcm_crypt()
1731 rctx->mode = AES_FLAGS_GCM | mode; in atmel_aes_gcm_crypt()
1733 return atmel_aes_handle_queue(ctx->dd, &req->base); in atmel_aes_gcm_crypt()
1744 return -EINVAL; in atmel_aes_gcm_setkey()
1746 memcpy(ctx->key, key, keylen); in atmel_aes_gcm_setkey()
1747 ctx->keylen = keylen; in atmel_aes_gcm_setkey()
1773 dd = atmel_aes_dev_alloc(&ctx->base); in atmel_aes_gcm_init()
1775 return -ENODEV; in atmel_aes_gcm_init()
1778 ctx->base.dd = dd; in atmel_aes_gcm_init()
1779 ctx->base.start = atmel_aes_gcm_start; in atmel_aes_gcm_init()
1795 .cra_driver_name = "atmel-gcm-aes",
1814 struct atmel_aes_xts_ctx *ctx = atmel_aes_xts_ctx_cast(dd->ctx); in atmel_aes_xts_start()
1815 struct skcipher_request *req = skcipher_request_cast(dd->areq); in atmel_aes_xts_start()
1826 /* Compute the tweak value from req->iv with ecb(aes). */ in atmel_aes_xts_start()
1827 flags = dd->flags; in atmel_aes_xts_start()
1828 dd->flags &= ~AES_FLAGS_MODE_MASK; in atmel_aes_xts_start()
1829 dd->flags |= (AES_FLAGS_ECB | AES_FLAGS_ENCRYPT); in atmel_aes_xts_start()
1831 ctx->key2, ctx->base.keylen); in atmel_aes_xts_start()
1832 dd->flags = flags; in atmel_aes_xts_start()
1834 atmel_aes_write_block(dd, AES_IDATAR(0), req->iv); in atmel_aes_xts_start()
1840 struct skcipher_request *req = skcipher_request_cast(dd->areq); in atmel_aes_xts_process_data()
1841 bool use_dma = (req->cryptlen >= ATMEL_AES_DMA_THRESHOLD); in atmel_aes_xts_process_data()
1855 swap(tweak_bytes[i], tweak_bytes[AES_BLOCK_SIZE - 1 - i]); in atmel_aes_xts_process_data()
1862 return atmel_aes_dma_start(dd, req->src, req->dst, in atmel_aes_xts_process_data()
1863 req->cryptlen, in atmel_aes_xts_process_data()
1866 return atmel_aes_cpu_start(dd, req->src, req->dst, req->cryptlen, in atmel_aes_xts_process_data()
1880 crypto_skcipher_clear_flags(ctx->fallback_tfm, CRYPTO_TFM_REQ_MASK); in atmel_aes_xts_setkey()
1881 crypto_skcipher_set_flags(ctx->fallback_tfm, tfm->base.crt_flags & in atmel_aes_xts_setkey()
1883 err = crypto_skcipher_setkey(ctx->fallback_tfm, key, keylen); in atmel_aes_xts_setkey()
1887 memcpy(ctx->base.key, key, keylen/2); in atmel_aes_xts_setkey()
1888 memcpy(ctx->key2, key + keylen/2, keylen/2); in atmel_aes_xts_setkey()
1889 ctx->base.keylen = keylen/2; in atmel_aes_xts_setkey()
1908 const char *tfm_name = crypto_tfm_alg_name(&tfm->base); in atmel_aes_xts_init_tfm()
1910 dd = atmel_aes_dev_alloc(&ctx->base); in atmel_aes_xts_init_tfm()
1912 return -ENODEV; in atmel_aes_xts_init_tfm()
1914 ctx->fallback_tfm = crypto_alloc_skcipher(tfm_name, 0, in atmel_aes_xts_init_tfm()
1916 if (IS_ERR(ctx->fallback_tfm)) in atmel_aes_xts_init_tfm()
1917 return PTR_ERR(ctx->fallback_tfm); in atmel_aes_xts_init_tfm()
1920 crypto_skcipher_reqsize(ctx->fallback_tfm)); in atmel_aes_xts_init_tfm()
1921 ctx->base.dd = dd; in atmel_aes_xts_init_tfm()
1922 ctx->base.start = atmel_aes_xts_start; in atmel_aes_xts_init_tfm()
1931 crypto_free_skcipher(ctx->fallback_tfm); in atmel_aes_xts_exit_tfm()
1936 .base.cra_driver_name = "atmel-xts-aes",
1965 struct aead_request *req = aead_request_cast(dd->areq); in atmel_aes_authenc_complete()
1968 if (err && (dd->flags & AES_FLAGS_OWN_SHA)) in atmel_aes_authenc_complete()
1969 atmel_sha_authenc_abort(&rctx->auth_req); in atmel_aes_authenc_complete()
1970 dd->flags &= ~AES_FLAGS_OWN_SHA; in atmel_aes_authenc_complete()
1975 struct aead_request *req = aead_request_cast(dd->areq); in atmel_aes_authenc_start()
1981 atmel_aes_set_mode(dd, &rctx->base); in atmel_aes_authenc_start()
1987 return atmel_sha_authenc_schedule(&rctx->auth_req, ctx->auth, in atmel_aes_authenc_start()
1994 struct aead_request *req = aead_request_cast(dd->areq); in atmel_aes_authenc_init()
1998 dd->is_async = true; in atmel_aes_authenc_init()
2002 /* If here, we've got the ownership of the SHA device. */ in atmel_aes_authenc_init()
2003 dd->flags |= AES_FLAGS_OWN_SHA; in atmel_aes_authenc_init()
2005 /* Configure the SHA device. */ in atmel_aes_authenc_init()
2006 return atmel_sha_authenc_init(&rctx->auth_req, in atmel_aes_authenc_init()
2007 req->src, req->assoclen, in atmel_aes_authenc_init()
2008 rctx->textlen, in atmel_aes_authenc_init()
2015 struct aead_request *req = aead_request_cast(dd->areq); in atmel_aes_authenc_transfer()
2023 dd->is_async = true; in atmel_aes_authenc_transfer()
2027 /* Prepare src and dst scatter-lists to transfer cipher/plain texts. */ in atmel_aes_authenc_transfer()
2028 src = scatterwalk_ffwd(rctx->src, req->src, req->assoclen); in atmel_aes_authenc_transfer()
2031 if (req->src != req->dst) in atmel_aes_authenc_transfer()
2032 dst = scatterwalk_ffwd(rctx->dst, req->dst, req->assoclen); in atmel_aes_authenc_transfer()
2035 memcpy(iv, req->iv, sizeof(iv)); in atmel_aes_authenc_transfer()
2051 return atmel_aes_dma_start(dd, src, dst, rctx->textlen, in atmel_aes_authenc_transfer()
2057 struct aead_request *req = aead_request_cast(dd->areq); in atmel_aes_authenc_digest()
2060 /* atmel_sha_authenc_final() releases the SHA device. */ in atmel_aes_authenc_digest()
2061 dd->flags &= ~AES_FLAGS_OWN_SHA; in atmel_aes_authenc_digest()
2062 return atmel_sha_authenc_final(&rctx->auth_req, in atmel_aes_authenc_digest()
2063 rctx->digest, sizeof(rctx->digest), in atmel_aes_authenc_digest()
2070 struct aead_request *req = aead_request_cast(dd->areq); in atmel_aes_authenc_final()
2074 u32 idigest[SHA512_DIGEST_SIZE / sizeof(u32)], *odigest = rctx->digest; in atmel_aes_authenc_final()
2078 dd->is_async = true; in atmel_aes_authenc_final()
2082 offs = req->assoclen + rctx->textlen; in atmel_aes_authenc_final()
2085 scatterwalk_map_and_copy(odigest, req->dst, offs, authsize, 1); in atmel_aes_authenc_final()
2087 scatterwalk_map_and_copy(idigest, req->src, offs, authsize, 0); in atmel_aes_authenc_final()
2089 err = -EBADMSG; in atmel_aes_authenc_final()
2106 if (keys.enckeylen > sizeof(ctx->base.key)) in atmel_aes_authenc_setkey()
2110 err = atmel_sha_authenc_setkey(ctx->auth, in atmel_aes_authenc_setkey()
2119 ctx->base.keylen = keys.enckeylen; in atmel_aes_authenc_setkey()
2120 memcpy(ctx->base.key, keys.enckey, keys.enckeylen); in atmel_aes_authenc_setkey()
2127 return -EINVAL; in atmel_aes_authenc_setkey()
2137 dd = atmel_aes_dev_alloc(&ctx->base); in atmel_aes_authenc_init_tfm()
2139 return -ENODEV; in atmel_aes_authenc_init_tfm()
2141 ctx->auth = atmel_sha_authenc_spawn(auth_mode); in atmel_aes_authenc_init_tfm()
2142 if (IS_ERR(ctx->auth)) in atmel_aes_authenc_init_tfm()
2143 return PTR_ERR(ctx->auth); in atmel_aes_authenc_init_tfm()
2147 ctx->base.dd = dd; in atmel_aes_authenc_init_tfm()
2148 ctx->base.start = atmel_aes_authenc_start; in atmel_aes_authenc_init_tfm()
2182 atmel_sha_authenc_free(ctx->auth); in atmel_aes_authenc_exit_tfm()
2195 if (!enc && req->cryptlen < authsize) in atmel_aes_authenc_crypt()
2196 return -EINVAL; in atmel_aes_authenc_crypt()
2197 rctx->textlen = req->cryptlen - (enc ? 0 : authsize); in atmel_aes_authenc_crypt()
2201 * the SHA auto-padding can be used only on non-empty messages. in atmel_aes_authenc_crypt()
2204 if (!rctx->textlen && !req->assoclen) in atmel_aes_authenc_crypt()
2205 return -EINVAL; in atmel_aes_authenc_crypt()
2207 rctx->base.mode = mode; in atmel_aes_authenc_crypt()
2208 ctx->block_size = AES_BLOCK_SIZE; in atmel_aes_authenc_crypt()
2209 ctx->is_aead = true; in atmel_aes_authenc_crypt()
2211 return atmel_aes_handle_queue(ctx->dd, &req->base); in atmel_aes_authenc_crypt()
2236 .cra_driver_name = "atmel-authenc-hmac-sha1-cbc-aes",
2252 .cra_driver_name = "atmel-authenc-hmac-sha224-cbc-aes",
2268 .cra_driver_name = "atmel-authenc-hmac-sha256-cbc-aes",
2284 .cra_driver_name = "atmel-authenc-hmac-sha384-cbc-aes",
2300 .cra_driver_name = "atmel-authenc-hmac-sha512-cbc-aes",
2312 dd->buf = (void *)__get_free_pages(GFP_KERNEL, ATMEL_AES_BUFFER_ORDER); in atmel_aes_buff_init()
2313 dd->buflen = ATMEL_AES_BUFFER_SIZE; in atmel_aes_buff_init()
2314 dd->buflen &= ~(AES_BLOCK_SIZE - 1); in atmel_aes_buff_init()
2316 if (!dd->buf) { in atmel_aes_buff_init()
2317 dev_err(dd->dev, "unable to alloc pages.\n"); in atmel_aes_buff_init()
2318 return -ENOMEM; in atmel_aes_buff_init()
2326 free_page((unsigned long)dd->buf); in atmel_aes_buff_cleanup()
2334 dd->src.chan = dma_request_chan(dd->dev, "tx"); in atmel_aes_dma_init()
2335 if (IS_ERR(dd->src.chan)) { in atmel_aes_dma_init()
2336 ret = PTR_ERR(dd->src.chan); in atmel_aes_dma_init()
2340 dd->dst.chan = dma_request_chan(dd->dev, "rx"); in atmel_aes_dma_init()
2341 if (IS_ERR(dd->dst.chan)) { in atmel_aes_dma_init()
2342 ret = PTR_ERR(dd->dst.chan); in atmel_aes_dma_init()
2349 dma_release_channel(dd->src.chan); in atmel_aes_dma_init()
2351 dev_err(dd->dev, "no DMA channel available\n"); in atmel_aes_dma_init()
2357 dma_release_channel(dd->dst.chan); in atmel_aes_dma_cleanup()
2358 dma_release_channel(dd->src.chan); in atmel_aes_dma_cleanup()
2372 dd->is_async = true; in atmel_aes_done_task()
2373 (void)dd->resume(dd); in atmel_aes_done_task()
2384 if (AES_FLAGS_BUSY & aes_dd->flags) in atmel_aes_irq()
2385 tasklet_schedule(&aes_dd->done_task); in atmel_aes_irq()
2387 dev_warn(aes_dd->dev, "AES interrupt when no active requests.\n"); in atmel_aes_irq()
2399 if (dd->caps.has_authenc) in atmel_aes_unregister_algs()
2404 if (dd->caps.has_xts) in atmel_aes_unregister_algs()
2407 if (dd->caps.has_gcm) in atmel_aes_unregister_algs()
2410 if (dd->caps.has_cfb64) in atmel_aes_unregister_algs()
2419 alg->cra_flags |= CRYPTO_ALG_ASYNC; in atmel_aes_crypto_alg_init()
2420 alg->cra_alignmask = 0xf; in atmel_aes_crypto_alg_init()
2421 alg->cra_priority = ATMEL_AES_PRIORITY; in atmel_aes_crypto_alg_init()
2422 alg->cra_module = THIS_MODULE; in atmel_aes_crypto_alg_init()
2437 if (dd->caps.has_cfb64) { in atmel_aes_register_algs()
2445 if (dd->caps.has_gcm) { in atmel_aes_register_algs()
2453 if (dd->caps.has_xts) { in atmel_aes_register_algs()
2462 if (dd->caps.has_authenc) { in atmel_aes_register_algs()
2497 dd->caps.has_dualbuff = 0; in atmel_aes_get_cap()
2498 dd->caps.has_cfb64 = 0; in atmel_aes_get_cap()
2499 dd->caps.has_gcm = 0; in atmel_aes_get_cap()
2500 dd->caps.has_xts = 0; in atmel_aes_get_cap()
2501 dd->caps.has_authenc = 0; in atmel_aes_get_cap()
2502 dd->caps.max_burst_size = 1; in atmel_aes_get_cap()
2505 switch (dd->hw_version & 0xff0) { in atmel_aes_get_cap()
2509 dd->caps.has_dualbuff = 1; in atmel_aes_get_cap()
2510 dd->caps.has_cfb64 = 1; in atmel_aes_get_cap()
2511 dd->caps.has_gcm = 1; in atmel_aes_get_cap()
2512 dd->caps.has_xts = 1; in atmel_aes_get_cap()
2513 dd->caps.has_authenc = 1; in atmel_aes_get_cap()
2514 dd->caps.max_burst_size = 4; in atmel_aes_get_cap()
2517 dd->caps.has_dualbuff = 1; in atmel_aes_get_cap()
2518 dd->caps.has_cfb64 = 1; in atmel_aes_get_cap()
2519 dd->caps.has_gcm = 1; in atmel_aes_get_cap()
2520 dd->caps.max_burst_size = 4; in atmel_aes_get_cap()
2523 dd->caps.has_dualbuff = 1; in atmel_aes_get_cap()
2524 dd->caps.has_cfb64 = 1; in atmel_aes_get_cap()
2525 dd->caps.max_burst_size = 4; in atmel_aes_get_cap()
2530 dev_warn(dd->dev, in atmel_aes_get_cap()
2537 { .compatible = "atmel,at91sam9g46-aes" },
2545 struct device *dev = &pdev->dev; in atmel_aes_probe()
2549 aes_dd = devm_kzalloc(&pdev->dev, sizeof(*aes_dd), GFP_KERNEL); in atmel_aes_probe()
2551 return -ENOMEM; in atmel_aes_probe()
2553 aes_dd->dev = dev; in atmel_aes_probe()
2557 INIT_LIST_HEAD(&aes_dd->list); in atmel_aes_probe()
2558 spin_lock_init(&aes_dd->lock); in atmel_aes_probe()
2560 tasklet_init(&aes_dd->done_task, atmel_aes_done_task, in atmel_aes_probe()
2562 tasklet_init(&aes_dd->queue_task, atmel_aes_queue_task, in atmel_aes_probe()
2565 crypto_init_queue(&aes_dd->queue, ATMEL_AES_QUEUE_LENGTH); in atmel_aes_probe()
2567 aes_dd->io_base = devm_platform_get_and_ioremap_resource(pdev, 0, &aes_res); in atmel_aes_probe()
2568 if (IS_ERR(aes_dd->io_base)) { in atmel_aes_probe()
2569 err = PTR_ERR(aes_dd->io_base); in atmel_aes_probe()
2572 aes_dd->phys_base = aes_res->start; in atmel_aes_probe()
2575 aes_dd->irq = platform_get_irq(pdev, 0); in atmel_aes_probe()
2576 if (aes_dd->irq < 0) { in atmel_aes_probe()
2577 err = aes_dd->irq; in atmel_aes_probe()
2581 err = devm_request_irq(&pdev->dev, aes_dd->irq, atmel_aes_irq, in atmel_aes_probe()
2582 IRQF_SHARED, "atmel-aes", aes_dd); in atmel_aes_probe()
2589 aes_dd->iclk = devm_clk_get(&pdev->dev, "aes_clk"); in atmel_aes_probe()
2590 if (IS_ERR(aes_dd->iclk)) { in atmel_aes_probe()
2592 err = PTR_ERR(aes_dd->iclk); in atmel_aes_probe()
2596 err = clk_prepare(aes_dd->iclk); in atmel_aes_probe()
2607 if (aes_dd->caps.has_authenc && !atmel_sha_authenc_is_ready()) { in atmel_aes_probe()
2608 err = -EPROBE_DEFER; in atmel_aes_probe()
2622 list_add_tail(&aes_dd->list, &atmel_aes.dev_list); in atmel_aes_probe()
2629 dev_info(dev, "Atmel AES - Using %s, %s for DMA transfers\n", in atmel_aes_probe()
2630 dma_chan_name(aes_dd->src.chan), in atmel_aes_probe()
2631 dma_chan_name(aes_dd->dst.chan)); in atmel_aes_probe()
2637 list_del(&aes_dd->list); in atmel_aes_probe()
2643 clk_unprepare(aes_dd->iclk); in atmel_aes_probe()
2645 tasklet_kill(&aes_dd->done_task); in atmel_aes_probe()
2646 tasklet_kill(&aes_dd->queue_task); in atmel_aes_probe()
2658 list_del(&aes_dd->list); in atmel_aes_remove()
2663 tasklet_kill(&aes_dd->done_task); in atmel_aes_remove()
2664 tasklet_kill(&aes_dd->queue_task); in atmel_aes_remove()
2669 clk_unprepare(aes_dd->iclk); in atmel_aes_remove()
2687 MODULE_AUTHOR("Nicolas Royer - Eukréa Electromatique");