Lines Matching full:qm
358 bool hpre_check_alg_support(struct hisi_qm *qm, u32 alg) in hpre_check_alg_support() argument
362 cap_val = qm->cap_tables.dev_cap_table[HPRE_DRV_ALG_BITMAP_CAP_IDX].cap_val; in hpre_check_alg_support()
371 struct hisi_qm *qm = s->private; in hpre_diff_regs_show() local
373 hisi_qm_acc_diff_regs_dump(qm, s, qm->debug.acc_diff_regs, in hpre_diff_regs_show()
458 static void hpre_config_pasid(struct hisi_qm *qm) in hpre_config_pasid() argument
462 if (qm->ver >= QM_HW_V3) in hpre_config_pasid()
465 val1 = readl_relaxed(qm->io_base + HPRE_DATA_RUSER_CFG); in hpre_config_pasid()
466 val2 = readl_relaxed(qm->io_base + HPRE_DATA_WUSER_CFG); in hpre_config_pasid()
467 if (qm->use_sva) { in hpre_config_pasid()
474 writel_relaxed(val1, qm->io_base + HPRE_DATA_RUSER_CFG); in hpre_config_pasid()
475 writel_relaxed(val2, qm->io_base + HPRE_DATA_WUSER_CFG); in hpre_config_pasid()
478 static int hpre_cfg_by_dsm(struct hisi_qm *qm) in hpre_cfg_by_dsm() argument
480 struct device *dev = &qm->pdev->dev; in hpre_cfg_by_dsm()
502 static int hpre_set_cluster(struct hisi_qm *qm) in hpre_set_cluster() argument
504 struct device *dev = &qm->pdev->dev; in hpre_set_cluster()
511 cluster_core_mask = qm->cap_tables.dev_cap_table[HPRE_CORE_ENABLE_BITMAP_CAP_IDX].cap_val; in hpre_set_cluster()
512 clusters_num = qm->cap_tables.dev_cap_table[HPRE_CLUSTER_NUM_CAP_IDX].cap_val; in hpre_set_cluster()
518 qm->io_base + offset + HPRE_CORE_ENB); in hpre_set_cluster()
519 writel(0x1, qm->io_base + offset + HPRE_CORE_INI_CFG); in hpre_set_cluster()
520 ret = readl_relaxed_poll_timeout(qm->io_base + offset + in hpre_set_cluster()
541 static void disable_flr_of_bme(struct hisi_qm *qm) in disable_flr_of_bme() argument
545 val = readl(qm->io_base + QM_PEH_AXUSER_CFG); in disable_flr_of_bme()
548 writel(val, qm->io_base + QM_PEH_AXUSER_CFG); in disable_flr_of_bme()
549 writel(PEH_AXUSER_CFG_ENABLE, qm->io_base + QM_PEH_AXUSER_CFG_ENABLE); in disable_flr_of_bme()
552 static void hpre_open_sva_prefetch(struct hisi_qm *qm) in hpre_open_sva_prefetch() argument
557 if (!test_bit(QM_SUPPORT_SVA_PREFETCH, &qm->caps)) in hpre_open_sva_prefetch()
561 val = readl_relaxed(qm->io_base + HPRE_PREFETCH_CFG); in hpre_open_sva_prefetch()
563 writel(val, qm->io_base + HPRE_PREFETCH_CFG); in hpre_open_sva_prefetch()
565 ret = readl_relaxed_poll_timeout(qm->io_base + HPRE_PREFETCH_CFG, in hpre_open_sva_prefetch()
570 pci_err(qm->pdev, "failed to open sva prefetch\n"); in hpre_open_sva_prefetch()
573 static void hpre_close_sva_prefetch(struct hisi_qm *qm) in hpre_close_sva_prefetch() argument
578 if (!test_bit(QM_SUPPORT_SVA_PREFETCH, &qm->caps)) in hpre_close_sva_prefetch()
581 val = readl_relaxed(qm->io_base + HPRE_PREFETCH_CFG); in hpre_close_sva_prefetch()
583 writel(val, qm->io_base + HPRE_PREFETCH_CFG); in hpre_close_sva_prefetch()
585 ret = readl_relaxed_poll_timeout(qm->io_base + HPRE_SVA_PREFTCH_DFX, in hpre_close_sva_prefetch()
590 pci_err(qm->pdev, "failed to close sva prefetch\n"); in hpre_close_sva_prefetch()
593 static void hpre_enable_clock_gate(struct hisi_qm *qm) in hpre_enable_clock_gate() argument
597 if (qm->ver < QM_HW_V3) in hpre_enable_clock_gate()
600 val = readl(qm->io_base + HPRE_CLKGATE_CTL); in hpre_enable_clock_gate()
602 writel(val, qm->io_base + HPRE_CLKGATE_CTL); in hpre_enable_clock_gate()
604 val = readl(qm->io_base + HPRE_PEH_CFG_AUTO_GATE); in hpre_enable_clock_gate()
606 writel(val, qm->io_base + HPRE_PEH_CFG_AUTO_GATE); in hpre_enable_clock_gate()
608 val = readl(qm->io_base + HPRE_CLUSTER_DYN_CTL); in hpre_enable_clock_gate()
610 writel(val, qm->io_base + HPRE_CLUSTER_DYN_CTL); in hpre_enable_clock_gate()
612 val = readl_relaxed(qm->io_base + HPRE_CORE_SHB_CFG); in hpre_enable_clock_gate()
614 writel(val, qm->io_base + HPRE_CORE_SHB_CFG); in hpre_enable_clock_gate()
617 static void hpre_disable_clock_gate(struct hisi_qm *qm) in hpre_disable_clock_gate() argument
621 if (qm->ver < QM_HW_V3) in hpre_disable_clock_gate()
624 val = readl(qm->io_base + HPRE_CLKGATE_CTL); in hpre_disable_clock_gate()
626 writel(val, qm->io_base + HPRE_CLKGATE_CTL); in hpre_disable_clock_gate()
628 val = readl(qm->io_base + HPRE_PEH_CFG_AUTO_GATE); in hpre_disable_clock_gate()
630 writel(val, qm->io_base + HPRE_PEH_CFG_AUTO_GATE); in hpre_disable_clock_gate()
632 val = readl(qm->io_base + HPRE_CLUSTER_DYN_CTL); in hpre_disable_clock_gate()
634 writel(val, qm->io_base + HPRE_CLUSTER_DYN_CTL); in hpre_disable_clock_gate()
636 val = readl_relaxed(qm->io_base + HPRE_CORE_SHB_CFG); in hpre_disable_clock_gate()
638 writel(val, qm->io_base + HPRE_CORE_SHB_CFG); in hpre_disable_clock_gate()
641 static int hpre_set_user_domain_and_cache(struct hisi_qm *qm) in hpre_set_user_domain_and_cache() argument
643 struct device *dev = &qm->pdev->dev; in hpre_set_user_domain_and_cache()
648 hpre_disable_clock_gate(qm); in hpre_set_user_domain_and_cache()
650 writel(HPRE_QM_USR_CFG_MASK, qm->io_base + QM_ARUSER_M_CFG_ENABLE); in hpre_set_user_domain_and_cache()
651 writel(HPRE_QM_USR_CFG_MASK, qm->io_base + QM_AWUSER_M_CFG_ENABLE); in hpre_set_user_domain_and_cache()
652 writel_relaxed(HPRE_QM_AXI_CFG_MASK, qm->io_base + QM_AXI_M_CFG); in hpre_set_user_domain_and_cache()
654 if (qm->ver >= QM_HW_V3) in hpre_set_user_domain_and_cache()
656 qm->io_base + HPRE_TYPES_ENB); in hpre_set_user_domain_and_cache()
658 writel(HPRE_RSA_ENB, qm->io_base + HPRE_TYPES_ENB); in hpre_set_user_domain_and_cache()
660 writel(HPRE_QM_VFG_AX_MASK, qm->io_base + HPRE_VFG_AXCACHE); in hpre_set_user_domain_and_cache()
661 writel(0x0, qm->io_base + HPRE_BD_ENDIAN); in hpre_set_user_domain_and_cache()
662 writel(0x0, qm->io_base + HPRE_POISON_BYPASS); in hpre_set_user_domain_and_cache()
663 writel(0x0, qm->io_base + HPRE_ECC_BYPASS); in hpre_set_user_domain_and_cache()
665 writel(HPRE_BD_USR_MASK, qm->io_base + HPRE_BD_ARUSR_CFG); in hpre_set_user_domain_and_cache()
666 writel(HPRE_BD_USR_MASK, qm->io_base + HPRE_BD_AWUSR_CFG); in hpre_set_user_domain_and_cache()
667 writel(0x1, qm->io_base + HPRE_RDCHN_INI_CFG); in hpre_set_user_domain_and_cache()
668 ret = readl_relaxed_poll_timeout(qm->io_base + HPRE_RDCHN_INI_ST, val, in hpre_set_user_domain_and_cache()
677 ret = hpre_set_cluster(qm); in hpre_set_user_domain_and_cache()
682 if (qm->ver == QM_HW_V2) { in hpre_set_user_domain_and_cache()
683 ret = hpre_cfg_by_dsm(qm); in hpre_set_user_domain_and_cache()
687 disable_flr_of_bme(qm); in hpre_set_user_domain_and_cache()
691 hpre_config_pasid(qm); in hpre_set_user_domain_and_cache()
693 hpre_enable_clock_gate(qm); in hpre_set_user_domain_and_cache()
698 static void hpre_cnt_regs_clear(struct hisi_qm *qm) in hpre_cnt_regs_clear() argument
705 clusters_num = qm->cap_tables.dev_cap_table[HPRE_CLUSTER_NUM_CAP_IDX].cap_val; in hpre_cnt_regs_clear()
708 writel(0x0, qm->io_base + offset + HPRE_CLUSTER_INQURY); in hpre_cnt_regs_clear()
712 writel(0x0, qm->io_base + HPRE_CTRL_CNT_CLR_CE); in hpre_cnt_regs_clear()
714 hisi_qm_debug_regs_clear(qm); in hpre_cnt_regs_clear()
717 static void hpre_master_ooo_ctrl(struct hisi_qm *qm, bool enable) in hpre_master_ooo_ctrl() argument
721 val1 = readl(qm->io_base + HPRE_AM_OOO_SHUTDOWN_ENB); in hpre_master_ooo_ctrl()
724 val2 = hisi_qm_get_hw_info(qm, hpre_basic_info, in hpre_master_ooo_ctrl()
725 HPRE_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver); in hpre_master_ooo_ctrl()
731 if (qm->ver > QM_HW_V2) in hpre_master_ooo_ctrl()
732 writel(val2, qm->io_base + HPRE_OOO_SHUTDOWN_SEL); in hpre_master_ooo_ctrl()
734 writel(val1, qm->io_base + HPRE_AM_OOO_SHUTDOWN_ENB); in hpre_master_ooo_ctrl()
737 static void hpre_hw_error_disable(struct hisi_qm *qm) in hpre_hw_error_disable() argument
741 ce = hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_CE_MASK_CAP, qm->cap_ver); in hpre_hw_error_disable()
742 nfe = hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_NFE_MASK_CAP, qm->cap_ver); in hpre_hw_error_disable()
745 writel(ce | nfe | HPRE_HAC_RAS_FE_ENABLE, qm->io_base + HPRE_INT_MASK); in hpre_hw_error_disable()
747 hpre_master_ooo_ctrl(qm, false); in hpre_hw_error_disable()
750 static void hpre_hw_error_enable(struct hisi_qm *qm) in hpre_hw_error_enable() argument
754 ce = hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_CE_MASK_CAP, qm->cap_ver); in hpre_hw_error_enable()
755 nfe = hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_NFE_MASK_CAP, qm->cap_ver); in hpre_hw_error_enable()
758 writel(ce | nfe | HPRE_HAC_RAS_FE_ENABLE, qm->io_base + HPRE_HAC_SOURCE_INT); in hpre_hw_error_enable()
761 writel(ce, qm->io_base + HPRE_RAS_CE_ENB); in hpre_hw_error_enable()
762 writel(nfe, qm->io_base + HPRE_RAS_NFE_ENB); in hpre_hw_error_enable()
763 writel(HPRE_HAC_RAS_FE_ENABLE, qm->io_base + HPRE_RAS_FE_ENB); in hpre_hw_error_enable()
766 hpre_master_ooo_ctrl(qm, true); in hpre_hw_error_enable()
770 writel(~err_en, qm->io_base + HPRE_INT_MASK); in hpre_hw_error_enable()
777 return &hpre->qm; in hpre_file_to_qm()
782 struct hisi_qm *qm = hpre_file_to_qm(file); in hpre_clear_enable_read() local
784 return readl(qm->io_base + HPRE_CTRL_CNT_CLR_CE) & in hpre_clear_enable_read()
790 struct hisi_qm *qm = hpre_file_to_qm(file); in hpre_clear_enable_write() local
796 tmp = (readl(qm->io_base + HPRE_CTRL_CNT_CLR_CE) & in hpre_clear_enable_write()
798 writel(tmp, qm->io_base + HPRE_CTRL_CNT_CLR_CE); in hpre_clear_enable_write()
805 struct hisi_qm *qm = hpre_file_to_qm(file); in hpre_cluster_inqry_read() local
810 return readl(qm->io_base + offset + HPRE_CLSTR_ADDR_INQRY_RSLT); in hpre_cluster_inqry_read()
815 struct hisi_qm *qm = hpre_file_to_qm(file); in hpre_cluster_inqry_write() local
820 writel(val, qm->io_base + offset + HPRE_CLUSTER_INQURY); in hpre_cluster_inqry_write()
827 struct hisi_qm *qm = hpre_file_to_qm(file); in hpre_ctrl_debug_read() local
832 ret = hisi_qm_get_dfx_access(qm); in hpre_ctrl_debug_read()
849 hisi_qm_put_dfx_access(qm); in hpre_ctrl_debug_read()
855 hisi_qm_put_dfx_access(qm); in hpre_ctrl_debug_read()
863 struct hisi_qm *qm = hpre_file_to_qm(file); in hpre_ctrl_debug_write() local
883 ret = hisi_qm_get_dfx_access(qm); in hpre_ctrl_debug_write()
906 hisi_qm_put_dfx_access(qm); in hpre_ctrl_debug_write()
946 static int hpre_create_debugfs_file(struct hisi_qm *qm, struct dentry *dir, in hpre_create_debugfs_file() argument
949 struct hpre *hpre = container_of(qm, struct hpre, qm); in hpre_create_debugfs_file()
956 file_dir = qm->debug.debug_root; in hpre_create_debugfs_file()
971 static int hpre_pf_comm_regs_debugfs_init(struct hisi_qm *qm) in hpre_pf_comm_regs_debugfs_init() argument
973 struct device *dev = &qm->pdev->dev; in hpre_pf_comm_regs_debugfs_init()
982 regset->base = qm->io_base; in hpre_pf_comm_regs_debugfs_init()
985 debugfs_create_file("regs", 0444, qm->debug.debug_root, in hpre_pf_comm_regs_debugfs_init()
991 static int hpre_cluster_debugfs_init(struct hisi_qm *qm) in hpre_cluster_debugfs_init() argument
993 struct device *dev = &qm->pdev->dev; in hpre_cluster_debugfs_init()
1000 clusters_num = qm->cap_tables.dev_cap_table[HPRE_CLUSTER_NUM_CAP_IDX].cap_val; in hpre_cluster_debugfs_init()
1005 tmp_d = debugfs_create_dir(buf, qm->debug.debug_root); in hpre_cluster_debugfs_init()
1013 regset->base = qm->io_base + hpre_cluster_offsets[i]; in hpre_cluster_debugfs_init()
1018 ret = hpre_create_debugfs_file(qm, tmp_d, HPRE_CLUSTER_CTRL, in hpre_cluster_debugfs_init()
1027 static int hpre_ctrl_debug_init(struct hisi_qm *qm) in hpre_ctrl_debug_init() argument
1031 ret = hpre_create_debugfs_file(qm, NULL, HPRE_CLEAR_ENABLE, in hpre_ctrl_debug_init()
1036 ret = hpre_pf_comm_regs_debugfs_init(qm); in hpre_ctrl_debug_init()
1040 return hpre_cluster_debugfs_init(qm); in hpre_ctrl_debug_init()
1043 static void hpre_dfx_debug_init(struct hisi_qm *qm) in hpre_dfx_debug_init() argument
1045 struct dfx_diff_registers *hpre_regs = qm->debug.acc_diff_regs; in hpre_dfx_debug_init()
1046 struct hpre *hpre = container_of(qm, struct hpre, qm); in hpre_dfx_debug_init()
1051 parent = debugfs_create_dir("hpre_dfx", qm->debug.debug_root); in hpre_dfx_debug_init()
1058 if (qm->fun_type == QM_HW_PF && hpre_regs) in hpre_dfx_debug_init()
1060 qm, &hpre_diff_regs_fops); in hpre_dfx_debug_init()
1063 static int hpre_debugfs_init(struct hisi_qm *qm) in hpre_debugfs_init() argument
1065 struct device *dev = &qm->pdev->dev; in hpre_debugfs_init()
1068 qm->debug.debug_root = debugfs_create_dir(dev_name(dev), in hpre_debugfs_init()
1071 qm->debug.sqe_mask_offset = HPRE_SQE_MASK_OFFSET; in hpre_debugfs_init()
1072 qm->debug.sqe_mask_len = HPRE_SQE_MASK_LEN; in hpre_debugfs_init()
1073 ret = hisi_qm_regs_debugfs_init(qm, hpre_diff_regs, ARRAY_SIZE(hpre_diff_regs)); in hpre_debugfs_init()
1079 hisi_qm_debug_init(qm); in hpre_debugfs_init()
1081 if (qm->pdev->device == PCI_DEVICE_ID_HUAWEI_HPRE_PF) { in hpre_debugfs_init()
1082 ret = hpre_ctrl_debug_init(qm); in hpre_debugfs_init()
1087 hpre_dfx_debug_init(qm); in hpre_debugfs_init()
1092 hisi_qm_regs_debugfs_uninit(qm, ARRAY_SIZE(hpre_diff_regs)); in hpre_debugfs_init()
1094 debugfs_remove_recursive(qm->debug.debug_root); in hpre_debugfs_init()
1098 static void hpre_debugfs_exit(struct hisi_qm *qm) in hpre_debugfs_exit() argument
1100 hisi_qm_regs_debugfs_uninit(qm, ARRAY_SIZE(hpre_diff_regs)); in hpre_debugfs_exit()
1102 debugfs_remove_recursive(qm->debug.debug_root); in hpre_debugfs_exit()
1105 static int hpre_pre_store_cap_reg(struct hisi_qm *qm) in hpre_pre_store_cap_reg() argument
1108 struct device *dev = &qm->pdev->dev; in hpre_pre_store_cap_reg()
1118 hpre_cap[i].cap_val = hisi_qm_get_hw_info(qm, hpre_basic_info, in hpre_pre_store_cap_reg()
1119 hpre_pre_store_caps[i], qm->cap_ver); in hpre_pre_store_cap_reg()
1128 qm->cap_tables.dev_cap_table = hpre_cap; in hpre_pre_store_cap_reg()
1133 static int hpre_qm_init(struct hisi_qm *qm, struct pci_dev *pdev) in hpre_qm_init() argument
1143 qm->mode = uacce_mode; in hpre_qm_init()
1144 qm->pdev = pdev; in hpre_qm_init()
1145 qm->ver = pdev->revision; in hpre_qm_init()
1146 qm->sqe_size = HPRE_SQE_SIZE; in hpre_qm_init()
1147 qm->dev_name = hpre_name; in hpre_qm_init()
1149 qm->fun_type = (pdev->device == PCI_DEVICE_ID_HUAWEI_HPRE_PF) ? in hpre_qm_init()
1151 if (qm->fun_type == QM_HW_PF) { in hpre_qm_init()
1152 qm->qp_base = HPRE_PF_DEF_Q_BASE; in hpre_qm_init()
1153 qm->qp_num = pf_q_num; in hpre_qm_init()
1154 qm->debug.curr_qm_qp_num = pf_q_num; in hpre_qm_init()
1155 qm->qm_list = &hpre_devices; in hpre_qm_init()
1156 qm->err_ini = &hpre_err_ini; in hpre_qm_init()
1158 set_bit(QM_MODULE_PARAM, &qm->misc_ctl); in hpre_qm_init()
1161 ret = hisi_qm_init(qm); in hpre_qm_init()
1163 pci_err(pdev, "Failed to init hpre qm configures!\n"); in hpre_qm_init()
1168 ret = hpre_pre_store_cap_reg(qm); in hpre_qm_init()
1171 hisi_qm_uninit(qm); in hpre_qm_init()
1175 alg_msk = qm->cap_tables.dev_cap_table[HPRE_DEV_ALG_BITMAP_CAP_IDX].cap_val; in hpre_qm_init()
1176 ret = hisi_qm_set_algs(qm, alg_msk, hpre_dev_algs, ARRAY_SIZE(hpre_dev_algs)); in hpre_qm_init()
1179 hisi_qm_uninit(qm); in hpre_qm_init()
1185 static int hpre_show_last_regs_init(struct hisi_qm *qm) in hpre_show_last_regs_init() argument
1189 struct qm_debug *debug = &qm->debug; in hpre_show_last_regs_init()
1194 clusters_num = qm->cap_tables.dev_cap_table[HPRE_CLUSTER_NUM_CAP_IDX].cap_val; in hpre_show_last_regs_init()
1201 debug->last_words[i] = readl_relaxed(qm->io_base + in hpre_show_last_regs_init()
1205 io_base = qm->io_base + hpre_cluster_offsets[i]; in hpre_show_last_regs_init()
1216 static void hpre_show_last_regs_uninit(struct hisi_qm *qm) in hpre_show_last_regs_uninit() argument
1218 struct qm_debug *debug = &qm->debug; in hpre_show_last_regs_uninit()
1220 if (qm->fun_type == QM_HW_VF || !debug->last_words) in hpre_show_last_regs_uninit()
1227 static void hpre_show_last_dfx_regs(struct hisi_qm *qm) in hpre_show_last_dfx_regs() argument
1231 struct qm_debug *debug = &qm->debug; in hpre_show_last_dfx_regs()
1232 struct pci_dev *pdev = qm->pdev; in hpre_show_last_dfx_regs()
1238 if (qm->fun_type == QM_HW_VF || !debug->last_words) in hpre_show_last_dfx_regs()
1243 val = readl_relaxed(qm->io_base + hpre_com_dfx_regs[i].offset); in hpre_show_last_dfx_regs()
1249 clusters_num = qm->cap_tables.dev_cap_table[HPRE_CLUSTER_NUM_CAP_IDX].cap_val; in hpre_show_last_dfx_regs()
1251 io_base = qm->io_base + hpre_cluster_offsets[i]; in hpre_show_last_dfx_regs()
1263 static void hpre_log_hw_error(struct hisi_qm *qm, u32 err_sts) in hpre_log_hw_error() argument
1266 struct device *dev = &qm->pdev->dev; in hpre_log_hw_error()
1276 static u32 hpre_get_hw_err_status(struct hisi_qm *qm) in hpre_get_hw_err_status() argument
1278 return readl(qm->io_base + HPRE_INT_STATUS); in hpre_get_hw_err_status()
1281 static void hpre_clear_hw_err_status(struct hisi_qm *qm, u32 err_sts) in hpre_clear_hw_err_status() argument
1283 writel(err_sts, qm->io_base + HPRE_HAC_SOURCE_INT); in hpre_clear_hw_err_status()
1286 static void hpre_disable_error_report(struct hisi_qm *qm, u32 err_type) in hpre_disable_error_report() argument
1290 nfe_mask = hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_NFE_MASK_CAP, qm->cap_ver); in hpre_disable_error_report()
1291 writel(nfe_mask & (~err_type), qm->io_base + HPRE_RAS_NFE_ENB); in hpre_disable_error_report()
1294 static void hpre_open_axi_master_ooo(struct hisi_qm *qm) in hpre_open_axi_master_ooo() argument
1298 value = readl(qm->io_base + HPRE_AM_OOO_SHUTDOWN_ENB); in hpre_open_axi_master_ooo()
1300 qm->io_base + HPRE_AM_OOO_SHUTDOWN_ENB); in hpre_open_axi_master_ooo()
1302 qm->io_base + HPRE_AM_OOO_SHUTDOWN_ENB); in hpre_open_axi_master_ooo()
1305 static enum acc_err_result hpre_get_err_result(struct hisi_qm *qm) in hpre_get_err_result() argument
1309 err_status = hpre_get_hw_err_status(qm); in hpre_get_err_result()
1311 if (err_status & qm->err_info.ecc_2bits_mask) in hpre_get_err_result()
1312 qm->err_status.is_dev_ecc_mbit = true; in hpre_get_err_result()
1313 hpre_log_hw_error(qm, err_status); in hpre_get_err_result()
1315 if (err_status & qm->err_info.dev_reset_mask) { in hpre_get_err_result()
1317 hpre_disable_error_report(qm, err_status); in hpre_get_err_result()
1320 hpre_clear_hw_err_status(qm, err_status); in hpre_get_err_result()
1326 static void hpre_err_info_init(struct hisi_qm *qm) in hpre_err_info_init() argument
1328 struct hisi_qm_err_info *err_info = &qm->err_info; in hpre_err_info_init()
1331 err_info->ce = hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_QM_CE_MASK_CAP, qm->cap_ver); in hpre_err_info_init()
1332 err_info->nfe = hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_QM_NFE_MASK_CAP, qm->cap_ver); in hpre_err_info_init()
1334 err_info->dev_shutdown_mask = hisi_qm_get_hw_info(qm, hpre_basic_info, in hpre_err_info_init()
1335 HPRE_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver); in hpre_err_info_init()
1336 err_info->qm_shutdown_mask = hisi_qm_get_hw_info(qm, hpre_basic_info, in hpre_err_info_init()
1337 HPRE_QM_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver); in hpre_err_info_init()
1338 err_info->qm_reset_mask = hisi_qm_get_hw_info(qm, hpre_basic_info, in hpre_err_info_init()
1339 HPRE_QM_RESET_MASK_CAP, qm->cap_ver); in hpre_err_info_init()
1340 err_info->dev_reset_mask = hisi_qm_get_hw_info(qm, hpre_basic_info, in hpre_err_info_init()
1341 HPRE_RESET_MASK_CAP, qm->cap_ver); in hpre_err_info_init()
1362 struct hisi_qm *qm = &hpre->qm; in hpre_pf_probe_init() local
1365 ret = hpre_set_user_domain_and_cache(qm); in hpre_pf_probe_init()
1369 hpre_open_sva_prefetch(qm); in hpre_pf_probe_init()
1371 hisi_qm_dev_err_init(qm); in hpre_pf_probe_init()
1372 ret = hpre_show_last_regs_init(qm); in hpre_pf_probe_init()
1374 pci_err(qm->pdev, "Failed to init last word regs!\n"); in hpre_pf_probe_init()
1382 struct hisi_qm *qm = &hpre->qm; in hpre_probe_init() local
1385 if (qm->fun_type == QM_HW_PF) { in hpre_probe_init()
1390 if (qm->ver >= QM_HW_V3) { in hpre_probe_init()
1392 qm->type_rate = type_rate; in hpre_probe_init()
1399 static void hpre_probe_uninit(struct hisi_qm *qm) in hpre_probe_uninit() argument
1401 if (qm->fun_type == QM_HW_VF) in hpre_probe_uninit()
1404 hpre_cnt_regs_clear(qm); in hpre_probe_uninit()
1405 qm->debug.curr_qm_qp_num = 0; in hpre_probe_uninit()
1406 hpre_show_last_regs_uninit(qm); in hpre_probe_uninit()
1407 hpre_close_sva_prefetch(qm); in hpre_probe_uninit()
1408 hisi_qm_dev_err_uninit(qm); in hpre_probe_uninit()
1413 struct hisi_qm *qm; in hpre_probe() local
1421 qm = &hpre->qm; in hpre_probe()
1422 ret = hpre_qm_init(qm, pdev); in hpre_probe()
1424 pci_err(pdev, "Failed to init HPRE QM (%d)!\n", ret); in hpre_probe()
1434 ret = hisi_qm_start(qm); in hpre_probe()
1438 ret = hpre_debugfs_init(qm); in hpre_probe()
1442 ret = hisi_qm_alg_register(qm, &hpre_devices); in hpre_probe()
1448 if (qm->uacce) { in hpre_probe()
1449 ret = uacce_register(qm->uacce); in hpre_probe()
1456 if (qm->fun_type == QM_HW_PF && vfs_num) { in hpre_probe()
1462 hisi_qm_pm_init(qm); in hpre_probe()
1467 hisi_qm_alg_unregister(qm, &hpre_devices); in hpre_probe()
1470 hpre_debugfs_exit(qm); in hpre_probe()
1471 hisi_qm_stop(qm, QM_NORMAL); in hpre_probe()
1474 hpre_probe_uninit(qm); in hpre_probe()
1477 hisi_qm_uninit(qm); in hpre_probe()
1484 struct hisi_qm *qm = pci_get_drvdata(pdev); in hpre_remove() local
1486 hisi_qm_pm_uninit(qm); in hpre_remove()
1487 hisi_qm_wait_task_finish(qm, &hpre_devices); in hpre_remove()
1488 hisi_qm_alg_unregister(qm, &hpre_devices); in hpre_remove()
1489 if (qm->fun_type == QM_HW_PF && qm->vfs_num) in hpre_remove()
1492 hpre_debugfs_exit(qm); in hpre_remove()
1493 hisi_qm_stop(qm, QM_NORMAL); in hpre_remove()
1495 hpre_probe_uninit(qm); in hpre_remove()
1496 hisi_qm_uninit(qm); in hpre_remove()