Lines Matching full:qm
306 struct hisi_qm *qm = s->private; in sec_diff_regs_show() local
308 hisi_qm_acc_diff_regs_dump(qm, s, qm->debug.acc_diff_regs, in sec_diff_regs_show()
394 u64 sec_get_alg_bitmap(struct hisi_qm *qm, u32 high, u32 low) in sec_get_alg_bitmap() argument
398 cap_val_h = qm->cap_tables.dev_cap_table[high].cap_val; in sec_get_alg_bitmap()
399 cap_val_l = qm->cap_tables.dev_cap_table[low].cap_val; in sec_get_alg_bitmap()
424 static void sec_set_endian(struct hisi_qm *qm) in sec_set_endian() argument
428 reg = readl_relaxed(qm->io_base + SEC_CONTROL_REG); in sec_set_endian()
436 writel_relaxed(reg, qm->io_base + SEC_CONTROL_REG); in sec_set_endian()
439 static void sec_engine_sva_config(struct hisi_qm *qm) in sec_engine_sva_config() argument
443 if (qm->ver > QM_HW_V2) { in sec_engine_sva_config()
444 reg = readl_relaxed(qm->io_base + in sec_engine_sva_config()
447 writel_relaxed(reg, qm->io_base + in sec_engine_sva_config()
450 reg = readl_relaxed(qm->io_base + in sec_engine_sva_config()
454 writel_relaxed(reg, qm->io_base + in sec_engine_sva_config()
457 reg = readl_relaxed(qm->io_base + in sec_engine_sva_config()
460 writel_relaxed(reg, qm->io_base + in sec_engine_sva_config()
462 reg = readl_relaxed(qm->io_base + in sec_engine_sva_config()
465 if (qm->use_sva) in sec_engine_sva_config()
469 writel_relaxed(reg, qm->io_base + in sec_engine_sva_config()
474 static void sec_open_sva_prefetch(struct hisi_qm *qm) in sec_open_sva_prefetch() argument
479 if (!test_bit(QM_SUPPORT_SVA_PREFETCH, &qm->caps)) in sec_open_sva_prefetch()
483 val = readl_relaxed(qm->io_base + SEC_PREFETCH_CFG); in sec_open_sva_prefetch()
485 writel(val, qm->io_base + SEC_PREFETCH_CFG); in sec_open_sva_prefetch()
487 ret = readl_relaxed_poll_timeout(qm->io_base + SEC_PREFETCH_CFG, in sec_open_sva_prefetch()
491 pci_err(qm->pdev, "failed to open sva prefetch\n"); in sec_open_sva_prefetch()
494 static void sec_close_sva_prefetch(struct hisi_qm *qm) in sec_close_sva_prefetch() argument
499 if (!test_bit(QM_SUPPORT_SVA_PREFETCH, &qm->caps)) in sec_close_sva_prefetch()
502 val = readl_relaxed(qm->io_base + SEC_PREFETCH_CFG); in sec_close_sva_prefetch()
504 writel(val, qm->io_base + SEC_PREFETCH_CFG); in sec_close_sva_prefetch()
506 ret = readl_relaxed_poll_timeout(qm->io_base + SEC_SVA_TRANS, in sec_close_sva_prefetch()
510 pci_err(qm->pdev, "failed to close sva prefetch\n"); in sec_close_sva_prefetch()
513 static void sec_enable_clock_gate(struct hisi_qm *qm) in sec_enable_clock_gate() argument
517 if (qm->ver < QM_HW_V3) in sec_enable_clock_gate()
520 val = readl_relaxed(qm->io_base + SEC_CONTROL_REG); in sec_enable_clock_gate()
522 writel_relaxed(val, qm->io_base + SEC_CONTROL_REG); in sec_enable_clock_gate()
524 val = readl(qm->io_base + SEC_DYNAMIC_GATE_REG); in sec_enable_clock_gate()
526 writel(val, qm->io_base + SEC_DYNAMIC_GATE_REG); in sec_enable_clock_gate()
528 val = readl(qm->io_base + SEC_CORE_AUTO_GATE); in sec_enable_clock_gate()
530 writel(val, qm->io_base + SEC_CORE_AUTO_GATE); in sec_enable_clock_gate()
533 static void sec_disable_clock_gate(struct hisi_qm *qm) in sec_disable_clock_gate() argument
538 val = readl_relaxed(qm->io_base + SEC_CONTROL_REG); in sec_disable_clock_gate()
540 writel_relaxed(val, qm->io_base + SEC_CONTROL_REG); in sec_disable_clock_gate()
543 static int sec_engine_init(struct hisi_qm *qm) in sec_engine_init() argument
549 sec_disable_clock_gate(qm); in sec_engine_init()
551 writel_relaxed(0x1, qm->io_base + SEC_MEM_START_INIT_REG); in sec_engine_init()
553 ret = readl_relaxed_poll_timeout(qm->io_base + SEC_MEM_INIT_DONE_REG, in sec_engine_init()
557 pci_err(qm->pdev, "fail to init sec mem\n"); in sec_engine_init()
561 reg = readl_relaxed(qm->io_base + SEC_CONTROL_REG); in sec_engine_init()
563 writel_relaxed(reg, qm->io_base + SEC_CONTROL_REG); in sec_engine_init()
565 sec_engine_sva_config(qm); in sec_engine_init()
568 qm->io_base + AM_CFG_SINGLE_PORT_MAX_TRANS); in sec_engine_init()
570 reg = hisi_qm_get_hw_info(qm, sec_basic_info, SEC_CORE_ENABLE_BITMAP, qm->cap_ver); in sec_engine_init()
571 writel(reg, qm->io_base + SEC_SAA_EN_REG); in sec_engine_init()
573 if (qm->ver < QM_HW_V3) { in sec_engine_init()
576 qm->io_base + SEC_BD_ERR_CHK_EN_REG0); in sec_engine_init()
580 qm->io_base + SEC_BD_ERR_CHK_EN_REG1); in sec_engine_init()
582 qm->io_base + SEC_BD_ERR_CHK_EN_REG3); in sec_engine_init()
586 sec_set_endian(qm); in sec_engine_init()
588 sec_enable_clock_gate(qm); in sec_engine_init()
593 static int sec_set_user_domain_and_cache(struct hisi_qm *qm) in sec_set_user_domain_and_cache() argument
595 /* qm user domain */ in sec_set_user_domain_and_cache()
596 writel(AXUSER_BASE, qm->io_base + QM_ARUSER_M_CFG_1); in sec_set_user_domain_and_cache()
597 writel(ARUSER_M_CFG_ENABLE, qm->io_base + QM_ARUSER_M_CFG_ENABLE); in sec_set_user_domain_and_cache()
598 writel(AXUSER_BASE, qm->io_base + QM_AWUSER_M_CFG_1); in sec_set_user_domain_and_cache()
599 writel(AWUSER_M_CFG_ENABLE, qm->io_base + QM_AWUSER_M_CFG_ENABLE); in sec_set_user_domain_and_cache()
600 writel(WUSER_M_CFG_ENABLE, qm->io_base + QM_WUSER_M_CFG_ENABLE); in sec_set_user_domain_and_cache()
602 /* qm cache */ in sec_set_user_domain_and_cache()
603 writel(AXI_M_CFG, qm->io_base + QM_AXI_M_CFG); in sec_set_user_domain_and_cache()
604 writel(AXI_M_CFG_ENABLE, qm->io_base + QM_AXI_M_CFG_ENABLE); in sec_set_user_domain_and_cache()
607 writel(PEH_AXUSER_CFG, qm->io_base + QM_PEH_AXUSER_CFG); in sec_set_user_domain_and_cache()
608 writel(PEH_AXUSER_CFG_ENABLE, qm->io_base + QM_PEH_AXUSER_CFG_ENABLE); in sec_set_user_domain_and_cache()
613 FIELD_PREP(CQC_CACHE_WB_THRD, 1), qm->io_base + QM_CACHE_CTL); in sec_set_user_domain_and_cache()
615 return sec_engine_init(qm); in sec_set_user_domain_and_cache()
619 static void sec_debug_regs_clear(struct hisi_qm *qm) in sec_debug_regs_clear() argument
624 writel(0x1, qm->io_base + SEC_CTRL_CNT_CLR_CE); in sec_debug_regs_clear()
626 readl(qm->io_base + sec_dfx_regs[i].offset); in sec_debug_regs_clear()
629 writel(0x0, qm->io_base + SEC_CTRL_CNT_CLR_CE); in sec_debug_regs_clear()
631 hisi_qm_debug_regs_clear(qm); in sec_debug_regs_clear()
634 static void sec_master_ooo_ctrl(struct hisi_qm *qm, bool enable) in sec_master_ooo_ctrl() argument
638 val1 = readl(qm->io_base + SEC_CONTROL_REG); in sec_master_ooo_ctrl()
641 val2 = hisi_qm_get_hw_info(qm, sec_basic_info, in sec_master_ooo_ctrl()
642 SEC_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver); in sec_master_ooo_ctrl()
648 if (qm->ver > QM_HW_V2) in sec_master_ooo_ctrl()
649 writel(val2, qm->io_base + SEC_OOO_SHUTDOWN_SEL); in sec_master_ooo_ctrl()
651 writel(val1, qm->io_base + SEC_CONTROL_REG); in sec_master_ooo_ctrl()
654 static void sec_hw_error_enable(struct hisi_qm *qm) in sec_hw_error_enable() argument
658 if (qm->ver == QM_HW_V1) { in sec_hw_error_enable()
659 writel(SEC_CORE_INT_DISABLE, qm->io_base + SEC_CORE_INT_MASK); in sec_hw_error_enable()
660 pci_info(qm->pdev, "V1 not support hw error handle\n"); in sec_hw_error_enable()
664 ce = hisi_qm_get_hw_info(qm, sec_basic_info, SEC_CE_MASK_CAP, qm->cap_ver); in sec_hw_error_enable()
665 nfe = hisi_qm_get_hw_info(qm, sec_basic_info, SEC_NFE_MASK_CAP, qm->cap_ver); in sec_hw_error_enable()
668 writel(ce | nfe | SEC_RAS_FE_ENB_MSK, qm->io_base + SEC_CORE_INT_SOURCE); in sec_hw_error_enable()
671 writel(ce, qm->io_base + SEC_RAS_CE_REG); in sec_hw_error_enable()
672 writel(SEC_RAS_FE_ENB_MSK, qm->io_base + SEC_RAS_FE_REG); in sec_hw_error_enable()
673 writel(nfe, qm->io_base + SEC_RAS_NFE_REG); in sec_hw_error_enable()
676 sec_master_ooo_ctrl(qm, true); in sec_hw_error_enable()
679 writel(ce | nfe | SEC_RAS_FE_ENB_MSK, qm->io_base + SEC_CORE_INT_MASK); in sec_hw_error_enable()
682 static void sec_hw_error_disable(struct hisi_qm *qm) in sec_hw_error_disable() argument
685 writel(SEC_CORE_INT_DISABLE, qm->io_base + SEC_CORE_INT_MASK); in sec_hw_error_disable()
688 sec_master_ooo_ctrl(qm, false); in sec_hw_error_disable()
691 writel(SEC_RAS_DISABLE, qm->io_base + SEC_RAS_CE_REG); in sec_hw_error_disable()
692 writel(SEC_RAS_DISABLE, qm->io_base + SEC_RAS_FE_REG); in sec_hw_error_disable()
693 writel(SEC_RAS_DISABLE, qm->io_base + SEC_RAS_NFE_REG); in sec_hw_error_disable()
696 static u32 sec_clear_enable_read(struct hisi_qm *qm) in sec_clear_enable_read() argument
698 return readl(qm->io_base + SEC_CTRL_CNT_CLR_CE) & in sec_clear_enable_read()
702 static int sec_clear_enable_write(struct hisi_qm *qm, u32 val) in sec_clear_enable_write() argument
709 tmp = (readl(qm->io_base + SEC_CTRL_CNT_CLR_CE) & in sec_clear_enable_write()
711 writel(tmp, qm->io_base + SEC_CTRL_CNT_CLR_CE); in sec_clear_enable_write()
721 struct hisi_qm *qm = file->qm; in sec_debug_read() local
725 ret = hisi_qm_get_dfx_access(qm); in sec_debug_read()
733 val = sec_clear_enable_read(qm); in sec_debug_read()
741 hisi_qm_put_dfx_access(qm); in sec_debug_read()
747 hisi_qm_put_dfx_access(qm); in sec_debug_read()
756 struct hisi_qm *qm = file->qm; in sec_debug_write() local
775 ret = hisi_qm_get_dfx_access(qm); in sec_debug_write()
783 ret = sec_clear_enable_write(qm, val); in sec_debug_write()
796 hisi_qm_put_dfx_access(qm); in sec_debug_write()
836 static int sec_core_debug_init(struct hisi_qm *qm) in sec_core_debug_init() argument
838 struct dfx_diff_registers *sec_regs = qm->debug.acc_diff_regs; in sec_core_debug_init()
839 struct sec_dev *sec = container_of(qm, struct sec_dev, qm); in sec_core_debug_init()
840 struct device *dev = &qm->pdev->dev; in sec_core_debug_init()
846 tmp_d = debugfs_create_dir("sec_dfx", qm->debug.debug_root); in sec_core_debug_init()
854 regset->base = qm->io_base; in sec_core_debug_init()
857 if (qm->pdev->device == PCI_DEVICE_ID_HUAWEI_SEC_PF) in sec_core_debug_init()
859 if (qm->fun_type == QM_HW_PF && sec_regs) in sec_core_debug_init()
861 qm, &sec_diff_regs_fops); in sec_core_debug_init()
873 static int sec_debug_init(struct hisi_qm *qm) in sec_debug_init() argument
875 struct sec_dev *sec = container_of(qm, struct sec_dev, qm); in sec_debug_init()
878 if (qm->pdev->device == PCI_DEVICE_ID_HUAWEI_SEC_PF) { in sec_debug_init()
882 sec->debug.files[i].qm = qm; in sec_debug_init()
885 qm->debug.debug_root, in sec_debug_init()
891 return sec_core_debug_init(qm); in sec_debug_init()
894 static int sec_debugfs_init(struct hisi_qm *qm) in sec_debugfs_init() argument
896 struct device *dev = &qm->pdev->dev; in sec_debugfs_init()
899 qm->debug.debug_root = debugfs_create_dir(dev_name(dev), in sec_debugfs_init()
901 qm->debug.sqe_mask_offset = SEC_SQE_MASK_OFFSET; in sec_debugfs_init()
902 qm->debug.sqe_mask_len = SEC_SQE_MASK_LEN; in sec_debugfs_init()
904 ret = hisi_qm_regs_debugfs_init(qm, sec_diff_regs, ARRAY_SIZE(sec_diff_regs)); in sec_debugfs_init()
910 hisi_qm_debug_init(qm); in sec_debugfs_init()
912 ret = sec_debug_init(qm); in sec_debugfs_init()
919 hisi_qm_regs_debugfs_uninit(qm, ARRAY_SIZE(sec_diff_regs)); in sec_debugfs_init()
925 static void sec_debugfs_exit(struct hisi_qm *qm) in sec_debugfs_exit() argument
927 hisi_qm_regs_debugfs_uninit(qm, ARRAY_SIZE(sec_diff_regs)); in sec_debugfs_exit()
929 debugfs_remove_recursive(qm->debug.debug_root); in sec_debugfs_exit()
932 static int sec_show_last_regs_init(struct hisi_qm *qm) in sec_show_last_regs_init() argument
934 struct qm_debug *debug = &qm->debug; in sec_show_last_regs_init()
943 debug->last_words[i] = readl_relaxed(qm->io_base + in sec_show_last_regs_init()
949 static void sec_show_last_regs_uninit(struct hisi_qm *qm) in sec_show_last_regs_uninit() argument
951 struct qm_debug *debug = &qm->debug; in sec_show_last_regs_uninit()
953 if (qm->fun_type == QM_HW_VF || !debug->last_words) in sec_show_last_regs_uninit()
960 static void sec_show_last_dfx_regs(struct hisi_qm *qm) in sec_show_last_dfx_regs() argument
962 struct qm_debug *debug = &qm->debug; in sec_show_last_dfx_regs()
963 struct pci_dev *pdev = qm->pdev; in sec_show_last_dfx_regs()
967 if (qm->fun_type == QM_HW_VF || !debug->last_words) in sec_show_last_dfx_regs()
972 val = readl_relaxed(qm->io_base + sec_dfx_regs[i].offset); in sec_show_last_dfx_regs()
979 static void sec_log_hw_error(struct hisi_qm *qm, u32 err_sts) in sec_log_hw_error() argument
982 struct device *dev = &qm->pdev->dev; in sec_log_hw_error()
991 err_val = readl(qm->io_base + in sec_log_hw_error()
1002 static u32 sec_get_hw_err_status(struct hisi_qm *qm) in sec_get_hw_err_status() argument
1004 return readl(qm->io_base + SEC_CORE_INT_STATUS); in sec_get_hw_err_status()
1007 static void sec_clear_hw_err_status(struct hisi_qm *qm, u32 err_sts) in sec_clear_hw_err_status() argument
1009 writel(err_sts, qm->io_base + SEC_CORE_INT_SOURCE); in sec_clear_hw_err_status()
1012 static void sec_disable_error_report(struct hisi_qm *qm, u32 err_type) in sec_disable_error_report() argument
1016 nfe_mask = hisi_qm_get_hw_info(qm, sec_basic_info, SEC_NFE_MASK_CAP, qm->cap_ver); in sec_disable_error_report()
1017 writel(nfe_mask & (~err_type), qm->io_base + SEC_RAS_NFE_REG); in sec_disable_error_report()
1020 static void sec_open_axi_master_ooo(struct hisi_qm *qm) in sec_open_axi_master_ooo() argument
1024 val = readl(qm->io_base + SEC_CONTROL_REG); in sec_open_axi_master_ooo()
1025 writel(val & SEC_AXI_SHUTDOWN_DISABLE, qm->io_base + SEC_CONTROL_REG); in sec_open_axi_master_ooo()
1026 writel(val | SEC_AXI_SHUTDOWN_ENABLE, qm->io_base + SEC_CONTROL_REG); in sec_open_axi_master_ooo()
1029 static enum acc_err_result sec_get_err_result(struct hisi_qm *qm) in sec_get_err_result() argument
1033 err_status = sec_get_hw_err_status(qm); in sec_get_err_result()
1035 if (err_status & qm->err_info.ecc_2bits_mask) in sec_get_err_result()
1036 qm->err_status.is_dev_ecc_mbit = true; in sec_get_err_result()
1037 sec_log_hw_error(qm, err_status); in sec_get_err_result()
1039 if (err_status & qm->err_info.dev_reset_mask) { in sec_get_err_result()
1041 sec_disable_error_report(qm, err_status); in sec_get_err_result()
1044 sec_clear_hw_err_status(qm, err_status); in sec_get_err_result()
1050 static void sec_err_info_init(struct hisi_qm *qm) in sec_err_info_init() argument
1052 struct hisi_qm_err_info *err_info = &qm->err_info; in sec_err_info_init()
1055 err_info->ce = hisi_qm_get_hw_info(qm, sec_basic_info, SEC_QM_CE_MASK_CAP, qm->cap_ver); in sec_err_info_init()
1056 err_info->nfe = hisi_qm_get_hw_info(qm, sec_basic_info, SEC_QM_NFE_MASK_CAP, qm->cap_ver); in sec_err_info_init()
1058 err_info->qm_shutdown_mask = hisi_qm_get_hw_info(qm, sec_basic_info, in sec_err_info_init()
1059 SEC_QM_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver); in sec_err_info_init()
1060 err_info->dev_shutdown_mask = hisi_qm_get_hw_info(qm, sec_basic_info, in sec_err_info_init()
1061 SEC_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver); in sec_err_info_init()
1062 err_info->qm_reset_mask = hisi_qm_get_hw_info(qm, sec_basic_info, in sec_err_info_init()
1063 SEC_QM_RESET_MASK_CAP, qm->cap_ver); in sec_err_info_init()
1064 err_info->dev_reset_mask = hisi_qm_get_hw_info(qm, sec_basic_info, in sec_err_info_init()
1065 SEC_RESET_MASK_CAP, qm->cap_ver); in sec_err_info_init()
1086 struct hisi_qm *qm = &sec->qm; in sec_pf_probe_init() local
1089 ret = sec_set_user_domain_and_cache(qm); in sec_pf_probe_init()
1093 sec_open_sva_prefetch(qm); in sec_pf_probe_init()
1094 hisi_qm_dev_err_init(qm); in sec_pf_probe_init()
1095 sec_debug_regs_clear(qm); in sec_pf_probe_init()
1096 ret = sec_show_last_regs_init(qm); in sec_pf_probe_init()
1098 pci_err(qm->pdev, "Failed to init last word regs!\n"); in sec_pf_probe_init()
1103 static int sec_pre_store_cap_reg(struct hisi_qm *qm) in sec_pre_store_cap_reg() argument
1106 struct pci_dev *pdev = qm->pdev; in sec_pre_store_cap_reg()
1116 sec_cap[i].cap_val = hisi_qm_get_hw_info(qm, sec_basic_info, in sec_pre_store_cap_reg()
1117 sec_pre_store_caps[i], qm->cap_ver); in sec_pre_store_cap_reg()
1120 qm->cap_tables.dev_cap_table = sec_cap; in sec_pre_store_cap_reg()
1125 static int sec_qm_init(struct hisi_qm *qm, struct pci_dev *pdev) in sec_qm_init() argument
1130 qm->pdev = pdev; in sec_qm_init()
1131 qm->ver = pdev->revision; in sec_qm_init()
1132 qm->mode = uacce_mode; in sec_qm_init()
1133 qm->sqe_size = SEC_SQE_SIZE; in sec_qm_init()
1134 qm->dev_name = sec_name; in sec_qm_init()
1136 qm->fun_type = (pdev->device == PCI_DEVICE_ID_HUAWEI_SEC_PF) ? in sec_qm_init()
1138 if (qm->fun_type == QM_HW_PF) { in sec_qm_init()
1139 qm->qp_base = SEC_PF_DEF_Q_BASE; in sec_qm_init()
1140 qm->qp_num = pf_q_num; in sec_qm_init()
1141 qm->debug.curr_qm_qp_num = pf_q_num; in sec_qm_init()
1142 qm->qm_list = &sec_devices; in sec_qm_init()
1143 qm->err_ini = &sec_err_ini; in sec_qm_init()
1145 set_bit(QM_MODULE_PARAM, &qm->misc_ctl); in sec_qm_init()
1146 } else if (qm->fun_type == QM_HW_VF && qm->ver == QM_HW_V1) { in sec_qm_init()
1148 * have no way to get qm configure in VM in v1 hardware, in sec_qm_init()
1153 qm->qp_base = SEC_PF_DEF_Q_NUM; in sec_qm_init()
1154 qm->qp_num = SEC_QUEUE_NUM_V1 - SEC_PF_DEF_Q_NUM; in sec_qm_init()
1157 ret = hisi_qm_init(qm); in sec_qm_init()
1159 pci_err(qm->pdev, "Failed to init sec qm configures!\n"); in sec_qm_init()
1164 ret = sec_pre_store_cap_reg(qm); in sec_qm_init()
1166 pci_err(qm->pdev, "Failed to pre-store capability registers!\n"); in sec_qm_init()
1167 hisi_qm_uninit(qm); in sec_qm_init()
1171 alg_msk = sec_get_alg_bitmap(qm, SEC_DEV_ALG_BITMAP_HIGH_IDX, SEC_DEV_ALG_BITMAP_LOW_IDX); in sec_qm_init()
1172 ret = hisi_qm_set_algs(qm, alg_msk, sec_dev_algs, ARRAY_SIZE(sec_dev_algs)); in sec_qm_init()
1174 pci_err(qm->pdev, "Failed to set sec algs!\n"); in sec_qm_init()
1175 hisi_qm_uninit(qm); in sec_qm_init()
1181 static void sec_qm_uninit(struct hisi_qm *qm) in sec_qm_uninit() argument
1183 hisi_qm_uninit(qm); in sec_qm_uninit()
1189 struct hisi_qm *qm = &sec->qm; in sec_probe_init() local
1192 if (qm->fun_type == QM_HW_PF) { in sec_probe_init()
1197 if (qm->ver >= QM_HW_V3) { in sec_probe_init()
1199 qm->type_rate = type_rate; in sec_probe_init()
1206 static void sec_probe_uninit(struct hisi_qm *qm) in sec_probe_uninit() argument
1208 if (qm->fun_type == QM_HW_VF) in sec_probe_uninit()
1211 sec_debug_regs_clear(qm); in sec_probe_uninit()
1212 sec_show_last_regs_uninit(qm); in sec_probe_uninit()
1213 sec_close_sva_prefetch(qm); in sec_probe_uninit()
1214 hisi_qm_dev_err_uninit(qm); in sec_probe_uninit()
1220 struct device *dev = &sec->qm.pdev->dev; in sec_iommu_used_check()
1237 struct hisi_qm *qm; in sec_probe() local
1244 qm = &sec->qm; in sec_probe()
1245 ret = sec_qm_init(qm, pdev); in sec_probe()
1247 pci_err(pdev, "Failed to init SEC QM (%d)!\n", ret); in sec_probe()
1260 ret = hisi_qm_start(qm); in sec_probe()
1262 pci_err(pdev, "Failed to start sec qm!\n"); in sec_probe()
1266 ret = sec_debugfs_init(qm); in sec_probe()
1270 if (qm->qp_num >= ctx_q_num) { in sec_probe()
1271 ret = hisi_qm_alg_register(qm, &sec_devices); in sec_probe()
1277 pci_warn(qm->pdev, in sec_probe()
1281 if (qm->uacce) { in sec_probe()
1282 ret = uacce_register(qm->uacce); in sec_probe()
1289 if (qm->fun_type == QM_HW_PF && vfs_num) { in sec_probe()
1295 hisi_qm_pm_init(qm); in sec_probe()
1300 if (qm->qp_num >= ctx_q_num) in sec_probe()
1301 hisi_qm_alg_unregister(qm, &sec_devices); in sec_probe()
1303 sec_debugfs_exit(qm); in sec_probe()
1304 hisi_qm_stop(qm, QM_NORMAL); in sec_probe()
1306 sec_probe_uninit(qm); in sec_probe()
1308 sec_qm_uninit(qm); in sec_probe()
1314 struct hisi_qm *qm = pci_get_drvdata(pdev); in sec_remove() local
1316 hisi_qm_pm_uninit(qm); in sec_remove()
1317 hisi_qm_wait_task_finish(qm, &sec_devices); in sec_remove()
1318 if (qm->qp_num >= ctx_q_num) in sec_remove()
1319 hisi_qm_alg_unregister(qm, &sec_devices); in sec_remove()
1321 if (qm->fun_type == QM_HW_PF && qm->vfs_num) in sec_remove()
1324 sec_debugfs_exit(qm); in sec_remove()
1326 (void)hisi_qm_stop(qm, QM_NORMAL); in sec_remove()
1327 sec_probe_uninit(qm); in sec_remove()
1329 sec_qm_uninit(qm); in sec_remove()