Lines Matching full:qm
368 struct hisi_qm *qm = s->private; in hzip_diff_regs_show() local
370 hisi_qm_acc_diff_regs_dump(qm, s, qm->debug.acc_diff_regs, in hzip_diff_regs_show()
461 bool hisi_zip_alg_support(struct hisi_qm *qm, u32 alg) in hisi_zip_alg_support() argument
465 cap_val = qm->cap_tables.dev_cap_table[ZIP_DRV_ALG_BITMAP_IDX].cap_val; in hisi_zip_alg_support()
472 static int hisi_zip_set_high_perf(struct hisi_qm *qm) in hisi_zip_set_high_perf() argument
477 val = readl_relaxed(qm->io_base + HZIP_HIGH_PERF_OFFSET); in hisi_zip_set_high_perf()
484 writel(val, qm->io_base + HZIP_HIGH_PERF_OFFSET); in hisi_zip_set_high_perf()
485 ret = readl_relaxed_poll_timeout(qm->io_base + HZIP_HIGH_PERF_OFFSET, in hisi_zip_set_high_perf()
489 pci_err(qm->pdev, "failed to set perf mode\n"); in hisi_zip_set_high_perf()
494 static void hisi_zip_open_sva_prefetch(struct hisi_qm *qm) in hisi_zip_open_sva_prefetch() argument
499 if (!test_bit(QM_SUPPORT_SVA_PREFETCH, &qm->caps)) in hisi_zip_open_sva_prefetch()
503 val = readl_relaxed(qm->io_base + HZIP_PREFETCH_CFG); in hisi_zip_open_sva_prefetch()
505 writel(val, qm->io_base + HZIP_PREFETCH_CFG); in hisi_zip_open_sva_prefetch()
507 ret = readl_relaxed_poll_timeout(qm->io_base + HZIP_PREFETCH_CFG, in hisi_zip_open_sva_prefetch()
511 pci_err(qm->pdev, "failed to open sva prefetch\n"); in hisi_zip_open_sva_prefetch()
514 static void hisi_zip_close_sva_prefetch(struct hisi_qm *qm) in hisi_zip_close_sva_prefetch() argument
519 if (!test_bit(QM_SUPPORT_SVA_PREFETCH, &qm->caps)) in hisi_zip_close_sva_prefetch()
522 val = readl_relaxed(qm->io_base + HZIP_PREFETCH_CFG); in hisi_zip_close_sva_prefetch()
524 writel(val, qm->io_base + HZIP_PREFETCH_CFG); in hisi_zip_close_sva_prefetch()
526 ret = readl_relaxed_poll_timeout(qm->io_base + HZIP_SVA_TRANS, in hisi_zip_close_sva_prefetch()
530 pci_err(qm->pdev, "failed to close sva prefetch\n"); in hisi_zip_close_sva_prefetch()
533 static void hisi_zip_enable_clock_gate(struct hisi_qm *qm) in hisi_zip_enable_clock_gate() argument
537 if (qm->ver < QM_HW_V3) in hisi_zip_enable_clock_gate()
540 val = readl(qm->io_base + HZIP_CLOCK_GATE_CTRL); in hisi_zip_enable_clock_gate()
542 writel(val, qm->io_base + HZIP_CLOCK_GATE_CTRL); in hisi_zip_enable_clock_gate()
544 val = readl(qm->io_base + HZIP_PEH_CFG_AUTO_GATE); in hisi_zip_enable_clock_gate()
546 writel(val, qm->io_base + HZIP_PEH_CFG_AUTO_GATE); in hisi_zip_enable_clock_gate()
549 static int hisi_zip_set_user_domain_and_cache(struct hisi_qm *qm) in hisi_zip_set_user_domain_and_cache() argument
551 void __iomem *base = qm->io_base; in hisi_zip_set_user_domain_and_cache()
554 /* qm user domain */ in hisi_zip_set_user_domain_and_cache()
561 /* qm cache */ in hisi_zip_set_user_domain_and_cache()
579 if (qm->use_sva && qm->ver == QM_HW_V2) { in hisi_zip_set_user_domain_and_cache()
590 dcomp_bm = qm->cap_tables.dev_cap_table[ZIP_DECOMP_ENABLE_BITMAP_IDX].cap_val; in hisi_zip_set_user_domain_and_cache()
591 comp_bm = qm->cap_tables.dev_cap_table[ZIP_COMP_ENABLE_BITMAP_IDX].cap_val; in hisi_zip_set_user_domain_and_cache()
599 hisi_zip_enable_clock_gate(qm); in hisi_zip_set_user_domain_and_cache()
604 static void hisi_zip_master_ooo_ctrl(struct hisi_qm *qm, bool enable) in hisi_zip_master_ooo_ctrl() argument
608 val1 = readl(qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL); in hisi_zip_master_ooo_ctrl()
611 val2 = hisi_qm_get_hw_info(qm, zip_basic_cap_info, in hisi_zip_master_ooo_ctrl()
612 ZIP_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver); in hisi_zip_master_ooo_ctrl()
618 if (qm->ver > QM_HW_V2) in hisi_zip_master_ooo_ctrl()
619 writel(val2, qm->io_base + HZIP_OOO_SHUTDOWN_SEL); in hisi_zip_master_ooo_ctrl()
621 writel(val1, qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL); in hisi_zip_master_ooo_ctrl()
624 static void hisi_zip_hw_error_enable(struct hisi_qm *qm) in hisi_zip_hw_error_enable() argument
628 if (qm->ver == QM_HW_V1) { in hisi_zip_hw_error_enable()
630 qm->io_base + HZIP_CORE_INT_MASK_REG); in hisi_zip_hw_error_enable()
631 dev_info(&qm->pdev->dev, "Does not support hw error handle\n"); in hisi_zip_hw_error_enable()
635 nfe = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_NFE_MASK_CAP, qm->cap_ver); in hisi_zip_hw_error_enable()
636 ce = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_CE_MASK_CAP, qm->cap_ver); in hisi_zip_hw_error_enable()
639 writel(ce | nfe | HZIP_CORE_INT_RAS_FE_ENB_MASK, qm->io_base + HZIP_CORE_INT_SOURCE); in hisi_zip_hw_error_enable()
642 writel(ce, qm->io_base + HZIP_CORE_INT_RAS_CE_ENB); in hisi_zip_hw_error_enable()
643 writel(HZIP_CORE_INT_RAS_FE_ENB_MASK, qm->io_base + HZIP_CORE_INT_RAS_FE_ENB); in hisi_zip_hw_error_enable()
644 writel(nfe, qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB); in hisi_zip_hw_error_enable()
646 hisi_zip_master_ooo_ctrl(qm, true); in hisi_zip_hw_error_enable()
649 writel(0, qm->io_base + HZIP_CORE_INT_MASK_REG); in hisi_zip_hw_error_enable()
652 static void hisi_zip_hw_error_disable(struct hisi_qm *qm) in hisi_zip_hw_error_disable() argument
657 nfe = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_NFE_MASK_CAP, qm->cap_ver); in hisi_zip_hw_error_disable()
658 ce = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_CE_MASK_CAP, qm->cap_ver); in hisi_zip_hw_error_disable()
659 writel(ce | nfe | HZIP_CORE_INT_RAS_FE_ENB_MASK, qm->io_base + HZIP_CORE_INT_MASK_REG); in hisi_zip_hw_error_disable()
661 hisi_zip_master_ooo_ctrl(qm, false); in hisi_zip_hw_error_disable()
668 return &hisi_zip->qm; in file_to_qm()
671 static u32 clear_enable_read(struct hisi_qm *qm) in clear_enable_read() argument
673 return readl(qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE) & in clear_enable_read()
677 static int clear_enable_write(struct hisi_qm *qm, u32 val) in clear_enable_write() argument
684 tmp = (readl(qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE) & in clear_enable_write()
686 writel(tmp, qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE); in clear_enable_write()
695 struct hisi_qm *qm = file_to_qm(file); in hisi_zip_ctrl_debug_read() local
700 ret = hisi_qm_get_dfx_access(qm); in hisi_zip_ctrl_debug_read()
707 val = clear_enable_read(qm); in hisi_zip_ctrl_debug_read()
714 hisi_qm_put_dfx_access(qm); in hisi_zip_ctrl_debug_read()
720 hisi_qm_put_dfx_access(qm); in hisi_zip_ctrl_debug_read()
729 struct hisi_qm *qm = file_to_qm(file); in hisi_zip_ctrl_debug_write() local
749 ret = hisi_qm_get_dfx_access(qm); in hisi_zip_ctrl_debug_write()
756 ret = clear_enable_write(qm, val); in hisi_zip_ctrl_debug_write()
769 hisi_qm_put_dfx_access(qm); in hisi_zip_ctrl_debug_write()
809 static int hisi_zip_core_debug_init(struct hisi_qm *qm) in hisi_zip_core_debug_init() argument
812 struct device *dev = &qm->pdev->dev; in hisi_zip_core_debug_init()
818 zip_core_num = qm->cap_tables.dev_cap_table[ZIP_CORE_NUM_CAP_IDX].cap_val; in hisi_zip_core_debug_init()
819 zip_comp_core_num = qm->cap_tables.dev_cap_table[ZIP_CLUSTER_COMP_NUM_CAP_IDX].cap_val; in hisi_zip_core_debug_init()
834 regset->base = qm->io_base + core_offsets[i]; in hisi_zip_core_debug_init()
837 tmp_d = debugfs_create_dir(buf, qm->debug.debug_root); in hisi_zip_core_debug_init()
845 static void hisi_zip_dfx_debug_init(struct hisi_qm *qm) in hisi_zip_dfx_debug_init() argument
847 struct dfx_diff_registers *hzip_regs = qm->debug.acc_diff_regs; in hisi_zip_dfx_debug_init()
848 struct hisi_zip *zip = container_of(qm, struct hisi_zip, qm); in hisi_zip_dfx_debug_init()
854 tmp_dir = debugfs_create_dir("zip_dfx", qm->debug.debug_root); in hisi_zip_dfx_debug_init()
862 if (qm->fun_type == QM_HW_PF && hzip_regs) in hisi_zip_dfx_debug_init()
864 qm, &hzip_diff_regs_fops); in hisi_zip_dfx_debug_init()
867 static int hisi_zip_ctrl_debug_init(struct hisi_qm *qm) in hisi_zip_ctrl_debug_init() argument
869 struct hisi_zip *zip = container_of(qm, struct hisi_zip, qm); in hisi_zip_ctrl_debug_init()
878 qm->debug.debug_root, in hisi_zip_ctrl_debug_init()
883 return hisi_zip_core_debug_init(qm); in hisi_zip_ctrl_debug_init()
886 static int hisi_zip_debugfs_init(struct hisi_qm *qm) in hisi_zip_debugfs_init() argument
888 struct device *dev = &qm->pdev->dev; in hisi_zip_debugfs_init()
894 qm->debug.sqe_mask_offset = HZIP_SQE_MASK_OFFSET; in hisi_zip_debugfs_init()
895 qm->debug.sqe_mask_len = HZIP_SQE_MASK_LEN; in hisi_zip_debugfs_init()
896 qm->debug.debug_root = dev_d; in hisi_zip_debugfs_init()
897 ret = hisi_qm_regs_debugfs_init(qm, hzip_diff_regs, ARRAY_SIZE(hzip_diff_regs)); in hisi_zip_debugfs_init()
903 hisi_qm_debug_init(qm); in hisi_zip_debugfs_init()
905 if (qm->fun_type == QM_HW_PF) { in hisi_zip_debugfs_init()
906 ret = hisi_zip_ctrl_debug_init(qm); in hisi_zip_debugfs_init()
911 hisi_zip_dfx_debug_init(qm); in hisi_zip_debugfs_init()
916 hisi_qm_regs_debugfs_uninit(qm, ARRAY_SIZE(hzip_diff_regs)); in hisi_zip_debugfs_init()
923 static void hisi_zip_debug_regs_clear(struct hisi_qm *qm) in hisi_zip_debug_regs_clear() argument
928 writel(HZIP_RD_CNT_CLR_CE_EN, qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE); in hisi_zip_debug_regs_clear()
931 readl(qm->io_base + core_offsets[i] + in hisi_zip_debug_regs_clear()
935 writel(0x0, qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE); in hisi_zip_debug_regs_clear()
937 hisi_qm_debug_regs_clear(qm); in hisi_zip_debug_regs_clear()
940 static void hisi_zip_debugfs_exit(struct hisi_qm *qm) in hisi_zip_debugfs_exit() argument
942 hisi_qm_regs_debugfs_uninit(qm, ARRAY_SIZE(hzip_diff_regs)); in hisi_zip_debugfs_exit()
944 debugfs_remove_recursive(qm->debug.debug_root); in hisi_zip_debugfs_exit()
946 if (qm->fun_type == QM_HW_PF) { in hisi_zip_debugfs_exit()
947 hisi_zip_debug_regs_clear(qm); in hisi_zip_debugfs_exit()
948 qm->debug.curr_qm_qp_num = 0; in hisi_zip_debugfs_exit()
952 static int hisi_zip_show_last_regs_init(struct hisi_qm *qm) in hisi_zip_show_last_regs_init() argument
956 struct qm_debug *debug = &qm->debug; in hisi_zip_show_last_regs_init()
961 zip_core_num = qm->cap_tables.dev_cap_table[ZIP_CORE_NUM_CAP_IDX].cap_val; in hisi_zip_show_last_regs_init()
969 io_base = qm->io_base + hzip_com_dfx_regs[i].offset; in hisi_zip_show_last_regs_init()
974 io_base = qm->io_base + core_offsets[i]; in hisi_zip_show_last_regs_init()
985 static void hisi_zip_show_last_regs_uninit(struct hisi_qm *qm) in hisi_zip_show_last_regs_uninit() argument
987 struct qm_debug *debug = &qm->debug; in hisi_zip_show_last_regs_uninit()
989 if (qm->fun_type == QM_HW_VF || !debug->last_words) in hisi_zip_show_last_regs_uninit()
996 static void hisi_zip_show_last_dfx_regs(struct hisi_qm *qm) in hisi_zip_show_last_dfx_regs() argument
1001 struct qm_debug *debug = &qm->debug; in hisi_zip_show_last_dfx_regs()
1007 if (qm->fun_type == QM_HW_VF || !debug->last_words) in hisi_zip_show_last_dfx_regs()
1011 val = readl_relaxed(qm->io_base + hzip_com_dfx_regs[i].offset); in hisi_zip_show_last_dfx_regs()
1013 pci_info(qm->pdev, "com_dfx: %s \t= 0x%08x => 0x%08x\n", in hisi_zip_show_last_dfx_regs()
1017 zip_core_num = qm->cap_tables.dev_cap_table[ZIP_CORE_NUM_CAP_IDX].cap_val; in hisi_zip_show_last_dfx_regs()
1018 zip_comp_core_num = qm->cap_tables.dev_cap_table[ZIP_CLUSTER_COMP_NUM_CAP_IDX].cap_val; in hisi_zip_show_last_dfx_regs()
1026 base = qm->io_base + core_offsets[i]; in hisi_zip_show_last_dfx_regs()
1028 pci_info(qm->pdev, "==>%s:\n", buf); in hisi_zip_show_last_dfx_regs()
1034 pci_info(qm->pdev, "%s \t= 0x%08x => 0x%08x\n", in hisi_zip_show_last_dfx_regs()
1041 static void hisi_zip_log_hw_error(struct hisi_qm *qm, u32 err_sts) in hisi_zip_log_hw_error() argument
1044 struct device *dev = &qm->pdev->dev; in hisi_zip_log_hw_error()
1053 err_val = readl(qm->io_base + in hisi_zip_log_hw_error()
1064 static u32 hisi_zip_get_hw_err_status(struct hisi_qm *qm) in hisi_zip_get_hw_err_status() argument
1066 return readl(qm->io_base + HZIP_CORE_INT_STATUS); in hisi_zip_get_hw_err_status()
1069 static void hisi_zip_clear_hw_err_status(struct hisi_qm *qm, u32 err_sts) in hisi_zip_clear_hw_err_status() argument
1071 writel(err_sts, qm->io_base + HZIP_CORE_INT_SOURCE); in hisi_zip_clear_hw_err_status()
1074 static void hisi_zip_disable_error_report(struct hisi_qm *qm, u32 err_type) in hisi_zip_disable_error_report() argument
1078 nfe_mask = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_NFE_MASK_CAP, qm->cap_ver); in hisi_zip_disable_error_report()
1079 writel(nfe_mask & (~err_type), qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB); in hisi_zip_disable_error_report()
1082 static void hisi_zip_open_axi_master_ooo(struct hisi_qm *qm) in hisi_zip_open_axi_master_ooo() argument
1086 val = readl(qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL); in hisi_zip_open_axi_master_ooo()
1089 qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL); in hisi_zip_open_axi_master_ooo()
1092 qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL); in hisi_zip_open_axi_master_ooo()
1095 static void hisi_zip_close_axi_master_ooo(struct hisi_qm *qm) in hisi_zip_close_axi_master_ooo() argument
1100 nfe_enb = readl(qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB); in hisi_zip_close_axi_master_ooo()
1102 qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB); in hisi_zip_close_axi_master_ooo()
1106 qm->io_base + HZIP_CORE_INT_SET); in hisi_zip_close_axi_master_ooo()
1109 static enum acc_err_result hisi_zip_get_err_result(struct hisi_qm *qm) in hisi_zip_get_err_result() argument
1113 err_status = hisi_zip_get_hw_err_status(qm); in hisi_zip_get_err_result()
1115 if (err_status & qm->err_info.ecc_2bits_mask) in hisi_zip_get_err_result()
1116 qm->err_status.is_dev_ecc_mbit = true; in hisi_zip_get_err_result()
1117 hisi_zip_log_hw_error(qm, err_status); in hisi_zip_get_err_result()
1119 if (err_status & qm->err_info.dev_reset_mask) { in hisi_zip_get_err_result()
1121 hisi_zip_disable_error_report(qm, err_status); in hisi_zip_get_err_result()
1124 hisi_zip_clear_hw_err_status(qm, err_status); in hisi_zip_get_err_result()
1130 static void hisi_zip_err_info_init(struct hisi_qm *qm) in hisi_zip_err_info_init() argument
1132 struct hisi_qm_err_info *err_info = &qm->err_info; in hisi_zip_err_info_init()
1135 err_info->ce = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_QM_CE_MASK_CAP, qm->cap_ver); in hisi_zip_err_info_init()
1136 err_info->nfe = hisi_qm_get_hw_info(qm, zip_basic_cap_info, in hisi_zip_err_info_init()
1137 ZIP_QM_NFE_MASK_CAP, qm->cap_ver); in hisi_zip_err_info_init()
1139 err_info->qm_shutdown_mask = hisi_qm_get_hw_info(qm, zip_basic_cap_info, in hisi_zip_err_info_init()
1140 ZIP_QM_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver); in hisi_zip_err_info_init()
1141 err_info->dev_shutdown_mask = hisi_qm_get_hw_info(qm, zip_basic_cap_info, in hisi_zip_err_info_init()
1142 ZIP_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver); in hisi_zip_err_info_init()
1143 err_info->qm_reset_mask = hisi_qm_get_hw_info(qm, zip_basic_cap_info, in hisi_zip_err_info_init()
1144 ZIP_QM_RESET_MASK_CAP, qm->cap_ver); in hisi_zip_err_info_init()
1145 err_info->dev_reset_mask = hisi_qm_get_hw_info(qm, zip_basic_cap_info, in hisi_zip_err_info_init()
1146 ZIP_RESET_MASK_CAP, qm->cap_ver); in hisi_zip_err_info_init()
1168 struct hisi_qm *qm = &hisi_zip->qm; in hisi_zip_pf_probe_init() local
1172 ctrl = devm_kzalloc(&qm->pdev->dev, sizeof(*ctrl), GFP_KERNEL); in hisi_zip_pf_probe_init()
1179 ret = hisi_zip_set_user_domain_and_cache(qm); in hisi_zip_pf_probe_init()
1183 ret = hisi_zip_set_high_perf(qm); in hisi_zip_pf_probe_init()
1187 hisi_zip_open_sva_prefetch(qm); in hisi_zip_pf_probe_init()
1188 hisi_qm_dev_err_init(qm); in hisi_zip_pf_probe_init()
1189 hisi_zip_debug_regs_clear(qm); in hisi_zip_pf_probe_init()
1191 ret = hisi_zip_show_last_regs_init(qm); in hisi_zip_pf_probe_init()
1193 pci_err(qm->pdev, "Failed to init last word regs!\n"); in hisi_zip_pf_probe_init()
1198 static int zip_pre_store_cap_reg(struct hisi_qm *qm) in zip_pre_store_cap_reg() argument
1201 struct pci_dev *pdev = qm->pdev; in zip_pre_store_cap_reg()
1211 zip_cap[i].cap_val = hisi_qm_get_hw_info(qm, zip_basic_cap_info, in zip_pre_store_cap_reg()
1212 zip_pre_store_caps[i], qm->cap_ver); in zip_pre_store_cap_reg()
1215 qm->cap_tables.dev_cap_table = zip_cap; in zip_pre_store_cap_reg()
1220 static int hisi_zip_qm_init(struct hisi_qm *qm, struct pci_dev *pdev) in hisi_zip_qm_init() argument
1225 qm->pdev = pdev; in hisi_zip_qm_init()
1226 qm->ver = pdev->revision; in hisi_zip_qm_init()
1227 qm->mode = uacce_mode; in hisi_zip_qm_init()
1228 qm->sqe_size = HZIP_SQE_SIZE; in hisi_zip_qm_init()
1229 qm->dev_name = hisi_zip_name; in hisi_zip_qm_init()
1231 qm->fun_type = (pdev->device == PCI_DEVICE_ID_HUAWEI_ZIP_PF) ? in hisi_zip_qm_init()
1233 if (qm->fun_type == QM_HW_PF) { in hisi_zip_qm_init()
1234 qm->qp_base = HZIP_PF_DEF_Q_BASE; in hisi_zip_qm_init()
1235 qm->qp_num = pf_q_num; in hisi_zip_qm_init()
1236 qm->debug.curr_qm_qp_num = pf_q_num; in hisi_zip_qm_init()
1237 qm->qm_list = &zip_devices; in hisi_zip_qm_init()
1238 qm->err_ini = &hisi_zip_err_ini; in hisi_zip_qm_init()
1240 set_bit(QM_MODULE_PARAM, &qm->misc_ctl); in hisi_zip_qm_init()
1241 } else if (qm->fun_type == QM_HW_VF && qm->ver == QM_HW_V1) { in hisi_zip_qm_init()
1243 * have no way to get qm configure in VM in v1 hardware, in hisi_zip_qm_init()
1249 qm->qp_base = HZIP_PF_DEF_Q_NUM; in hisi_zip_qm_init()
1250 qm->qp_num = HZIP_QUEUE_NUM_V1 - HZIP_PF_DEF_Q_NUM; in hisi_zip_qm_init()
1253 ret = hisi_qm_init(qm); in hisi_zip_qm_init()
1255 pci_err(qm->pdev, "Failed to init zip qm configures!\n"); in hisi_zip_qm_init()
1260 ret = zip_pre_store_cap_reg(qm); in hisi_zip_qm_init()
1262 pci_err(qm->pdev, "Failed to pre-store capability registers!\n"); in hisi_zip_qm_init()
1263 hisi_qm_uninit(qm); in hisi_zip_qm_init()
1267 alg_msk = qm->cap_tables.dev_cap_table[ZIP_DEV_ALG_BITMAP_IDX].cap_val; in hisi_zip_qm_init()
1268 ret = hisi_qm_set_algs(qm, alg_msk, zip_dev_algs, ARRAY_SIZE(zip_dev_algs)); in hisi_zip_qm_init()
1270 pci_err(qm->pdev, "Failed to set zip algs!\n"); in hisi_zip_qm_init()
1271 hisi_qm_uninit(qm); in hisi_zip_qm_init()
1277 static void hisi_zip_qm_uninit(struct hisi_qm *qm) in hisi_zip_qm_uninit() argument
1279 hisi_qm_uninit(qm); in hisi_zip_qm_uninit()
1285 struct hisi_qm *qm = &hisi_zip->qm; in hisi_zip_probe_init() local
1288 if (qm->fun_type == QM_HW_PF) { in hisi_zip_probe_init()
1293 if (qm->ver >= QM_HW_V3) { in hisi_zip_probe_init()
1298 qm->type_rate = type_rate; in hisi_zip_probe_init()
1305 static void hisi_zip_probe_uninit(struct hisi_qm *qm) in hisi_zip_probe_uninit() argument
1307 if (qm->fun_type == QM_HW_VF) in hisi_zip_probe_uninit()
1310 hisi_zip_show_last_regs_uninit(qm); in hisi_zip_probe_uninit()
1311 hisi_zip_close_sva_prefetch(qm); in hisi_zip_probe_uninit()
1312 hisi_qm_dev_err_uninit(qm); in hisi_zip_probe_uninit()
1318 struct hisi_qm *qm; in hisi_zip_probe() local
1325 qm = &hisi_zip->qm; in hisi_zip_probe()
1327 ret = hisi_zip_qm_init(qm, pdev); in hisi_zip_probe()
1329 pci_err(pdev, "Failed to init ZIP QM (%d)!\n", ret); in hisi_zip_probe()
1339 ret = hisi_qm_start(qm); in hisi_zip_probe()
1343 ret = hisi_zip_debugfs_init(qm); in hisi_zip_probe()
1347 ret = hisi_qm_alg_register(qm, &zip_devices); in hisi_zip_probe()
1353 if (qm->uacce) { in hisi_zip_probe()
1354 ret = uacce_register(qm->uacce); in hisi_zip_probe()
1361 if (qm->fun_type == QM_HW_PF && vfs_num > 0) { in hisi_zip_probe()
1367 hisi_qm_pm_init(qm); in hisi_zip_probe()
1372 hisi_qm_alg_unregister(qm, &zip_devices); in hisi_zip_probe()
1375 hisi_zip_debugfs_exit(qm); in hisi_zip_probe()
1376 hisi_qm_stop(qm, QM_NORMAL); in hisi_zip_probe()
1379 hisi_zip_probe_uninit(qm); in hisi_zip_probe()
1382 hisi_zip_qm_uninit(qm); in hisi_zip_probe()
1389 struct hisi_qm *qm = pci_get_drvdata(pdev); in hisi_zip_remove() local
1391 hisi_qm_pm_uninit(qm); in hisi_zip_remove()
1392 hisi_qm_wait_task_finish(qm, &zip_devices); in hisi_zip_remove()
1393 hisi_qm_alg_unregister(qm, &zip_devices); in hisi_zip_remove()
1395 if (qm->fun_type == QM_HW_PF && qm->vfs_num) in hisi_zip_remove()
1398 hisi_zip_debugfs_exit(qm); in hisi_zip_remove()
1399 hisi_qm_stop(qm, QM_NORMAL); in hisi_zip_remove()
1400 hisi_zip_probe_uninit(qm); in hisi_zip_remove()
1401 hisi_zip_qm_uninit(qm); in hisi_zip_remove()