Lines Matching +full:stm32 +full:- +full:uart
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Driver for STM32 DMA controller
5 * Inspired by dma-jz4740.c and tegra20-apb-dma.c
9 * Pierre-Yves Mordret <pierre-yves.mordret@st.com>
16 #include <linux/dma-mapping.h>
32 #include "virt-dma.h"
50 * If (chan->id % 4) is 2 or 3, left shift the mask by 16 bits;
65 #define STM32_DMA_SCR_TRBUFF BIT(20) /* Bufferable transfer for USART/UART */
159 * struct stm32_dma_cfg - STM32 DMA custom configuration
198 * struct stm32_dma_mdma_config - STM32 DMA MDMA configuration
199 * @stream_id: DMA request to trigger STM32 MDMA transfer
201 * used by STM32 MDMA to clear DMA Transfer Complete flag
238 return container_of(chan->vchan.chan.device, struct stm32_dma_device, in stm32_dma_get_dev()
254 return &chan->vchan.chan.dev->device; in chan2dev()
259 return readl_relaxed(dmadev->base + reg); in stm32_dma_read()
264 writel_relaxed(val, dmadev->base + reg); in stm32_dma_write()
279 return -EINVAL; in stm32_dma_get_width()
298 if (buf_addr & (max_width - 1)) in stm32_dma_get_max_width()
379 return -EINVAL; in stm32_dma_get_burst()
386 chan->chan_reg.dma_sfcr &= ~STM32_DMA_SFCR_MASK; in stm32_dma_set_fifo_config()
387 chan->chan_reg.dma_scr &= ~STM32_DMA_SCR_DMEIE; in stm32_dma_set_fifo_config()
391 chan->chan_reg.dma_scr |= STM32_DMA_SCR_DMEIE; in stm32_dma_set_fifo_config()
394 chan->chan_reg.dma_sfcr |= STM32_DMA_SFCR_MASK; in stm32_dma_set_fifo_config()
403 memcpy(&chan->dma_sconfig, config, sizeof(*config)); in stm32_dma_slave_config()
405 /* Check if user is requesting DMA to trigger STM32 MDMA */ in stm32_dma_slave_config()
406 if (config->peripheral_size) { in stm32_dma_slave_config()
407 config->peripheral_config = &chan->mdma_config; in stm32_dma_slave_config()
408 config->peripheral_size = sizeof(chan->mdma_config); in stm32_dma_slave_config()
409 chan->trig_mdma = true; in stm32_dma_slave_config()
412 chan->config_init = true; in stm32_dma_slave_config()
427 dma_isr = stm32_dma_read(dmadev, STM32_DMA_ISR(chan->id)); in stm32_dma_irq_status()
428 flags = dma_isr >> STM32_DMA_FLAGS_SHIFT(chan->id); in stm32_dma_irq_status()
443 dma_ifcr = flags << STM32_DMA_FLAGS_SHIFT(chan->id); in stm32_dma_irq_clear()
445 stm32_dma_write(dmadev, STM32_DMA_IFCR(chan->id), dma_ifcr); in stm32_dma_irq_clear()
453 id = chan->id; in stm32_dma_disable_chan()
461 return readl_relaxed_poll_timeout_atomic(dmadev->base + reg, in stm32_dma_disable_chan()
476 dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id)); in stm32_dma_stop()
478 stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), dma_scr); in stm32_dma_stop()
479 dma_sfcr = stm32_dma_read(dmadev, STM32_DMA_SFCR(chan->id)); in stm32_dma_stop()
481 stm32_dma_write(dmadev, STM32_DMA_SFCR(chan->id), dma_sfcr); in stm32_dma_stop()
496 chan->busy = false; in stm32_dma_stop()
497 chan->status = DMA_COMPLETE; in stm32_dma_stop()
506 spin_lock_irqsave(&chan->vchan.lock, flags); in stm32_dma_terminate_all()
508 if (chan->desc) { in stm32_dma_terminate_all()
509 dma_cookie_complete(&chan->desc->vdesc.tx); in stm32_dma_terminate_all()
510 vchan_terminate_vdesc(&chan->desc->vdesc); in stm32_dma_terminate_all()
511 if (chan->busy) in stm32_dma_terminate_all()
513 chan->desc = NULL; in stm32_dma_terminate_all()
516 vchan_get_all_descriptors(&chan->vchan, &head); in stm32_dma_terminate_all()
517 spin_unlock_irqrestore(&chan->vchan.lock, flags); in stm32_dma_terminate_all()
518 vchan_dma_desc_free_list(&chan->vchan, &head); in stm32_dma_terminate_all()
527 vchan_synchronize(&chan->vchan); in stm32_dma_synchronize()
533 u32 scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id)); in stm32_dma_dump_reg()
534 u32 ndtr = stm32_dma_read(dmadev, STM32_DMA_SNDTR(chan->id)); in stm32_dma_dump_reg()
535 u32 spar = stm32_dma_read(dmadev, STM32_DMA_SPAR(chan->id)); in stm32_dma_dump_reg()
536 u32 sm0ar = stm32_dma_read(dmadev, STM32_DMA_SM0AR(chan->id)); in stm32_dma_dump_reg()
537 u32 sm1ar = stm32_dma_read(dmadev, STM32_DMA_SM1AR(chan->id)); in stm32_dma_dump_reg()
538 u32 sfcr = stm32_dma_read(dmadev, STM32_DMA_SFCR(chan->id)); in stm32_dma_dump_reg()
550 chan->next_sg++; in stm32_dma_sg_inc()
551 if (chan->desc->cyclic && (chan->next_sg == chan->desc->num_sgs)) in stm32_dma_sg_inc()
552 chan->next_sg = 0; in stm32_dma_sg_inc()
570 if (!chan->desc) { in stm32_dma_start_transfer()
571 vdesc = vchan_next_desc(&chan->vchan); in stm32_dma_start_transfer()
575 list_del(&vdesc->node); in stm32_dma_start_transfer()
577 chan->desc = to_stm32_dma_desc(vdesc); in stm32_dma_start_transfer()
578 chan->next_sg = 0; in stm32_dma_start_transfer()
581 if (chan->next_sg == chan->desc->num_sgs) in stm32_dma_start_transfer()
582 chan->next_sg = 0; in stm32_dma_start_transfer()
584 sg_req = &chan->desc->sg_req[chan->next_sg]; in stm32_dma_start_transfer()
585 reg = &sg_req->chan_reg; in stm32_dma_start_transfer()
587 /* When DMA triggers STM32 MDMA, DMA Transfer Complete is managed by STM32 MDMA */ in stm32_dma_start_transfer()
588 if (chan->trig_mdma && chan->dma_sconfig.direction != DMA_MEM_TO_DEV) in stm32_dma_start_transfer()
589 reg->dma_scr &= ~STM32_DMA_SCR_TCIE; in stm32_dma_start_transfer()
591 reg->dma_scr &= ~STM32_DMA_SCR_EN; in stm32_dma_start_transfer()
592 stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), reg->dma_scr); in stm32_dma_start_transfer()
593 stm32_dma_write(dmadev, STM32_DMA_SPAR(chan->id), reg->dma_spar); in stm32_dma_start_transfer()
594 stm32_dma_write(dmadev, STM32_DMA_SM0AR(chan->id), reg->dma_sm0ar); in stm32_dma_start_transfer()
595 stm32_dma_write(dmadev, STM32_DMA_SFCR(chan->id), reg->dma_sfcr); in stm32_dma_start_transfer()
596 stm32_dma_write(dmadev, STM32_DMA_SM1AR(chan->id), reg->dma_sm1ar); in stm32_dma_start_transfer()
597 stm32_dma_write(dmadev, STM32_DMA_SNDTR(chan->id), reg->dma_sndtr); in stm32_dma_start_transfer()
606 if (chan->desc->cyclic) in stm32_dma_start_transfer()
612 chan->busy = true; in stm32_dma_start_transfer()
613 chan->status = DMA_IN_PROGRESS; in stm32_dma_start_transfer()
614 reg->dma_scr |= STM32_DMA_SCR_EN; in stm32_dma_start_transfer()
615 stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), reg->dma_scr); in stm32_dma_start_transfer()
617 dev_dbg(chan2dev(chan), "vchan %pK: started\n", &chan->vchan); in stm32_dma_start_transfer()
626 id = chan->id; in stm32_dma_configure_next_sg()
629 sg_req = &chan->desc->sg_req[chan->next_sg]; in stm32_dma_configure_next_sg()
632 dma_sm0ar = sg_req->chan_reg.dma_sm0ar; in stm32_dma_configure_next_sg()
637 dma_sm1ar = sg_req->chan_reg.dma_sm1ar; in stm32_dma_configure_next_sg()
653 dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id)); in stm32_dma_handle_chan_paused()
659 if (chan->desc && chan->desc->cyclic) { in stm32_dma_handle_chan_paused()
660 if (chan->desc->num_sgs == 1) in stm32_dma_handle_chan_paused()
665 chan->chan_reg.dma_scr = dma_scr; in stm32_dma_handle_chan_paused()
671 if (chan->desc && chan->desc->cyclic) { in stm32_dma_handle_chan_paused()
673 stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), dma_scr); in stm32_dma_handle_chan_paused()
676 chan->chan_reg.dma_sndtr = stm32_dma_read(dmadev, STM32_DMA_SNDTR(chan->id)); in stm32_dma_handle_chan_paused()
678 chan->status = DMA_PAUSED; in stm32_dma_handle_chan_paused()
680 dev_dbg(chan2dev(chan), "vchan %pK: paused\n", &chan->vchan); in stm32_dma_handle_chan_paused()
689 id = chan->id; in stm32_dma_post_resume_reconfigure()
697 if (!chan->next_sg) in stm32_dma_post_resume_reconfigure()
698 sg_req = &chan->desc->sg_req[chan->desc->num_sgs - 1]; in stm32_dma_post_resume_reconfigure()
700 sg_req = &chan->desc->sg_req[chan->next_sg - 1]; in stm32_dma_post_resume_reconfigure()
703 stm32_dma_write(dmadev, STM32_DMA_SNDTR(chan->id), sg_req->chan_reg.dma_sndtr); in stm32_dma_post_resume_reconfigure()
706 stm32_dma_write(dmadev, STM32_DMA_SPAR(id), sg_req->chan_reg.dma_spar); in stm32_dma_post_resume_reconfigure()
709 stm32_dma_write(dmadev, STM32_DMA_SM0AR(id), sg_req->chan_reg.dma_sm0ar); in stm32_dma_post_resume_reconfigure()
710 stm32_dma_write(dmadev, STM32_DMA_SM1AR(id), sg_req->chan_reg.dma_sm1ar); in stm32_dma_post_resume_reconfigure()
713 if (chan->chan_reg.dma_scr & STM32_DMA_SCR_DBM) { in stm32_dma_post_resume_reconfigure()
716 if (chan->chan_reg.dma_scr & STM32_DMA_SCR_CT) in stm32_dma_post_resume_reconfigure()
720 } else if (chan->chan_reg.dma_scr & STM32_DMA_SCR_CIRC) { in stm32_dma_post_resume_reconfigure()
723 stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), dma_scr); in stm32_dma_post_resume_reconfigure()
730 stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), dma_scr); in stm32_dma_post_resume_reconfigure()
732 dev_dbg(chan2dev(chan), "vchan %pK: reconfigured after pause/resume\n", &chan->vchan); in stm32_dma_post_resume_reconfigure()
737 if (!chan->desc) in stm32_dma_handle_chan_done()
740 if (chan->desc->cyclic) { in stm32_dma_handle_chan_done()
741 vchan_cyclic_callback(&chan->desc->vdesc); in stm32_dma_handle_chan_done()
742 if (chan->trig_mdma) in stm32_dma_handle_chan_done()
751 chan->busy = false; in stm32_dma_handle_chan_done()
752 chan->status = DMA_COMPLETE; in stm32_dma_handle_chan_done()
753 if (chan->next_sg == chan->desc->num_sgs) { in stm32_dma_handle_chan_done()
754 vchan_cookie_complete(&chan->desc->vdesc); in stm32_dma_handle_chan_done()
755 chan->desc = NULL; in stm32_dma_handle_chan_done()
767 spin_lock(&chan->vchan.lock); in stm32_dma_chan_irq()
770 scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id)); in stm32_dma_chan_irq()
771 sfcr = stm32_dma_read(dmadev, STM32_DMA_SFCR(chan->id)); in stm32_dma_chan_irq()
794 if (chan->status != DMA_PAUSED) in stm32_dma_chan_irq()
812 spin_unlock(&chan->vchan.lock); in stm32_dma_chan_irq()
822 spin_lock_irqsave(&chan->vchan.lock, flags); in stm32_dma_issue_pending()
823 if (vchan_issue_pending(&chan->vchan) && !chan->desc && !chan->busy) { in stm32_dma_issue_pending()
824 dev_dbg(chan2dev(chan), "vchan %pK: issued\n", &chan->vchan); in stm32_dma_issue_pending()
828 spin_unlock_irqrestore(&chan->vchan.lock, flags); in stm32_dma_issue_pending()
837 if (chan->status != DMA_IN_PROGRESS) in stm32_dma_pause()
838 return -EPERM; in stm32_dma_pause()
840 spin_lock_irqsave(&chan->vchan.lock, flags); in stm32_dma_pause()
846 spin_unlock_irqrestore(&chan->vchan.lock, flags); in stm32_dma_pause()
855 struct stm32_dma_chan_reg chan_reg = chan->chan_reg; in stm32_dma_resume()
856 u32 id = chan->id, scr, ndtr, offset, spar, sm0ar, sm1ar; in stm32_dma_resume()
860 if (chan->status != DMA_PAUSED) in stm32_dma_resume()
861 return -EPERM; in stm32_dma_resume()
865 return -EPERM; in stm32_dma_resume()
867 spin_lock_irqsave(&chan->vchan.lock, flags); in stm32_dma_resume()
870 if (!chan->next_sg) in stm32_dma_resume()
871 sg_req = &chan->desc->sg_req[chan->desc->num_sgs - 1]; in stm32_dma_resume()
873 sg_req = &chan->desc->sg_req[chan->next_sg - 1]; in stm32_dma_resume()
875 ndtr = sg_req->chan_reg.dma_sndtr; in stm32_dma_resume()
876 offset = (ndtr - chan_reg.dma_sndtr); in stm32_dma_resume()
878 spar = sg_req->chan_reg.dma_spar; in stm32_dma_resume()
879 sm0ar = sg_req->chan_reg.dma_sm0ar; in stm32_dma_resume()
880 sm1ar = sg_req->chan_reg.dma_sm1ar; in stm32_dma_resume()
919 /* The stream may then be re-enabled to restart transfer from the point it was stopped */ in stm32_dma_resume()
920 chan->status = DMA_IN_PROGRESS; in stm32_dma_resume()
924 spin_unlock_irqrestore(&chan->vchan.lock, flags); in stm32_dma_resume()
926 dev_dbg(chan2dev(chan), "vchan %pK: resumed\n", &chan->vchan); in stm32_dma_resume()
942 src_addr_width = chan->dma_sconfig.src_addr_width; in stm32_dma_set_xfer_param()
943 dst_addr_width = chan->dma_sconfig.dst_addr_width; in stm32_dma_set_xfer_param()
944 src_maxburst = chan->dma_sconfig.src_maxburst; in stm32_dma_set_xfer_param()
945 dst_maxburst = chan->dma_sconfig.dst_maxburst; in stm32_dma_set_xfer_param()
946 fifoth = chan->threshold; in stm32_dma_set_xfer_param()
968 chan->mem_width = src_addr_width; in stm32_dma_set_xfer_param()
974 * Set memory burst size - burst not possible if address is not aligned on in stm32_dma_set_xfer_param()
977 if (buf_addr & (buf_len - 1)) in stm32_dma_set_xfer_param()
996 chan->chan_reg.dma_sfcr &= ~STM32_DMA_SFCR_FTH_MASK; in stm32_dma_set_xfer_param()
998 chan->chan_reg.dma_sfcr |= FIELD_PREP(STM32_DMA_SFCR_FTH_MASK, fifoth); in stm32_dma_set_xfer_param()
1001 chan->chan_reg.dma_spar = chan->dma_sconfig.dst_addr; in stm32_dma_set_xfer_param()
1016 chan->mem_burst = src_best_burst; in stm32_dma_set_xfer_param()
1024 chan->mem_width = dst_addr_width; in stm32_dma_set_xfer_param()
1030 * Set memory burst size - burst not possible if address is not aligned on in stm32_dma_set_xfer_param()
1033 if (buf_addr & (buf_len - 1)) in stm32_dma_set_xfer_param()
1041 chan->mem_burst = dst_best_burst; in stm32_dma_set_xfer_param()
1053 chan->chan_reg.dma_sfcr &= ~STM32_DMA_SFCR_FTH_MASK; in stm32_dma_set_xfer_param()
1055 chan->chan_reg.dma_sfcr |= FIELD_PREP(STM32_DMA_SFCR_FTH_MASK, fifoth); in stm32_dma_set_xfer_param()
1058 chan->chan_reg.dma_spar = chan->dma_sconfig.src_addr; in stm32_dma_set_xfer_param()
1059 *buswidth = chan->dma_sconfig.src_addr_width; in stm32_dma_set_xfer_param()
1064 return -EINVAL; in stm32_dma_set_xfer_param()
1070 chan->chan_reg.dma_scr &= ~(STM32_DMA_SCR_DIR_MASK | in stm32_dma_set_xfer_param()
1073 chan->chan_reg.dma_scr |= dma_scr; in stm32_dma_set_xfer_param()
1095 if (!chan->config_init) { in stm32_dma_prep_slave_sg()
1110 if (chan->dma_sconfig.device_fc) in stm32_dma_prep_slave_sg()
1111 chan->chan_reg.dma_scr |= STM32_DMA_SCR_PFCTRL; in stm32_dma_prep_slave_sg()
1113 chan->chan_reg.dma_scr &= ~STM32_DMA_SCR_PFCTRL; in stm32_dma_prep_slave_sg()
1115 /* Activate Double Buffer Mode if DMA triggers STM32 MDMA and more than 1 sg */ in stm32_dma_prep_slave_sg()
1116 if (chan->trig_mdma && sg_len > 1) { in stm32_dma_prep_slave_sg()
1117 chan->chan_reg.dma_scr |= STM32_DMA_SCR_DBM; in stm32_dma_prep_slave_sg()
1118 chan->chan_reg.dma_scr &= ~STM32_DMA_SCR_CT; in stm32_dma_prep_slave_sg()
1128 desc->sg_req[i].len = sg_dma_len(sg); in stm32_dma_prep_slave_sg()
1130 nb_data_items = desc->sg_req[i].len / buswidth; in stm32_dma_prep_slave_sg()
1136 stm32_dma_clear_reg(&desc->sg_req[i].chan_reg); in stm32_dma_prep_slave_sg()
1137 desc->sg_req[i].chan_reg.dma_scr = chan->chan_reg.dma_scr; in stm32_dma_prep_slave_sg()
1138 desc->sg_req[i].chan_reg.dma_sfcr = chan->chan_reg.dma_sfcr; in stm32_dma_prep_slave_sg()
1139 desc->sg_req[i].chan_reg.dma_spar = chan->chan_reg.dma_spar; in stm32_dma_prep_slave_sg()
1140 desc->sg_req[i].chan_reg.dma_sm0ar = sg_dma_address(sg); in stm32_dma_prep_slave_sg()
1141 desc->sg_req[i].chan_reg.dma_sm1ar = sg_dma_address(sg); in stm32_dma_prep_slave_sg()
1142 if (chan->trig_mdma) in stm32_dma_prep_slave_sg()
1143 desc->sg_req[i].chan_reg.dma_sm1ar += sg_dma_len(sg); in stm32_dma_prep_slave_sg()
1144 desc->sg_req[i].chan_reg.dma_sndtr = nb_data_items; in stm32_dma_prep_slave_sg()
1147 desc->num_sgs = sg_len; in stm32_dma_prep_slave_sg()
1148 desc->cyclic = false; in stm32_dma_prep_slave_sg()
1150 return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags); in stm32_dma_prep_slave_sg()
1173 if (!chan->config_init) { in stm32_dma_prep_dma_cyclic()
1189 if (chan->busy) { in stm32_dma_prep_dma_cyclic()
1207 chan->chan_reg.dma_scr |= STM32_DMA_SCR_CIRC; in stm32_dma_prep_dma_cyclic()
1209 chan->chan_reg.dma_scr |= STM32_DMA_SCR_DBM; in stm32_dma_prep_dma_cyclic()
1210 chan->chan_reg.dma_scr &= ~STM32_DMA_SCR_CT; in stm32_dma_prep_dma_cyclic()
1214 chan->chan_reg.dma_scr &= ~STM32_DMA_SCR_PFCTRL; in stm32_dma_prep_dma_cyclic()
1223 desc->sg_req[i].len = period_len; in stm32_dma_prep_dma_cyclic()
1225 stm32_dma_clear_reg(&desc->sg_req[i].chan_reg); in stm32_dma_prep_dma_cyclic()
1226 desc->sg_req[i].chan_reg.dma_scr = chan->chan_reg.dma_scr; in stm32_dma_prep_dma_cyclic()
1227 desc->sg_req[i].chan_reg.dma_sfcr = chan->chan_reg.dma_sfcr; in stm32_dma_prep_dma_cyclic()
1228 desc->sg_req[i].chan_reg.dma_spar = chan->chan_reg.dma_spar; in stm32_dma_prep_dma_cyclic()
1229 desc->sg_req[i].chan_reg.dma_sm0ar = buf_addr; in stm32_dma_prep_dma_cyclic()
1230 desc->sg_req[i].chan_reg.dma_sm1ar = buf_addr; in stm32_dma_prep_dma_cyclic()
1231 if (chan->trig_mdma) in stm32_dma_prep_dma_cyclic()
1232 desc->sg_req[i].chan_reg.dma_sm1ar += period_len; in stm32_dma_prep_dma_cyclic()
1233 desc->sg_req[i].chan_reg.dma_sndtr = nb_data_items; in stm32_dma_prep_dma_cyclic()
1234 if (!chan->trig_mdma) in stm32_dma_prep_dma_cyclic()
1238 desc->num_sgs = num_periods; in stm32_dma_prep_dma_cyclic()
1239 desc->cyclic = true; in stm32_dma_prep_dma_cyclic()
1241 return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags); in stm32_dma_prep_dma_cyclic()
1260 threshold = chan->threshold; in stm32_dma_prep_dma_memcpy()
1263 xfer_count = min_t(size_t, len - offset, in stm32_dma_prep_dma_memcpy()
1276 stm32_dma_clear_reg(&desc->sg_req[i].chan_reg); in stm32_dma_prep_dma_memcpy()
1277 desc->sg_req[i].chan_reg.dma_scr = in stm32_dma_prep_dma_memcpy()
1285 desc->sg_req[i].chan_reg.dma_sfcr |= STM32_DMA_SFCR_MASK; in stm32_dma_prep_dma_memcpy()
1286 desc->sg_req[i].chan_reg.dma_sfcr |= FIELD_PREP(STM32_DMA_SFCR_FTH_MASK, threshold); in stm32_dma_prep_dma_memcpy()
1287 desc->sg_req[i].chan_reg.dma_spar = src + offset; in stm32_dma_prep_dma_memcpy()
1288 desc->sg_req[i].chan_reg.dma_sm0ar = dest + offset; in stm32_dma_prep_dma_memcpy()
1289 desc->sg_req[i].chan_reg.dma_sndtr = xfer_count; in stm32_dma_prep_dma_memcpy()
1290 desc->sg_req[i].len = xfer_count; in stm32_dma_prep_dma_memcpy()
1293 desc->num_sgs = num_sgs; in stm32_dma_prep_dma_memcpy()
1294 desc->cyclic = false; in stm32_dma_prep_dma_memcpy()
1296 return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags); in stm32_dma_prep_dma_memcpy()
1304 dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id)); in stm32_dma_get_remaining_bytes()
1306 ndtr = stm32_dma_read(dmadev, STM32_DMA_SNDTR(chan->id)); in stm32_dma_get_remaining_bytes()
1312 * stm32_dma_is_current_sg - check that expected sg_req is currently transferred
1329 id = chan->id; in stm32_dma_is_current_sg()
1336 sg_req = &chan->desc->sg_req[chan->next_sg]; in stm32_dma_is_current_sg()
1337 period_len = sg_req->len; in stm32_dma_is_current_sg()
1339 /* DBM - take care of a previous pause/resume not yet post reconfigured */ in stm32_dma_is_current_sg()
1346 return (dma_smar >= sg_req->chan_reg.dma_sm0ar && in stm32_dma_is_current_sg()
1347 dma_smar < sg_req->chan_reg.dma_sm0ar + period_len); in stm32_dma_is_current_sg()
1355 return (dma_smar >= sg_req->chan_reg.dma_sm1ar && in stm32_dma_is_current_sg()
1356 dma_smar < sg_req->chan_reg.dma_sm1ar + period_len); in stm32_dma_is_current_sg()
1366 struct stm32_dma_sg_req *sg_req = &chan->desc->sg_req[chan->next_sg]; in stm32_dma_desc_residue()
1372 * - the sg_req currently transferred in stm32_dma_desc_residue()
1373 * - the Hardware remaining position in this sg (NDTR bits field). in stm32_dma_desc_residue()
1382 * The strategy implemented in the stm32 driver is to: in stm32_dma_desc_residue()
1383 * - read the SxNDTR register in stm32_dma_desc_residue()
1384 * - crosscheck that hardware is still in current transfer. in stm32_dma_desc_residue()
1396 if ((chan->desc->cyclic || chan->trig_mdma) && !stm32_dma_is_current_sg(chan)) { in stm32_dma_desc_residue()
1398 if (n_sg == chan->desc->num_sgs) in stm32_dma_desc_residue()
1400 if (!chan->trig_mdma) in stm32_dma_desc_residue()
1401 residue = sg_req->len; in stm32_dma_desc_residue()
1411 if ((!chan->desc->cyclic && !chan->trig_mdma) || n_sg != 0) in stm32_dma_desc_residue()
1412 for (i = n_sg; i < desc->num_sgs; i++) in stm32_dma_desc_residue()
1413 residue += desc->sg_req[i].len; in stm32_dma_desc_residue()
1415 if (!chan->mem_burst) in stm32_dma_desc_residue()
1418 burst_size = chan->mem_burst * chan->mem_width; in stm32_dma_desc_residue()
1421 residue = residue - modulo + burst_size; in stm32_dma_desc_residue()
1440 status = chan->status; in stm32_dma_tx_status()
1445 spin_lock_irqsave(&chan->vchan.lock, flags); in stm32_dma_tx_status()
1446 vdesc = vchan_find_desc(&chan->vchan, cookie); in stm32_dma_tx_status()
1447 if (chan->desc && cookie == chan->desc->vdesc.tx.cookie) in stm32_dma_tx_status()
1448 residue = stm32_dma_desc_residue(chan, chan->desc, in stm32_dma_tx_status()
1449 chan->next_sg); in stm32_dma_tx_status()
1455 spin_unlock_irqrestore(&chan->vchan.lock, flags); in stm32_dma_tx_status()
1466 chan->config_init = false; in stm32_dma_alloc_chan_resources()
1468 ret = pm_runtime_resume_and_get(dmadev->ddev.dev); in stm32_dma_alloc_chan_resources()
1474 pm_runtime_put(dmadev->ddev.dev); in stm32_dma_alloc_chan_resources()
1485 dev_dbg(chan2dev(chan), "Freeing channel %d\n", chan->id); in stm32_dma_free_chan_resources()
1487 if (chan->busy) { in stm32_dma_free_chan_resources()
1488 spin_lock_irqsave(&chan->vchan.lock, flags); in stm32_dma_free_chan_resources()
1490 chan->desc = NULL; in stm32_dma_free_chan_resources()
1491 spin_unlock_irqrestore(&chan->vchan.lock, flags); in stm32_dma_free_chan_resources()
1494 pm_runtime_put(dmadev->ddev.dev); in stm32_dma_free_chan_resources()
1497 stm32_dma_clear_reg(&chan->chan_reg); in stm32_dma_free_chan_resources()
1498 chan->threshold = 0; in stm32_dma_free_chan_resources()
1509 stm32_dma_clear_reg(&chan->chan_reg); in stm32_dma_set_config()
1511 chan->chan_reg.dma_scr = cfg->stream_config & STM32_DMA_SCR_CFG_MASK; in stm32_dma_set_config()
1512 chan->chan_reg.dma_scr |= FIELD_PREP(STM32_DMA_SCR_REQ_MASK, cfg->request_line); in stm32_dma_set_config()
1515 chan->chan_reg.dma_scr |= STM32_DMA_SCR_TEIE | STM32_DMA_SCR_TCIE; in stm32_dma_set_config()
1517 chan->threshold = FIELD_GET(STM32_DMA_THRESHOLD_FTR_MASK, cfg->features); in stm32_dma_set_config()
1518 if (FIELD_GET(STM32_DMA_DIRECT_MODE_MASK, cfg->features)) in stm32_dma_set_config()
1519 chan->threshold = STM32_DMA_FIFO_THRESHOLD_NONE; in stm32_dma_set_config()
1520 if (FIELD_GET(STM32_DMA_ALT_ACK_MODE_MASK, cfg->features)) in stm32_dma_set_config()
1521 chan->chan_reg.dma_scr |= STM32_DMA_SCR_TRBUFF; in stm32_dma_set_config()
1522 chan->mdma_config.stream_id = FIELD_GET(STM32_DMA_MDMA_STREAM_ID_MASK, cfg->features); in stm32_dma_set_config()
1528 struct stm32_dma_device *dmadev = ofdma->of_dma_data; in stm32_dma_of_xlate()
1529 struct device *dev = dmadev->ddev.dev; in stm32_dma_of_xlate()
1534 if (dma_spec->args_count < 4) { in stm32_dma_of_xlate()
1539 cfg.channel_id = dma_spec->args[0]; in stm32_dma_of_xlate()
1540 cfg.request_line = dma_spec->args[1]; in stm32_dma_of_xlate()
1541 cfg.stream_config = dma_spec->args[2]; in stm32_dma_of_xlate()
1542 cfg.features = dma_spec->args[3]; in stm32_dma_of_xlate()
1550 chan = &dmadev->chan[cfg.channel_id]; in stm32_dma_of_xlate()
1552 c = dma_get_slave_channel(&chan->vchan.chan); in stm32_dma_of_xlate()
1564 { .compatible = "st,stm32-dma", },
1579 match = of_match_device(stm32_dma_of_match, &pdev->dev); in stm32_dma_probe()
1581 dev_err(&pdev->dev, "Error: No device match found\n"); in stm32_dma_probe()
1582 return -ENODEV; in stm32_dma_probe()
1585 dmadev = devm_kzalloc(&pdev->dev, sizeof(*dmadev), GFP_KERNEL); in stm32_dma_probe()
1587 return -ENOMEM; in stm32_dma_probe()
1589 dd = &dmadev->ddev; in stm32_dma_probe()
1591 dmadev->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); in stm32_dma_probe()
1592 if (IS_ERR(dmadev->base)) in stm32_dma_probe()
1593 return PTR_ERR(dmadev->base); in stm32_dma_probe()
1595 dmadev->clk = devm_clk_get(&pdev->dev, NULL); in stm32_dma_probe()
1596 if (IS_ERR(dmadev->clk)) in stm32_dma_probe()
1597 return dev_err_probe(&pdev->dev, PTR_ERR(dmadev->clk), "Can't get clock\n"); in stm32_dma_probe()
1599 ret = clk_prepare_enable(dmadev->clk); in stm32_dma_probe()
1601 dev_err(&pdev->dev, "clk_prep_enable error: %d\n", ret); in stm32_dma_probe()
1605 dmadev->mem2mem = of_property_read_bool(pdev->dev.of_node, in stm32_dma_probe()
1608 rst = devm_reset_control_get(&pdev->dev, NULL); in stm32_dma_probe()
1611 if (ret == -EPROBE_DEFER) in stm32_dma_probe()
1619 dma_set_max_seg_size(&pdev->dev, STM32_DMA_ALIGNED_MAX_DATA_ITEMS); in stm32_dma_probe()
1621 dma_cap_set(DMA_SLAVE, dd->cap_mask); in stm32_dma_probe()
1622 dma_cap_set(DMA_PRIVATE, dd->cap_mask); in stm32_dma_probe()
1623 dma_cap_set(DMA_CYCLIC, dd->cap_mask); in stm32_dma_probe()
1624 dd->device_alloc_chan_resources = stm32_dma_alloc_chan_resources; in stm32_dma_probe()
1625 dd->device_free_chan_resources = stm32_dma_free_chan_resources; in stm32_dma_probe()
1626 dd->device_tx_status = stm32_dma_tx_status; in stm32_dma_probe()
1627 dd->device_issue_pending = stm32_dma_issue_pending; in stm32_dma_probe()
1628 dd->device_prep_slave_sg = stm32_dma_prep_slave_sg; in stm32_dma_probe()
1629 dd->device_prep_dma_cyclic = stm32_dma_prep_dma_cyclic; in stm32_dma_probe()
1630 dd->device_config = stm32_dma_slave_config; in stm32_dma_probe()
1631 dd->device_pause = stm32_dma_pause; in stm32_dma_probe()
1632 dd->device_resume = stm32_dma_resume; in stm32_dma_probe()
1633 dd->device_terminate_all = stm32_dma_terminate_all; in stm32_dma_probe()
1634 dd->device_synchronize = stm32_dma_synchronize; in stm32_dma_probe()
1635 dd->src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | in stm32_dma_probe()
1638 dd->dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | in stm32_dma_probe()
1641 dd->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); in stm32_dma_probe()
1642 dd->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; in stm32_dma_probe()
1643 dd->copy_align = DMAENGINE_ALIGN_32_BYTES; in stm32_dma_probe()
1644 dd->max_burst = STM32_DMA_MAX_BURST; in stm32_dma_probe()
1645 dd->max_sg_burst = STM32_DMA_ALIGNED_MAX_DATA_ITEMS; in stm32_dma_probe()
1646 dd->descriptor_reuse = true; in stm32_dma_probe()
1647 dd->dev = &pdev->dev; in stm32_dma_probe()
1648 INIT_LIST_HEAD(&dd->channels); in stm32_dma_probe()
1650 if (dmadev->mem2mem) { in stm32_dma_probe()
1651 dma_cap_set(DMA_MEMCPY, dd->cap_mask); in stm32_dma_probe()
1652 dd->device_prep_dma_memcpy = stm32_dma_prep_dma_memcpy; in stm32_dma_probe()
1653 dd->directions |= BIT(DMA_MEM_TO_MEM); in stm32_dma_probe()
1657 chan = &dmadev->chan[i]; in stm32_dma_probe()
1658 chan->id = i; in stm32_dma_probe()
1659 chan->vchan.desc_free = stm32_dma_desc_free; in stm32_dma_probe()
1660 vchan_init(&chan->vchan, dd); in stm32_dma_probe()
1662 chan->mdma_config.ifcr = res->start; in stm32_dma_probe()
1663 chan->mdma_config.ifcr += STM32_DMA_IFCR(chan->id); in stm32_dma_probe()
1665 chan->mdma_config.tcf = STM32_DMA_TCI; in stm32_dma_probe()
1666 chan->mdma_config.tcf <<= STM32_DMA_FLAGS_SHIFT(chan->id); in stm32_dma_probe()
1674 chan = &dmadev->chan[i]; in stm32_dma_probe()
1678 chan->irq = ret; in stm32_dma_probe()
1680 ret = devm_request_irq(&pdev->dev, chan->irq, in stm32_dma_probe()
1684 dev_err(&pdev->dev, in stm32_dma_probe()
1691 ret = of_dma_controller_register(pdev->dev.of_node, in stm32_dma_probe()
1694 dev_err(&pdev->dev, in stm32_dma_probe()
1695 "STM32 DMA DMA OF registration failed %d\n", ret); in stm32_dma_probe()
1701 pm_runtime_set_active(&pdev->dev); in stm32_dma_probe()
1702 pm_runtime_enable(&pdev->dev); in stm32_dma_probe()
1703 pm_runtime_get_noresume(&pdev->dev); in stm32_dma_probe()
1704 pm_runtime_put(&pdev->dev); in stm32_dma_probe()
1706 dev_info(&pdev->dev, "STM32 DMA driver registered\n"); in stm32_dma_probe()
1713 clk_disable_unprepare(dmadev->clk); in stm32_dma_probe()
1723 clk_disable_unprepare(dmadev->clk); in stm32_dma_runtime_suspend()
1733 ret = clk_prepare_enable(dmadev->clk); in stm32_dma_runtime_resume()
1757 return -EBUSY; in stm32_dma_pm_suspend()
1782 .name = "stm32-dma",