11 static u8 xec_mask	 = 0xf;
72 	"PFB valid bit parity error",			/* xec = 0xd */
73 	"Microcode Patch Buffer",			/* xec = 010 */
82 	"Fill ECC error on data fills",			/* xec = 0x4 */
91 	"L2 Tag ECC error",				/* xec = 0x10 */
114 	"L3 data cache ECC error",			/* xec = 0x1c */
157 	"System Read Data Error Thread 0",
207 	"BPQ Thread 0 Snoop Parity Error",
352 	"Instruction Cache Bank 0 ECC or parity error",
354 	"Instruction Tag Ram 0 parity error",
356 	"Data Cache Bank 0 ECC or parity error",
360 	"Data Tag Bank 0 parity error",
365 	"TLB Bank 0 parity error",
403 	"Main SRAM [31:0] bank ECC or parity error",
436 	"MPDMA TVF SDP Slave Memory 0 ECC or parity error",
439 	"MPDMA TVF SDP Master Memory 0 ECC or parity error",
526 	"Parity error for port 0",
622 static bool f12h_mc0_mce(u16 ec, u8 xec)  in f12h_mc0_mce()  argument
640 static bool f10h_mc0_mce(u16 ec, u8 xec)  in f10h_mc0_mce()  argument
646 	return f12h_mc0_mce(ec, xec);  in f10h_mc0_mce()
649 static bool k8_mc0_mce(u16 ec, u8 xec)  in k8_mc0_mce()  argument
656 	return f10h_mc0_mce(ec, xec);  in k8_mc0_mce()
659 static bool cat_mc0_mce(u16 ec, u8 xec)  in cat_mc0_mce()  argument
711 static bool f15h_mc0_mce(u16 ec, u8 xec)  in f15h_mc0_mce()  argument
717 		switch (xec) {  in f15h_mc0_mce()
718 		case 0x0:  in f15h_mc0_mce()
722 		case 0x1:  in f15h_mc0_mce()
726 		case 0x2:  in f15h_mc0_mce()
727 		case 0x11:  in f15h_mc0_mce()
731 		case 0x3:  in f15h_mc0_mce()
735 		case 0x10:  in f15h_mc0_mce()
739 		case 0x12:  in f15h_mc0_mce()
748 		if (!xec)  in f15h_mc0_mce()
751 			pr_cont(" Internal error condition type %d.\n", xec);  in f15h_mc0_mce()
753 		if (xec <= 0x1f)  in f15h_mc0_mce()
767 	u8 xec = XEC(m->status, xec_mask);  in decode_mc0_mce()  local
775 				((xec == 2) ? "locked miss"  in decode_mc0_mce()
776 					    : (xec ? "multimatch" : "parity")));  in decode_mc0_mce()
779 	} else if (fam_ops.mc0_mce(ec, xec))  in decode_mc0_mce()
785 static bool k8_mc1_mce(u16 ec, u8 xec)  in k8_mc1_mce()  argument
793 	if (ll == 0x2)  in k8_mc1_mce()
795 	else if (ll == 0x1) {  in k8_mc1_mce()
819 static bool cat_mc1_mce(u16 ec, u8 xec)  in cat_mc1_mce()  argument
834 	else if (xec == 0x0)  in cat_mc1_mce()
836 	else if (xec == 0x2)  in cat_mc1_mce()
844 static bool f15h_mc1_mce(u16 ec, u8 xec)  in f15h_mc1_mce()  argument
851 	switch (xec) {  in f15h_mc1_mce()
852 	case 0x0 ... 0xa:  in f15h_mc1_mce()
853 		pr_cont("%s.\n", f15h_mc1_mce_desc[xec]);  in f15h_mc1_mce()
856 	case 0xd:  in f15h_mc1_mce()
857 		pr_cont("%s.\n", f15h_mc1_mce_desc[xec-2]);  in f15h_mc1_mce()
860 	case 0x10:  in f15h_mc1_mce()
861 		pr_cont("%s.\n", f15h_mc1_mce_desc[xec-4]);  in f15h_mc1_mce()
864 	case 0x11 ... 0x15:  in f15h_mc1_mce()
865 		pr_cont("Decoder %s parity error.\n", f15h_mc1_mce_desc[xec-4]);  in f15h_mc1_mce()
877 	u8 xec = XEC(m->status, xec_mask);  in decode_mc1_mce()  local
883 			(xec ? "multimatch" : "parity error"));  in decode_mc1_mce()
885 		bool k8 = (boot_cpu_data.x86 == 0xf && (m->status & BIT_64(58)));  in decode_mc1_mce()
889 		if (xec <= 0x3f)  in decode_mc1_mce()
893 	} else if (fam_ops.mc1_mce(ec, xec))  in decode_mc1_mce()
904 static bool k8_mc2_mce(u16 ec, u8 xec)  in k8_mc2_mce()  argument
908 	if (xec == 0x1)  in k8_mc2_mce()
910 	else if (xec == 0x3)  in k8_mc2_mce()
912 	else if (xec == 0x2 && MEM_ERROR(ec))  in k8_mc2_mce()
914 	else if (xec == 0x0) {  in k8_mc2_mce()
924 			if (r4 >= 0x7)  in k8_mc2_mce()
927 			else if (r4 <= 0x1)  in k8_mc2_mce()
940 static bool f15h_mc2_mce(u16 ec, u8 xec)  in f15h_mc2_mce()  argument
945 		if (xec == 0x0)  in f15h_mc2_mce()
947 		else if (xec == 0x1)  in f15h_mc2_mce()
952 		if (xec > 2)  in f15h_mc2_mce()
957 		switch (xec) {  in f15h_mc2_mce()
958 		case 0x4 ... 0xc:  in f15h_mc2_mce()
959 			pr_cont("%s.\n", f15h_mc2_mce_desc[xec - 0x4]);  in f15h_mc2_mce()
962 		case 0x10 ... 0x14:  in f15h_mc2_mce()
963 			pr_cont("%s.\n", f15h_mc2_mce_desc[xec - 0x7]);  in f15h_mc2_mce()
970 		if (xec <= 0x3f)  in f15h_mc2_mce()
979 static bool f16h_mc2_mce(u16 ec, u8 xec)  in f16h_mc2_mce()  argument
986 	switch (xec) {  in f16h_mc2_mce()
987 	case 0x04 ... 0x05:  in f16h_mc2_mce()
991 	case 0x09 ... 0x0b:  in f16h_mc2_mce()
992 	case 0x0d ... 0x0f:  in f16h_mc2_mce()
998 	case 0x10 ... 0x19:  in f16h_mc2_mce()
999 	case 0x1b:  in f16h_mc2_mce()
1001 			(((r4 == R4_RD) && !(xec & 0x3)) ? "Hit"  :  in f16h_mc2_mce()
1006 	case 0x1c ... 0x1d:  in f16h_mc2_mce()
1007 	case 0x1f:  in f16h_mc2_mce()
1023 	u8 xec = XEC(m->status, xec_mask);  in decode_mc2_mce()  local
1027 	if (!fam_ops.mc2_mce(ec, xec))  in decode_mc2_mce()
1034 	u8 xec = XEC(m->status, xec_mask);  in decode_mc3_mce()  local
1036 	if (boot_cpu_data.x86 >= 0x14) {  in decode_mc3_mce()
1044 	if (xec == 0x0) {  in decode_mc3_mce()
1065 	u8 xec = XEC(m->status, 0x1f);  in decode_mc4_mce()  local
1066 	u8 offset = 0;  in decode_mc4_mce()
1070 	switch (xec) {  in decode_mc4_mce()
1071 	case 0x0 ... 0xe:  in decode_mc4_mce()
1074 		if (xec == 0x0 || xec == 0x8) {  in decode_mc4_mce()
1076 			if (fam == 0x11)  in decode_mc4_mce()
1079 			pr_cont("%s.\n", mc4_mce_desc[xec]);  in decode_mc4_mce()
1087 	case 0xf:  in decode_mc4_mce()
1096 	case 0x19:  in decode_mc4_mce()
1097 		if (fam == 0x15 || fam == 0x16)  in decode_mc4_mce()
1103 	case 0x1c ... 0x1f:  in decode_mc4_mce()
1111 	pr_cont("%s.\n", mc4_mce_desc[xec - offset]);  in decode_mc4_mce()
1122 	u8 xec = XEC(m->status, xec_mask);  in decode_mc5_mce()  local
1124 	if (fam == 0xf || fam == 0x11)  in decode_mc5_mce()
1130 		if (xec <= 0x1f) {  in decode_mc5_mce()
1137 	if (xec == 0x0 || xec == 0xc)  in decode_mc5_mce()
1138 		pr_cont("%s.\n", mc5_mce_desc[xec]);  in decode_mc5_mce()
1139 	else if (xec <= 0xd)  in decode_mc5_mce()
1140 		pr_cont("%s parity error.\n", mc5_mce_desc[xec]);  in decode_mc5_mce()
1152 	u8 xec = XEC(m->status, xec_mask);  in decode_mc6_mce()  local
1156 	if (xec > 0x5)  in decode_mc6_mce()
1159 	pr_cont("%s parity error.\n", mc6_mce_desc[xec]);  in decode_mc6_mce()
1171 	u8 xec = XEC(m->status, xec_mask);  in decode_smca_error()  local
1183 	pr_emerg(HW_ERR "%s Ext. Error Code: %d", ip_name, xec);  in decode_smca_error()
1186 	if (xec < smca_mce_descs[bank_type].num_descs)  in decode_smca_error()
1187 		pr_cont(", %s.\n", smca_mce_descs[bank_type].descs[xec]);  in decode_smca_error()
1190 	    xec == 0 && decode_dram_ecc)  in decode_smca_error()
1269 	ecc = (m->status >> 45) & 0x3;  in amd_decode_mce()
1273 	if (fam >= 0x15) {  in amd_decode_mce()
1277 		if (fam != 0x15 || m->bank != 4)  in amd_decode_mce()
1281 	if (fam >= 0x17)  in amd_decode_mce()
1284 	pr_cont("]: 0x%016llx\n", m->status);  in amd_decode_mce()
1287 		pr_emerg(HW_ERR "Error Addr: 0x%016llx\n", m->addr);  in amd_decode_mce()
1290 		pr_emerg(HW_ERR "PPIN: 0x%016llx\n", m->ppin);  in amd_decode_mce()
1293 		pr_emerg(HW_ERR "IPID: 0x%016llx", m->ipid);  in amd_decode_mce()
1296 			pr_cont(", Syndrome: 0x%016llx", m->synd);  in amd_decode_mce()
1312 	case 0:  in amd_decode_mce()
1345 	amd_decode_err_code(m->status & 0xffff);  in amd_decode_mce()
1368 		xec_mask = 0x3f;  in mce_amd_init()
1373 	case 0xf:  in mce_amd_init()
1379 	case 0x10:  in mce_amd_init()
1385 	case 0x11:  in mce_amd_init()
1391 	case 0x12:  in mce_amd_init()
1397 	case 0x14:  in mce_amd_init()
1403 	case 0x15:  in mce_amd_init()
1404 		xec_mask = c->x86_model == 0x60 ? 0x3f : 0x1f;  in mce_amd_init()
1411 	case 0x16:  in mce_amd_init()
1412 		xec_mask = 0x1f;  in mce_amd_init()
1418 	case 0x17:  in mce_amd_init()
1419 	case 0x18:  in mce_amd_init()
1424 		printk(KERN_WARNING "Huh? What family is it: 0x%x?!\n", c->x86);  in mce_amd_init()
1433 	return 0;  in mce_amd_init()