Lines Matching full:dsp
3 * cs_dsp.c -- Cirrus Logic DSP firmware support
279 bool (*validate_version)(struct cs_dsp *dsp, unsigned int version);
280 unsigned int (*parse_sizes)(struct cs_dsp *dsp,
284 int (*setup_algs)(struct cs_dsp *dsp);
288 void (*show_fw_status)(struct cs_dsp *dsp);
289 void (*stop_watchdog)(struct cs_dsp *dsp);
291 int (*enable_memory)(struct cs_dsp *dsp);
292 void (*disable_memory)(struct cs_dsp *dsp);
293 int (*lock_memory)(struct cs_dsp *dsp, unsigned int lock_regions);
295 int (*enable_core)(struct cs_dsp *dsp);
296 void (*disable_core)(struct cs_dsp *dsp);
298 int (*start_core)(struct cs_dsp *dsp);
299 void (*stop_core)(struct cs_dsp *dsp);
377 static void cs_dsp_debugfs_save_wmfwname(struct cs_dsp *dsp, const char *s) in cs_dsp_debugfs_save_wmfwname() argument
381 kfree(dsp->wmfw_file_name); in cs_dsp_debugfs_save_wmfwname()
382 dsp->wmfw_file_name = tmp; in cs_dsp_debugfs_save_wmfwname()
385 static void cs_dsp_debugfs_save_binname(struct cs_dsp *dsp, const char *s) in cs_dsp_debugfs_save_binname() argument
389 kfree(dsp->bin_file_name); in cs_dsp_debugfs_save_binname()
390 dsp->bin_file_name = tmp; in cs_dsp_debugfs_save_binname()
393 static void cs_dsp_debugfs_clear(struct cs_dsp *dsp) in cs_dsp_debugfs_clear() argument
395 kfree(dsp->wmfw_file_name); in cs_dsp_debugfs_clear()
396 kfree(dsp->bin_file_name); in cs_dsp_debugfs_clear()
397 dsp->wmfw_file_name = NULL; in cs_dsp_debugfs_clear()
398 dsp->bin_file_name = NULL; in cs_dsp_debugfs_clear()
405 struct cs_dsp *dsp = file->private_data; in cs_dsp_debugfs_wmfw_read() local
408 mutex_lock(&dsp->pwr_lock); in cs_dsp_debugfs_wmfw_read()
410 if (!dsp->wmfw_file_name || !dsp->booted) in cs_dsp_debugfs_wmfw_read()
414 dsp->wmfw_file_name, in cs_dsp_debugfs_wmfw_read()
415 strlen(dsp->wmfw_file_name)); in cs_dsp_debugfs_wmfw_read()
417 mutex_unlock(&dsp->pwr_lock); in cs_dsp_debugfs_wmfw_read()
425 struct cs_dsp *dsp = file->private_data; in cs_dsp_debugfs_bin_read() local
428 mutex_lock(&dsp->pwr_lock); in cs_dsp_debugfs_bin_read()
430 if (!dsp->bin_file_name || !dsp->booted) in cs_dsp_debugfs_bin_read()
434 dsp->bin_file_name, in cs_dsp_debugfs_bin_read()
435 strlen(dsp->bin_file_name)); in cs_dsp_debugfs_bin_read()
437 mutex_unlock(&dsp->pwr_lock); in cs_dsp_debugfs_bin_read()
466 struct cs_dsp *dsp = s->private; in cs_dsp_debugfs_read_controls_show() local
470 list_for_each_entry(ctl, &dsp->ctl_list, list) { in cs_dsp_debugfs_read_controls_show()
489 * cs_dsp_init_debugfs() - Create and populate DSP representation in debugfs
490 * @dsp: pointer to DSP structure
491 * @debugfs_root: pointer to debugfs directory in which to create this DSP
494 void cs_dsp_init_debugfs(struct cs_dsp *dsp, struct dentry *debugfs_root) in cs_dsp_init_debugfs() argument
499 root = debugfs_create_dir(dsp->name, debugfs_root); in cs_dsp_init_debugfs()
501 debugfs_create_bool("booted", 0444, root, &dsp->booted); in cs_dsp_init_debugfs()
502 debugfs_create_bool("running", 0444, root, &dsp->running); in cs_dsp_init_debugfs()
503 debugfs_create_x32("fw_id", 0444, root, &dsp->fw_id); in cs_dsp_init_debugfs()
504 debugfs_create_x32("fw_version", 0444, root, &dsp->fw_id_version); in cs_dsp_init_debugfs()
508 dsp, &cs_dsp_debugfs_fops[i].fops); in cs_dsp_init_debugfs()
510 debugfs_create_file("controls", 0444, root, dsp, in cs_dsp_init_debugfs()
513 dsp->debugfs_root = root; in cs_dsp_init_debugfs()
518 * cs_dsp_cleanup_debugfs() - Removes DSP representation from debugfs
519 * @dsp: pointer to DSP structure
521 void cs_dsp_cleanup_debugfs(struct cs_dsp *dsp) in cs_dsp_cleanup_debugfs() argument
523 cs_dsp_debugfs_clear(dsp); in cs_dsp_cleanup_debugfs()
524 debugfs_remove_recursive(dsp->debugfs_root); in cs_dsp_cleanup_debugfs()
525 dsp->debugfs_root = ERR_PTR(-ENODEV); in cs_dsp_cleanup_debugfs()
529 void cs_dsp_init_debugfs(struct cs_dsp *dsp, struct dentry *debugfs_root) in cs_dsp_init_debugfs() argument
534 void cs_dsp_cleanup_debugfs(struct cs_dsp *dsp) in cs_dsp_cleanup_debugfs() argument
539 static inline void cs_dsp_debugfs_save_wmfwname(struct cs_dsp *dsp, in cs_dsp_debugfs_save_wmfwname() argument
544 static inline void cs_dsp_debugfs_save_binname(struct cs_dsp *dsp, in cs_dsp_debugfs_save_binname() argument
549 static inline void cs_dsp_debugfs_clear(struct cs_dsp *dsp) in cs_dsp_debugfs_clear() argument
554 static const struct cs_dsp_region *cs_dsp_find_region(struct cs_dsp *dsp, in cs_dsp_find_region() argument
559 for (i = 0; i < dsp->num_mems; i++) in cs_dsp_find_region()
560 if (dsp->mem[i].type == type) in cs_dsp_find_region()
561 return &dsp->mem[i]; in cs_dsp_find_region()
601 static void cs_dsp_read_fw_status(struct cs_dsp *dsp, in cs_dsp_read_fw_status() argument
608 ret = regmap_read(dsp->regmap, dsp->base + offs[i], &offs[i]); in cs_dsp_read_fw_status()
610 cs_dsp_err(dsp, "Failed to read SCRATCH%u: %d\n", i, ret); in cs_dsp_read_fw_status()
616 static void cs_dsp_adsp2_show_fw_status(struct cs_dsp *dsp) in cs_dsp_adsp2_show_fw_status() argument
622 cs_dsp_read_fw_status(dsp, ARRAY_SIZE(offs), offs); in cs_dsp_adsp2_show_fw_status()
624 cs_dsp_dbg(dsp, "FW SCRATCH 0:0x%x 1:0x%x 2:0x%x 3:0x%x\n", in cs_dsp_adsp2_show_fw_status()
628 static void cs_dsp_adsp2v2_show_fw_status(struct cs_dsp *dsp) in cs_dsp_adsp2v2_show_fw_status() argument
632 cs_dsp_read_fw_status(dsp, ARRAY_SIZE(offs), offs); in cs_dsp_adsp2v2_show_fw_status()
634 cs_dsp_dbg(dsp, "FW SCRATCH 0:0x%x 1:0x%x 2:0x%x 3:0x%x\n", in cs_dsp_adsp2v2_show_fw_status()
639 static void cs_dsp_halo_show_fw_status(struct cs_dsp *dsp) in cs_dsp_halo_show_fw_status() argument
645 cs_dsp_read_fw_status(dsp, ARRAY_SIZE(offs), offs); in cs_dsp_halo_show_fw_status()
647 cs_dsp_dbg(dsp, "FW SCRATCH 0:0x%x 1:0x%x 2:0x%x 3:0x%x\n", in cs_dsp_halo_show_fw_status()
655 struct cs_dsp *dsp = ctl->dsp; in cs_dsp_coeff_base_reg() local
658 mem = cs_dsp_find_region(dsp, alg_region->type); in cs_dsp_coeff_base_reg()
660 cs_dsp_err(dsp, "No base for region %x\n", in cs_dsp_coeff_base_reg()
665 *reg = dsp->ops->region_to_reg(mem, ctl->alg_region.base + ctl->offset + off); in cs_dsp_coeff_base_reg()
684 struct cs_dsp *dsp = ctl->dsp; in cs_dsp_coeff_write_acked_control() local
689 lockdep_assert_held(&dsp->pwr_lock); in cs_dsp_coeff_write_acked_control()
691 if (!dsp->running) in cs_dsp_coeff_write_acked_control()
698 cs_dsp_dbg(dsp, "Sending 0x%x to acked control alg 0x%x %s:0x%x\n", in cs_dsp_coeff_write_acked_control()
702 ret = regmap_raw_write(dsp->regmap, reg, &val, sizeof(val)); in cs_dsp_coeff_write_acked_control()
704 cs_dsp_err(dsp, "Failed to write %x: %d\n", reg, ret); in cs_dsp_coeff_write_acked_control()
726 ret = regmap_raw_read(dsp->regmap, reg, &val, sizeof(val)); in cs_dsp_coeff_write_acked_control()
728 cs_dsp_err(dsp, "Failed to read %x: %d\n", reg, ret); in cs_dsp_coeff_write_acked_control()
733 cs_dsp_dbg(dsp, "Acked control ACKED at poll %u\n", i); in cs_dsp_coeff_write_acked_control()
738 cs_dsp_warn(dsp, "Acked control @0x%x alg:0x%x %s:0x%x timed out\n", in cs_dsp_coeff_write_acked_control()
750 struct cs_dsp *dsp = ctl->dsp; in cs_dsp_coeff_write_ctrl_raw() local
763 ret = regmap_raw_write(dsp->regmap, reg, scratch, in cs_dsp_coeff_write_ctrl_raw()
766 cs_dsp_err(dsp, "Failed to write %zu bytes to %x: %d\n", in cs_dsp_coeff_write_ctrl_raw()
771 cs_dsp_dbg(dsp, "Wrote %zu bytes to %x\n", len, reg); in cs_dsp_coeff_write_ctrl_raw()
797 lockdep_assert_held(&ctl->dsp->pwr_lock); in cs_dsp_coeff_write_ctrl()
815 if (ctl->enabled && ctl->dsp->running) in cs_dsp_coeff_write_ctrl()
828 struct cs_dsp *dsp = ctl->dsp; in cs_dsp_coeff_read_ctrl_raw() local
841 ret = regmap_raw_read(dsp->regmap, reg, scratch, len); in cs_dsp_coeff_read_ctrl_raw()
843 cs_dsp_err(dsp, "Failed to read %zu bytes from %x: %d\n", in cs_dsp_coeff_read_ctrl_raw()
848 cs_dsp_dbg(dsp, "Read %zu bytes from %x\n", len, reg); in cs_dsp_coeff_read_ctrl_raw()
875 lockdep_assert_held(&ctl->dsp->pwr_lock); in cs_dsp_coeff_read_ctrl()
881 if (ctl->enabled && ctl->dsp->running) in cs_dsp_coeff_read_ctrl()
886 if (!ctl->flags && ctl->enabled && ctl->dsp->running) in cs_dsp_coeff_read_ctrl()
897 static int cs_dsp_coeff_init_control_caches(struct cs_dsp *dsp) in cs_dsp_coeff_init_control_caches() argument
902 list_for_each_entry(ctl, &dsp->ctl_list, list) { in cs_dsp_coeff_init_control_caches()
909 * For readable controls populate the cache from the DSP memory. in cs_dsp_coeff_init_control_caches()
923 static int cs_dsp_coeff_sync_controls(struct cs_dsp *dsp) in cs_dsp_coeff_sync_controls() argument
928 list_for_each_entry(ctl, &dsp->ctl_list, list) { in cs_dsp_coeff_sync_controls()
942 static void cs_dsp_signal_event_controls(struct cs_dsp *dsp, in cs_dsp_signal_event_controls() argument
948 list_for_each_entry(ctl, &dsp->ctl_list, list) { in cs_dsp_signal_event_controls()
957 cs_dsp_warn(dsp, in cs_dsp_signal_event_controls()
970 static int cs_dsp_create_control(struct cs_dsp *dsp, in cs_dsp_create_control() argument
979 list_for_each_entry(ctl, &dsp->ctl_list, list) { in cs_dsp_create_control()
980 if (ctl->fw_name == dsp->fw_name && in cs_dsp_create_control()
997 ctl->fw_name = dsp->fw_name; in cs_dsp_create_control()
999 if (subname && dsp->fw_ver >= 2) { in cs_dsp_create_control()
1009 ctl->dsp = dsp; in cs_dsp_create_control()
1021 list_add(&ctl->list, &dsp->ctl_list); in cs_dsp_create_control()
1023 if (dsp->client_ops->control_add) { in cs_dsp_create_control()
1024 ret = dsp->client_ops->control_add(ctl); in cs_dsp_create_control()
1115 static int cs_dsp_coeff_parse_alg(struct cs_dsp *dsp, in cs_dsp_coeff_parse_alg() argument
1126 switch (dsp->fw_ver) { in cs_dsp_coeff_parse_alg()
1170 cs_dsp_dbg(dsp, "Algorithm ID: %#x\n", blk->id); in cs_dsp_coeff_parse_alg()
1171 cs_dsp_dbg(dsp, "Algorithm name: %.*s\n", blk->name_len, blk->name); in cs_dsp_coeff_parse_alg()
1172 cs_dsp_dbg(dsp, "# of coefficient descriptors: %#x\n", blk->ncoeff); in cs_dsp_coeff_parse_alg()
1177 static int cs_dsp_coeff_parse_coeff(struct cs_dsp *dsp, in cs_dsp_coeff_parse_coeff() argument
1203 switch (dsp->fw_ver) { in cs_dsp_coeff_parse_coeff()
1246 cs_dsp_dbg(dsp, "\tCoefficient type: %#x\n", blk->mem_type); in cs_dsp_coeff_parse_coeff()
1247 cs_dsp_dbg(dsp, "\tCoefficient offset: %#x\n", blk->offset); in cs_dsp_coeff_parse_coeff()
1248 cs_dsp_dbg(dsp, "\tCoefficient name: %.*s\n", blk->name_len, blk->name); in cs_dsp_coeff_parse_coeff()
1249 cs_dsp_dbg(dsp, "\tCoefficient flags: %#x\n", blk->flags); in cs_dsp_coeff_parse_coeff()
1250 cs_dsp_dbg(dsp, "\tALSA control type: %#x\n", blk->ctl_type); in cs_dsp_coeff_parse_coeff()
1251 cs_dsp_dbg(dsp, "\tALSA control len: %#x\n", blk->len); in cs_dsp_coeff_parse_coeff()
1256 static int cs_dsp_check_coeff_flags(struct cs_dsp *dsp, in cs_dsp_check_coeff_flags() argument
1263 cs_dsp_err(dsp, "Illegal flags 0x%x for control type 0x%x\n", in cs_dsp_check_coeff_flags()
1271 static int cs_dsp_parse_coeff(struct cs_dsp *dsp, in cs_dsp_parse_coeff() argument
1279 pos = cs_dsp_coeff_parse_alg(dsp, region, &alg_blk); in cs_dsp_parse_coeff()
1284 pos = cs_dsp_coeff_parse_coeff(dsp, region, pos, &coeff_blk); in cs_dsp_parse_coeff()
1295 ret = cs_dsp_check_coeff_flags(dsp, &coeff_blk, in cs_dsp_parse_coeff()
1305 ret = cs_dsp_check_coeff_flags(dsp, &coeff_blk, in cs_dsp_parse_coeff()
1315 ret = cs_dsp_check_coeff_flags(dsp, &coeff_blk, in cs_dsp_parse_coeff()
1324 cs_dsp_err(dsp, "Unknown control type: %d\n", in cs_dsp_parse_coeff()
1332 ret = cs_dsp_create_control(dsp, &alg_region, in cs_dsp_parse_coeff()
1340 cs_dsp_err(dsp, "Failed to create control: %.*s, %d\n", in cs_dsp_parse_coeff()
1347 static unsigned int cs_dsp_adsp1_parse_sizes(struct cs_dsp *dsp, in cs_dsp_adsp1_parse_sizes() argument
1356 cs_dsp_err(dsp, "%s: file truncated\n", file); in cs_dsp_adsp1_parse_sizes()
1360 cs_dsp_dbg(dsp, "%s: %d DM, %d PM, %d ZM\n", file, in cs_dsp_adsp1_parse_sizes()
1367 static unsigned int cs_dsp_adsp2_parse_sizes(struct cs_dsp *dsp, in cs_dsp_adsp2_parse_sizes() argument
1376 cs_dsp_err(dsp, "%s: file truncated\n", file); in cs_dsp_adsp2_parse_sizes()
1380 cs_dsp_dbg(dsp, "%s: %d XM, %d YM %d PM, %d ZM\n", file, in cs_dsp_adsp2_parse_sizes()
1387 static bool cs_dsp_validate_version(struct cs_dsp *dsp, unsigned int version) in cs_dsp_validate_version() argument
1391 cs_dsp_warn(dsp, "Deprecated file format %d\n", version); in cs_dsp_validate_version()
1401 static bool cs_dsp_halo_validate_version(struct cs_dsp *dsp, unsigned int version) in cs_dsp_halo_validate_version() argument
1411 static int cs_dsp_load(struct cs_dsp *dsp, const struct firmware *firmware, in cs_dsp_load() argument
1415 struct regmap *regmap = dsp->regmap; in cs_dsp_load()
1441 cs_dsp_err(dsp, "%s: invalid magic\n", file); in cs_dsp_load()
1445 if (!dsp->ops->validate_version(dsp, header->ver)) { in cs_dsp_load()
1446 cs_dsp_err(dsp, "%s: unknown file format %d\n", in cs_dsp_load()
1451 cs_dsp_info(dsp, "Firmware version: %d\n", header->ver); in cs_dsp_load()
1452 dsp->fw_ver = header->ver; in cs_dsp_load()
1454 if (header->core != dsp->type) { in cs_dsp_load()
1455 cs_dsp_err(dsp, "%s: invalid core %d != %d\n", in cs_dsp_load()
1456 file, header->core, dsp->type); in cs_dsp_load()
1461 pos = dsp->ops->parse_sizes(dsp, file, pos, firmware); in cs_dsp_load()
1475 cs_dsp_dbg(dsp, "%s: timestamp %llu\n", file, in cs_dsp_load()
1506 ret = cs_dsp_parse_coeff(dsp, region); in cs_dsp_load()
1527 mem = cs_dsp_find_region(dsp, type); in cs_dsp_load()
1529 cs_dsp_err(dsp, "No region of type: %x\n", type); in cs_dsp_load()
1535 reg = dsp->ops->region_to_reg(mem, offset); in cs_dsp_load()
1538 cs_dsp_warn(dsp, in cs_dsp_load()
1544 cs_dsp_dbg(dsp, "%s.%d: %d bytes at %d in %s\n", file, in cs_dsp_load()
1550 cs_dsp_info(dsp, "%s: %s\n", file, text); in cs_dsp_load()
1560 cs_dsp_err(dsp, "Out of memory\n"); in cs_dsp_load()
1568 cs_dsp_err(dsp, in cs_dsp_load()
1582 cs_dsp_warn(dsp, "%s.%d: %zu bytes at end of file\n", in cs_dsp_load()
1585 cs_dsp_debugfs_save_wmfwname(dsp, file); in cs_dsp_load()
1593 cs_dsp_err(dsp, "%s: file content overflows file data\n", file); in cs_dsp_load()
1600 * @dsp: pointer to DSP structure
1609 struct cs_dsp_coeff_ctl *cs_dsp_get_ctl(struct cs_dsp *dsp, const char *name, int type, in cs_dsp_get_ctl() argument
1614 lockdep_assert_held(&dsp->pwr_lock); in cs_dsp_get_ctl()
1616 list_for_each_entry(pos, &dsp->ctl_list, list) { in cs_dsp_get_ctl()
1620 pos->fw_name == dsp->fw_name && in cs_dsp_get_ctl()
1632 static void cs_dsp_ctl_fixup_base(struct cs_dsp *dsp, in cs_dsp_ctl_fixup_base() argument
1637 list_for_each_entry(ctl, &dsp->ctl_list, list) { in cs_dsp_ctl_fixup_base()
1638 if (ctl->fw_name == dsp->fw_name && in cs_dsp_ctl_fixup_base()
1646 static void *cs_dsp_read_algs(struct cs_dsp *dsp, size_t n_algs, in cs_dsp_read_algs() argument
1656 cs_dsp_err(dsp, "No algorithms\n"); in cs_dsp_read_algs()
1661 cs_dsp_err(dsp, "Algorithm count %zx excessive\n", n_algs); in cs_dsp_read_algs()
1666 reg = dsp->ops->region_to_reg(mem, pos + len); in cs_dsp_read_algs()
1668 ret = regmap_raw_read(dsp->regmap, reg, &val, sizeof(val)); in cs_dsp_read_algs()
1670 cs_dsp_err(dsp, "Failed to read algorithm list end: %d\n", in cs_dsp_read_algs()
1676 cs_dsp_warn(dsp, "Algorithm list end %x 0x%x != 0xbedead\n", in cs_dsp_read_algs()
1679 /* Convert length from DSP words to bytes */ in cs_dsp_read_algs()
1686 reg = dsp->ops->region_to_reg(mem, pos); in cs_dsp_read_algs()
1688 ret = regmap_raw_read(dsp->regmap, reg, alg, len); in cs_dsp_read_algs()
1690 cs_dsp_err(dsp, "Failed to read algorithm list: %d\n", ret); in cs_dsp_read_algs()
1700 * @dsp: pointer to DSP structure
1706 struct cs_dsp_alg_region *cs_dsp_find_alg_region(struct cs_dsp *dsp, in cs_dsp_find_alg_region() argument
1711 lockdep_assert_held(&dsp->pwr_lock); in cs_dsp_find_alg_region()
1713 list_for_each_entry(alg_region, &dsp->alg_regions, list) { in cs_dsp_find_alg_region()
1722 static struct cs_dsp_alg_region *cs_dsp_create_region(struct cs_dsp *dsp, in cs_dsp_create_region() argument
1737 list_add_tail(&alg_region->list, &dsp->alg_regions); in cs_dsp_create_region()
1739 if (dsp->fw_ver > 0) in cs_dsp_create_region()
1740 cs_dsp_ctl_fixup_base(dsp, alg_region); in cs_dsp_create_region()
1745 static void cs_dsp_free_alg_regions(struct cs_dsp *dsp) in cs_dsp_free_alg_regions() argument
1749 while (!list_empty(&dsp->alg_regions)) { in cs_dsp_free_alg_regions()
1750 alg_region = list_first_entry(&dsp->alg_regions, in cs_dsp_free_alg_regions()
1758 static void cs_dsp_parse_wmfw_id_header(struct cs_dsp *dsp, in cs_dsp_parse_wmfw_id_header() argument
1761 dsp->fw_id = be32_to_cpu(fw->id); in cs_dsp_parse_wmfw_id_header()
1762 dsp->fw_id_version = be32_to_cpu(fw->ver); in cs_dsp_parse_wmfw_id_header()
1764 cs_dsp_info(dsp, "Firmware: %x v%d.%d.%d, %d algorithms\n", in cs_dsp_parse_wmfw_id_header()
1765 dsp->fw_id, (dsp->fw_id_version & 0xff0000) >> 16, in cs_dsp_parse_wmfw_id_header()
1766 (dsp->fw_id_version & 0xff00) >> 8, dsp->fw_id_version & 0xff, in cs_dsp_parse_wmfw_id_header()
1770 static void cs_dsp_parse_wmfw_v3_id_header(struct cs_dsp *dsp, in cs_dsp_parse_wmfw_v3_id_header() argument
1773 dsp->fw_id = be32_to_cpu(fw->id); in cs_dsp_parse_wmfw_v3_id_header()
1774 dsp->fw_id_version = be32_to_cpu(fw->ver); in cs_dsp_parse_wmfw_v3_id_header()
1775 dsp->fw_vendor_id = be32_to_cpu(fw->vendor_id); in cs_dsp_parse_wmfw_v3_id_header()
1777 cs_dsp_info(dsp, "Firmware: %x vendor: 0x%x v%d.%d.%d, %d algorithms\n", in cs_dsp_parse_wmfw_v3_id_header()
1778 dsp->fw_id, dsp->fw_vendor_id, in cs_dsp_parse_wmfw_v3_id_header()
1779 (dsp->fw_id_version & 0xff0000) >> 16, in cs_dsp_parse_wmfw_v3_id_header()
1780 (dsp->fw_id_version & 0xff00) >> 8, dsp->fw_id_version & 0xff, in cs_dsp_parse_wmfw_v3_id_header()
1784 static int cs_dsp_create_regions(struct cs_dsp *dsp, __be32 id, __be32 ver, in cs_dsp_create_regions() argument
1791 alg_region = cs_dsp_create_region(dsp, type[i], id, ver, base[i]); in cs_dsp_create_regions()
1799 static int cs_dsp_adsp1_setup_algs(struct cs_dsp *dsp) in cs_dsp_adsp1_setup_algs() argument
1809 mem = cs_dsp_find_region(dsp, WMFW_ADSP1_DM); in cs_dsp_adsp1_setup_algs()
1813 ret = regmap_raw_read(dsp->regmap, mem->base, &adsp1_id, in cs_dsp_adsp1_setup_algs()
1816 cs_dsp_err(dsp, "Failed to read algorithm info: %d\n", in cs_dsp_adsp1_setup_algs()
1823 cs_dsp_parse_wmfw_id_header(dsp, &adsp1_id.fw, n_algs); in cs_dsp_adsp1_setup_algs()
1825 alg_region = cs_dsp_create_region(dsp, WMFW_ADSP1_ZM, in cs_dsp_adsp1_setup_algs()
1831 alg_region = cs_dsp_create_region(dsp, WMFW_ADSP1_DM, in cs_dsp_adsp1_setup_algs()
1837 /* Calculate offset and length in DSP words */ in cs_dsp_adsp1_setup_algs()
1841 adsp1_alg = cs_dsp_read_algs(dsp, n_algs, mem, pos, len); in cs_dsp_adsp1_setup_algs()
1846 cs_dsp_info(dsp, "%d: ID %x v%d.%d.%d DM@%x ZM@%x\n", in cs_dsp_adsp1_setup_algs()
1854 alg_region = cs_dsp_create_region(dsp, WMFW_ADSP1_DM, in cs_dsp_adsp1_setup_algs()
1862 if (dsp->fw_ver == 0) { in cs_dsp_adsp1_setup_algs()
1867 cs_dsp_create_control(dsp, alg_region, 0, in cs_dsp_adsp1_setup_algs()
1871 cs_dsp_warn(dsp, "Missing length info for region DM with ID %x\n", in cs_dsp_adsp1_setup_algs()
1876 alg_region = cs_dsp_create_region(dsp, WMFW_ADSP1_ZM, in cs_dsp_adsp1_setup_algs()
1884 if (dsp->fw_ver == 0) { in cs_dsp_adsp1_setup_algs()
1889 cs_dsp_create_control(dsp, alg_region, 0, in cs_dsp_adsp1_setup_algs()
1893 cs_dsp_warn(dsp, "Missing length info for region ZM with ID %x\n", in cs_dsp_adsp1_setup_algs()
1904 static int cs_dsp_adsp2_setup_algs(struct cs_dsp *dsp) in cs_dsp_adsp2_setup_algs() argument
1914 mem = cs_dsp_find_region(dsp, WMFW_ADSP2_XM); in cs_dsp_adsp2_setup_algs()
1918 ret = regmap_raw_read(dsp->regmap, mem->base, &adsp2_id, in cs_dsp_adsp2_setup_algs()
1921 cs_dsp_err(dsp, "Failed to read algorithm info: %d\n", in cs_dsp_adsp2_setup_algs()
1928 cs_dsp_parse_wmfw_id_header(dsp, &adsp2_id.fw, n_algs); in cs_dsp_adsp2_setup_algs()
1930 alg_region = cs_dsp_create_region(dsp, WMFW_ADSP2_XM, in cs_dsp_adsp2_setup_algs()
1936 alg_region = cs_dsp_create_region(dsp, WMFW_ADSP2_YM, in cs_dsp_adsp2_setup_algs()
1942 alg_region = cs_dsp_create_region(dsp, WMFW_ADSP2_ZM, in cs_dsp_adsp2_setup_algs()
1948 /* Calculate offset and length in DSP words */ in cs_dsp_adsp2_setup_algs()
1952 adsp2_alg = cs_dsp_read_algs(dsp, n_algs, mem, pos, len); in cs_dsp_adsp2_setup_algs()
1957 cs_dsp_dbg(dsp, in cs_dsp_adsp2_setup_algs()
1967 alg_region = cs_dsp_create_region(dsp, WMFW_ADSP2_XM, in cs_dsp_adsp2_setup_algs()
1975 if (dsp->fw_ver == 0) { in cs_dsp_adsp2_setup_algs()
1980 cs_dsp_create_control(dsp, alg_region, 0, in cs_dsp_adsp2_setup_algs()
1984 cs_dsp_warn(dsp, "Missing length info for region XM with ID %x\n", in cs_dsp_adsp2_setup_algs()
1989 alg_region = cs_dsp_create_region(dsp, WMFW_ADSP2_YM, in cs_dsp_adsp2_setup_algs()
1997 if (dsp->fw_ver == 0) { in cs_dsp_adsp2_setup_algs()
2002 cs_dsp_create_control(dsp, alg_region, 0, in cs_dsp_adsp2_setup_algs()
2006 cs_dsp_warn(dsp, "Missing length info for region YM with ID %x\n", in cs_dsp_adsp2_setup_algs()
2011 alg_region = cs_dsp_create_region(dsp, WMFW_ADSP2_ZM, in cs_dsp_adsp2_setup_algs()
2019 if (dsp->fw_ver == 0) { in cs_dsp_adsp2_setup_algs()
2024 cs_dsp_create_control(dsp, alg_region, 0, in cs_dsp_adsp2_setup_algs()
2028 cs_dsp_warn(dsp, "Missing length info for region ZM with ID %x\n", in cs_dsp_adsp2_setup_algs()
2039 static int cs_dsp_halo_create_regions(struct cs_dsp *dsp, __be32 id, __be32 ver, in cs_dsp_halo_create_regions() argument
2048 return cs_dsp_create_regions(dsp, id, ver, ARRAY_SIZE(types), types, bases); in cs_dsp_halo_create_regions()
2051 static int cs_dsp_halo_setup_algs(struct cs_dsp *dsp) in cs_dsp_halo_setup_algs() argument
2060 mem = cs_dsp_find_region(dsp, WMFW_ADSP2_XM); in cs_dsp_halo_setup_algs()
2064 ret = regmap_raw_read(dsp->regmap, mem->base, &halo_id, in cs_dsp_halo_setup_algs()
2067 cs_dsp_err(dsp, "Failed to read algorithm info: %d\n", in cs_dsp_halo_setup_algs()
2074 cs_dsp_parse_wmfw_v3_id_header(dsp, &halo_id.fw, n_algs); in cs_dsp_halo_setup_algs()
2076 ret = cs_dsp_halo_create_regions(dsp, halo_id.fw.id, halo_id.fw.ver, in cs_dsp_halo_setup_algs()
2081 /* Calculate offset and length in DSP words */ in cs_dsp_halo_setup_algs()
2085 halo_alg = cs_dsp_read_algs(dsp, n_algs, mem, pos, len); in cs_dsp_halo_setup_algs()
2090 cs_dsp_dbg(dsp, in cs_dsp_halo_setup_algs()
2099 ret = cs_dsp_halo_create_regions(dsp, halo_alg[i].alg.id, in cs_dsp_halo_setup_algs()
2112 static int cs_dsp_load_coeff(struct cs_dsp *dsp, const struct firmware *firmware, in cs_dsp_load_coeff() argument
2116 struct regmap *regmap = dsp->regmap; in cs_dsp_load_coeff()
2132 cs_dsp_err(dsp, "%s: coefficient file too short, %zu bytes\n", in cs_dsp_load_coeff()
2139 cs_dsp_err(dsp, "%s: invalid coefficient magic\n", file); in cs_dsp_load_coeff()
2148 cs_dsp_err(dsp, "%s: Unsupported coefficient file format %d\n", in cs_dsp_load_coeff()
2154 cs_dsp_info(dsp, "%s: v%d.%d.%d\n", file, in cs_dsp_load_coeff()
2180 cs_dsp_dbg(dsp, "%s.%d: %x v%d.%d.%d\n", in cs_dsp_load_coeff()
2185 cs_dsp_dbg(dsp, "%s.%d: %d bytes at 0x%x in %x\n", in cs_dsp_load_coeff()
2202 if (le32_to_cpu(blk->id) == dsp->fw_id && in cs_dsp_load_coeff()
2205 mem = cs_dsp_find_region(dsp, type); in cs_dsp_load_coeff()
2207 cs_dsp_err(dsp, "No ZM\n"); in cs_dsp_load_coeff()
2210 reg = dsp->ops->region_to_reg(mem, 0); in cs_dsp_load_coeff()
2225 cs_dsp_dbg(dsp, "%s.%d: %d bytes in %x for %x\n", in cs_dsp_load_coeff()
2230 mem = cs_dsp_find_region(dsp, type); in cs_dsp_load_coeff()
2232 cs_dsp_err(dsp, "No base for region %x\n", type); in cs_dsp_load_coeff()
2236 alg_region = cs_dsp_find_alg_region(dsp, type, in cs_dsp_load_coeff()
2240 cs_dsp_warn(dsp, in cs_dsp_load_coeff()
2250 reg = dsp->ops->region_to_reg(mem, reg); in cs_dsp_load_coeff()
2253 cs_dsp_err(dsp, "No %s for algorithm %x\n", in cs_dsp_load_coeff()
2259 cs_dsp_err(dsp, "%s.%d: Unknown region type %x at %d\n", in cs_dsp_load_coeff()
2266 cs_dsp_info(dsp, "%s: %s\n", dsp->fw_name, text); in cs_dsp_load_coeff()
2276 cs_dsp_err(dsp, "Out of memory\n"); in cs_dsp_load_coeff()
2281 cs_dsp_dbg(dsp, "%s.%d: Writing %d bytes at %x\n", in cs_dsp_load_coeff()
2287 cs_dsp_err(dsp, in cs_dsp_load_coeff()
2298 cs_dsp_warn(dsp, "%s.%d: %zu bytes at end of file\n", in cs_dsp_load_coeff()
2301 cs_dsp_debugfs_save_binname(dsp, file); in cs_dsp_load_coeff()
2309 cs_dsp_err(dsp, "%s: file content overflows file data\n", file); in cs_dsp_load_coeff()
2314 static int cs_dsp_create_name(struct cs_dsp *dsp) in cs_dsp_create_name() argument
2316 if (!dsp->name) { in cs_dsp_create_name()
2317 dsp->name = devm_kasprintf(dsp->dev, GFP_KERNEL, "DSP%d", in cs_dsp_create_name()
2318 dsp->num); in cs_dsp_create_name()
2319 if (!dsp->name) in cs_dsp_create_name()
2326 static int cs_dsp_common_init(struct cs_dsp *dsp) in cs_dsp_common_init() argument
2330 ret = cs_dsp_create_name(dsp); in cs_dsp_common_init()
2334 INIT_LIST_HEAD(&dsp->alg_regions); in cs_dsp_common_init()
2335 INIT_LIST_HEAD(&dsp->ctl_list); in cs_dsp_common_init()
2337 mutex_init(&dsp->pwr_lock); in cs_dsp_common_init()
2341 dsp->debugfs_root = ERR_PTR(-ENODEV); in cs_dsp_common_init()
2349 * @dsp: pointer to DSP structure
2353 int cs_dsp_adsp1_init(struct cs_dsp *dsp) in cs_dsp_adsp1_init() argument
2355 dsp->ops = &cs_dsp_adsp1_ops; in cs_dsp_adsp1_init()
2357 return cs_dsp_common_init(dsp); in cs_dsp_adsp1_init()
2363 * @dsp: pointer to DSP structure
2372 int cs_dsp_adsp1_power_up(struct cs_dsp *dsp, in cs_dsp_adsp1_power_up() argument
2380 mutex_lock(&dsp->pwr_lock); in cs_dsp_adsp1_power_up()
2382 dsp->fw_name = fw_name; in cs_dsp_adsp1_power_up()
2384 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30, in cs_dsp_adsp1_power_up()
2388 * For simplicity set the DSP clock rate to be the in cs_dsp_adsp1_power_up()
2391 if (dsp->sysclk_reg) { in cs_dsp_adsp1_power_up()
2392 ret = regmap_read(dsp->regmap, dsp->sysclk_reg, &val); in cs_dsp_adsp1_power_up()
2394 cs_dsp_err(dsp, "Failed to read SYSCLK state: %d\n", ret); in cs_dsp_adsp1_power_up()
2398 val = (val & dsp->sysclk_mask) >> dsp->sysclk_shift; in cs_dsp_adsp1_power_up()
2400 ret = regmap_update_bits(dsp->regmap, in cs_dsp_adsp1_power_up()
2401 dsp->base + ADSP1_CONTROL_31, in cs_dsp_adsp1_power_up()
2404 cs_dsp_err(dsp, "Failed to set clock rate: %d\n", ret); in cs_dsp_adsp1_power_up()
2409 ret = cs_dsp_load(dsp, wmfw_firmware, wmfw_filename); in cs_dsp_adsp1_power_up()
2413 ret = cs_dsp_adsp1_setup_algs(dsp); in cs_dsp_adsp1_power_up()
2417 ret = cs_dsp_load_coeff(dsp, coeff_firmware, coeff_filename); in cs_dsp_adsp1_power_up()
2422 ret = cs_dsp_coeff_init_control_caches(dsp); in cs_dsp_adsp1_power_up()
2427 ret = cs_dsp_coeff_sync_controls(dsp); in cs_dsp_adsp1_power_up()
2431 dsp->booted = true; in cs_dsp_adsp1_power_up()
2434 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30, in cs_dsp_adsp1_power_up()
2438 dsp->running = true; in cs_dsp_adsp1_power_up()
2440 mutex_unlock(&dsp->pwr_lock); in cs_dsp_adsp1_power_up()
2445 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30, in cs_dsp_adsp1_power_up()
2448 mutex_unlock(&dsp->pwr_lock); in cs_dsp_adsp1_power_up()
2454 * cs_dsp_adsp1_power_down() - Halts the DSP
2455 * @dsp: pointer to DSP structure
2457 void cs_dsp_adsp1_power_down(struct cs_dsp *dsp) in cs_dsp_adsp1_power_down() argument
2461 mutex_lock(&dsp->pwr_lock); in cs_dsp_adsp1_power_down()
2463 dsp->running = false; in cs_dsp_adsp1_power_down()
2464 dsp->booted = false; in cs_dsp_adsp1_power_down()
2467 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30, in cs_dsp_adsp1_power_down()
2470 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_19, in cs_dsp_adsp1_power_down()
2473 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30, in cs_dsp_adsp1_power_down()
2476 list_for_each_entry(ctl, &dsp->ctl_list, list) in cs_dsp_adsp1_power_down()
2479 cs_dsp_free_alg_regions(dsp); in cs_dsp_adsp1_power_down()
2481 mutex_unlock(&dsp->pwr_lock); in cs_dsp_adsp1_power_down()
2485 static int cs_dsp_adsp2v2_enable_core(struct cs_dsp *dsp) in cs_dsp_adsp2v2_enable_core() argument
2492 ret = regmap_read(dsp->regmap, dsp->base + ADSP2_STATUS1, &val); in cs_dsp_adsp2v2_enable_core()
2503 cs_dsp_err(dsp, "Failed to start DSP RAM\n"); in cs_dsp_adsp2v2_enable_core()
2507 cs_dsp_dbg(dsp, "RAM ready after %d polls\n", count); in cs_dsp_adsp2v2_enable_core()
2512 static int cs_dsp_adsp2_enable_core(struct cs_dsp *dsp) in cs_dsp_adsp2_enable_core() argument
2516 ret = regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL, in cs_dsp_adsp2_enable_core()
2521 return cs_dsp_adsp2v2_enable_core(dsp); in cs_dsp_adsp2_enable_core()
2524 static int cs_dsp_adsp2_lock(struct cs_dsp *dsp, unsigned int lock_regions) in cs_dsp_adsp2_lock() argument
2526 struct regmap *regmap = dsp->regmap; in cs_dsp_adsp2_lock()
2533 lock_reg = dsp->base + ADSP2_LOCK_REGION_1_LOCK_REGION_0; in cs_dsp_adsp2_lock()
2554 static int cs_dsp_adsp2_enable_memory(struct cs_dsp *dsp) in cs_dsp_adsp2_enable_memory() argument
2556 return regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL, in cs_dsp_adsp2_enable_memory()
2560 static void cs_dsp_adsp2_disable_memory(struct cs_dsp *dsp) in cs_dsp_adsp2_disable_memory() argument
2562 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL, in cs_dsp_adsp2_disable_memory()
2566 static void cs_dsp_adsp2_disable_core(struct cs_dsp *dsp) in cs_dsp_adsp2_disable_core() argument
2568 regmap_write(dsp->regmap, dsp->base + ADSP2_RDMA_CONFIG_1, 0); in cs_dsp_adsp2_disable_core()
2569 regmap_write(dsp->regmap, dsp->base + ADSP2_WDMA_CONFIG_1, 0); in cs_dsp_adsp2_disable_core()
2570 regmap_write(dsp->regmap, dsp->base + ADSP2_WDMA_CONFIG_2, 0); in cs_dsp_adsp2_disable_core()
2572 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL, in cs_dsp_adsp2_disable_core()
2576 static void cs_dsp_adsp2v2_disable_core(struct cs_dsp *dsp) in cs_dsp_adsp2v2_disable_core() argument
2578 regmap_write(dsp->regmap, dsp->base + ADSP2_RDMA_CONFIG_1, 0); in cs_dsp_adsp2v2_disable_core()
2579 regmap_write(dsp->regmap, dsp->base + ADSP2_WDMA_CONFIG_1, 0); in cs_dsp_adsp2v2_disable_core()
2580 regmap_write(dsp->regmap, dsp->base + ADSP2V2_WDMA_CONFIG_2, 0); in cs_dsp_adsp2v2_disable_core()
2583 static int cs_dsp_halo_configure_mpu(struct cs_dsp *dsp, unsigned int lock_regions) in cs_dsp_halo_configure_mpu() argument
2586 { dsp->base + HALO_MPU_LOCK_CONFIG, 0x5555 }, in cs_dsp_halo_configure_mpu()
2587 { dsp->base + HALO_MPU_LOCK_CONFIG, 0xAAAA }, in cs_dsp_halo_configure_mpu()
2588 { dsp->base + HALO_MPU_XMEM_ACCESS_0, 0xFFFFFFFF }, in cs_dsp_halo_configure_mpu()
2589 { dsp->base + HALO_MPU_YMEM_ACCESS_0, 0xFFFFFFFF }, in cs_dsp_halo_configure_mpu()
2590 { dsp->base + HALO_MPU_WINDOW_ACCESS_0, lock_regions }, in cs_dsp_halo_configure_mpu()
2591 { dsp->base + HALO_MPU_XREG_ACCESS_0, lock_regions }, in cs_dsp_halo_configure_mpu()
2592 { dsp->base + HALO_MPU_YREG_ACCESS_0, lock_regions }, in cs_dsp_halo_configure_mpu()
2593 { dsp->base + HALO_MPU_XMEM_ACCESS_1, 0xFFFFFFFF }, in cs_dsp_halo_configure_mpu()
2594 { dsp->base + HALO_MPU_YMEM_ACCESS_1, 0xFFFFFFFF }, in cs_dsp_halo_configure_mpu()
2595 { dsp->base + HALO_MPU_WINDOW_ACCESS_1, lock_regions }, in cs_dsp_halo_configure_mpu()
2596 { dsp->base + HALO_MPU_XREG_ACCESS_1, lock_regions }, in cs_dsp_halo_configure_mpu()
2597 { dsp->base + HALO_MPU_YREG_ACCESS_1, lock_regions }, in cs_dsp_halo_configure_mpu()
2598 { dsp->base + HALO_MPU_XMEM_ACCESS_2, 0xFFFFFFFF }, in cs_dsp_halo_configure_mpu()
2599 { dsp->base + HALO_MPU_YMEM_ACCESS_2, 0xFFFFFFFF }, in cs_dsp_halo_configure_mpu()
2600 { dsp->base + HALO_MPU_WINDOW_ACCESS_2, lock_regions }, in cs_dsp_halo_configure_mpu()
2601 { dsp->base + HALO_MPU_XREG_ACCESS_2, lock_regions }, in cs_dsp_halo_configure_mpu()
2602 { dsp->base + HALO_MPU_YREG_ACCESS_2, lock_regions }, in cs_dsp_halo_configure_mpu()
2603 { dsp->base + HALO_MPU_XMEM_ACCESS_3, 0xFFFFFFFF }, in cs_dsp_halo_configure_mpu()
2604 { dsp->base + HALO_MPU_YMEM_ACCESS_3, 0xFFFFFFFF }, in cs_dsp_halo_configure_mpu()
2605 { dsp->base + HALO_MPU_WINDOW_ACCESS_3, lock_regions }, in cs_dsp_halo_configure_mpu()
2606 { dsp->base + HALO_MPU_XREG_ACCESS_3, lock_regions }, in cs_dsp_halo_configure_mpu()
2607 { dsp->base + HALO_MPU_YREG_ACCESS_3, lock_regions }, in cs_dsp_halo_configure_mpu()
2608 { dsp->base + HALO_MPU_LOCK_CONFIG, 0 }, in cs_dsp_halo_configure_mpu()
2611 return regmap_multi_reg_write(dsp->regmap, config, ARRAY_SIZE(config)); in cs_dsp_halo_configure_mpu()
2616 * @dsp: pointer to DSP structure
2623 int cs_dsp_set_dspclk(struct cs_dsp *dsp, unsigned int freq) in cs_dsp_set_dspclk() argument
2627 ret = regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CLOCKING, in cs_dsp_set_dspclk()
2631 cs_dsp_err(dsp, "Failed to set clock rate: %d\n", ret); in cs_dsp_set_dspclk()
2637 static void cs_dsp_stop_watchdog(struct cs_dsp *dsp) in cs_dsp_stop_watchdog() argument
2639 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_WATCHDOG, in cs_dsp_stop_watchdog()
2643 static void cs_dsp_halo_stop_watchdog(struct cs_dsp *dsp) in cs_dsp_halo_stop_watchdog() argument
2645 regmap_update_bits(dsp->regmap, dsp->base + HALO_WDT_CONTROL, in cs_dsp_halo_stop_watchdog()
2650 * cs_dsp_power_up() - Downloads firmware to the DSP
2651 * @dsp: pointer to DSP structure
2658 * This function is used on ADSP2 and Halo DSP cores, it powers-up the DSP core
2666 int cs_dsp_power_up(struct cs_dsp *dsp, in cs_dsp_power_up() argument
2673 mutex_lock(&dsp->pwr_lock); in cs_dsp_power_up()
2675 dsp->fw_name = fw_name; in cs_dsp_power_up()
2677 if (dsp->ops->enable_memory) { in cs_dsp_power_up()
2678 ret = dsp->ops->enable_memory(dsp); in cs_dsp_power_up()
2683 if (dsp->ops->enable_core) { in cs_dsp_power_up()
2684 ret = dsp->ops->enable_core(dsp); in cs_dsp_power_up()
2689 ret = cs_dsp_load(dsp, wmfw_firmware, wmfw_filename); in cs_dsp_power_up()
2693 ret = dsp->ops->setup_algs(dsp); in cs_dsp_power_up()
2697 ret = cs_dsp_load_coeff(dsp, coeff_firmware, coeff_filename); in cs_dsp_power_up()
2702 ret = cs_dsp_coeff_init_control_caches(dsp); in cs_dsp_power_up()
2706 if (dsp->ops->disable_core) in cs_dsp_power_up()
2707 dsp->ops->disable_core(dsp); in cs_dsp_power_up()
2709 dsp->booted = true; in cs_dsp_power_up()
2711 mutex_unlock(&dsp->pwr_lock); in cs_dsp_power_up()
2715 if (dsp->ops->disable_core) in cs_dsp_power_up()
2716 dsp->ops->disable_core(dsp); in cs_dsp_power_up()
2718 if (dsp->ops->disable_memory) in cs_dsp_power_up()
2719 dsp->ops->disable_memory(dsp); in cs_dsp_power_up()
2721 mutex_unlock(&dsp->pwr_lock); in cs_dsp_power_up()
2728 * cs_dsp_power_down() - Powers-down the DSP
2729 * @dsp: pointer to DSP structure
2734 void cs_dsp_power_down(struct cs_dsp *dsp) in cs_dsp_power_down() argument
2738 mutex_lock(&dsp->pwr_lock); in cs_dsp_power_down()
2740 cs_dsp_debugfs_clear(dsp); in cs_dsp_power_down()
2742 dsp->fw_id = 0; in cs_dsp_power_down()
2743 dsp->fw_id_version = 0; in cs_dsp_power_down()
2745 dsp->booted = false; in cs_dsp_power_down()
2747 if (dsp->ops->disable_memory) in cs_dsp_power_down()
2748 dsp->ops->disable_memory(dsp); in cs_dsp_power_down()
2750 list_for_each_entry(ctl, &dsp->ctl_list, list) in cs_dsp_power_down()
2753 cs_dsp_free_alg_regions(dsp); in cs_dsp_power_down()
2755 mutex_unlock(&dsp->pwr_lock); in cs_dsp_power_down()
2757 cs_dsp_dbg(dsp, "Shutdown complete\n"); in cs_dsp_power_down()
2761 static int cs_dsp_adsp2_start_core(struct cs_dsp *dsp) in cs_dsp_adsp2_start_core() argument
2763 return regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL, in cs_dsp_adsp2_start_core()
2768 static void cs_dsp_adsp2_stop_core(struct cs_dsp *dsp) in cs_dsp_adsp2_stop_core() argument
2770 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL, in cs_dsp_adsp2_stop_core()
2776 * @dsp: pointer to DSP structure
2782 int cs_dsp_run(struct cs_dsp *dsp) in cs_dsp_run() argument
2786 mutex_lock(&dsp->pwr_lock); in cs_dsp_run()
2788 if (!dsp->booted) { in cs_dsp_run()
2793 if (dsp->ops->enable_core) { in cs_dsp_run()
2794 ret = dsp->ops->enable_core(dsp); in cs_dsp_run()
2799 if (dsp->client_ops->pre_run) { in cs_dsp_run()
2800 ret = dsp->client_ops->pre_run(dsp); in cs_dsp_run()
2806 ret = cs_dsp_coeff_sync_controls(dsp); in cs_dsp_run()
2810 if (dsp->ops->lock_memory) { in cs_dsp_run()
2811 ret = dsp->ops->lock_memory(dsp, dsp->lock_regions); in cs_dsp_run()
2813 cs_dsp_err(dsp, "Error configuring MPU: %d\n", ret); in cs_dsp_run()
2818 if (dsp->ops->start_core) { in cs_dsp_run()
2819 ret = dsp->ops->start_core(dsp); in cs_dsp_run()
2824 dsp->running = true; in cs_dsp_run()
2826 if (dsp->client_ops->post_run) { in cs_dsp_run()
2827 ret = dsp->client_ops->post_run(dsp); in cs_dsp_run()
2832 mutex_unlock(&dsp->pwr_lock); in cs_dsp_run()
2837 if (dsp->ops->stop_core) in cs_dsp_run()
2838 dsp->ops->stop_core(dsp); in cs_dsp_run()
2839 if (dsp->ops->disable_core) in cs_dsp_run()
2840 dsp->ops->disable_core(dsp); in cs_dsp_run()
2841 mutex_unlock(&dsp->pwr_lock); in cs_dsp_run()
2849 * @dsp: pointer to DSP structure
2853 void cs_dsp_stop(struct cs_dsp *dsp) in cs_dsp_stop() argument
2856 cs_dsp_signal_event_controls(dsp, CS_DSP_FW_EVENT_SHUTDOWN); in cs_dsp_stop()
2858 if (dsp->ops->stop_watchdog) in cs_dsp_stop()
2859 dsp->ops->stop_watchdog(dsp); in cs_dsp_stop()
2862 if (dsp->ops->show_fw_status) in cs_dsp_stop()
2863 dsp->ops->show_fw_status(dsp); in cs_dsp_stop()
2865 mutex_lock(&dsp->pwr_lock); in cs_dsp_stop()
2867 if (dsp->client_ops->pre_stop) in cs_dsp_stop()
2868 dsp->client_ops->pre_stop(dsp); in cs_dsp_stop()
2870 dsp->running = false; in cs_dsp_stop()
2872 if (dsp->ops->stop_core) in cs_dsp_stop()
2873 dsp->ops->stop_core(dsp); in cs_dsp_stop()
2874 if (dsp->ops->disable_core) in cs_dsp_stop()
2875 dsp->ops->disable_core(dsp); in cs_dsp_stop()
2877 if (dsp->client_ops->post_stop) in cs_dsp_stop()
2878 dsp->client_ops->post_stop(dsp); in cs_dsp_stop()
2880 mutex_unlock(&dsp->pwr_lock); in cs_dsp_stop()
2882 cs_dsp_dbg(dsp, "Execution stopped\n"); in cs_dsp_stop()
2886 static int cs_dsp_halo_start_core(struct cs_dsp *dsp) in cs_dsp_halo_start_core() argument
2890 ret = regmap_update_bits(dsp->regmap, dsp->base + HALO_CCM_CORE_CONTROL, in cs_dsp_halo_start_core()
2896 return regmap_update_bits(dsp->regmap, dsp->base + HALO_CCM_CORE_CONTROL, in cs_dsp_halo_start_core()
2900 static void cs_dsp_halo_stop_core(struct cs_dsp *dsp) in cs_dsp_halo_stop_core() argument
2902 regmap_update_bits(dsp->regmap, dsp->base + HALO_CCM_CORE_CONTROL, in cs_dsp_halo_stop_core()
2906 regmap_update_bits(dsp->regmap, dsp->base + HALO_CORE_SOFT_RESET, in cs_dsp_halo_stop_core()
2912 * @dsp: pointer to DSP structure
2916 int cs_dsp_adsp2_init(struct cs_dsp *dsp) in cs_dsp_adsp2_init() argument
2920 switch (dsp->rev) { in cs_dsp_adsp2_init()
2923 * Disable the DSP memory by default when in reset for a small in cs_dsp_adsp2_init()
2926 ret = regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL, in cs_dsp_adsp2_init()
2929 cs_dsp_err(dsp, in cs_dsp_adsp2_init()
2934 dsp->ops = &cs_dsp_adsp2_ops[0]; in cs_dsp_adsp2_init()
2937 dsp->ops = &cs_dsp_adsp2_ops[1]; in cs_dsp_adsp2_init()
2940 dsp->ops = &cs_dsp_adsp2_ops[2]; in cs_dsp_adsp2_init()
2944 return cs_dsp_common_init(dsp); in cs_dsp_adsp2_init()
2949 * cs_dsp_halo_init() - Initialise a cs_dsp structure representing a HALO Core DSP
2950 * @dsp: pointer to DSP structure
2954 int cs_dsp_halo_init(struct cs_dsp *dsp) in cs_dsp_halo_init() argument
2956 if (dsp->no_core_startstop) in cs_dsp_halo_init()
2957 dsp->ops = &cs_dsp_halo_ao_ops; in cs_dsp_halo_init()
2959 dsp->ops = &cs_dsp_halo_ops; in cs_dsp_halo_init()
2961 return cs_dsp_common_init(dsp); in cs_dsp_halo_init()
2967 * @dsp: pointer to DSP structure
2969 void cs_dsp_remove(struct cs_dsp *dsp) in cs_dsp_remove() argument
2973 while (!list_empty(&dsp->ctl_list)) { in cs_dsp_remove()
2974 ctl = list_first_entry(&dsp->ctl_list, struct cs_dsp_coeff_ctl, list); in cs_dsp_remove()
2976 if (dsp->client_ops->control_remove) in cs_dsp_remove()
2977 dsp->client_ops->control_remove(ctl); in cs_dsp_remove()
2986 * cs_dsp_read_raw_data_block() - Reads a block of data from DSP memory
2987 * @dsp: pointer to DSP structure
2988 * @mem_type: the type of DSP memory containing the data to be read
2993 * If this is used to read unpacked 24-bit memory, each 24-bit DSP word will
2999 int cs_dsp_read_raw_data_block(struct cs_dsp *dsp, int mem_type, unsigned int mem_addr, in cs_dsp_read_raw_data_block() argument
3002 struct cs_dsp_region const *mem = cs_dsp_find_region(dsp, mem_type); in cs_dsp_read_raw_data_block()
3006 lockdep_assert_held(&dsp->pwr_lock); in cs_dsp_read_raw_data_block()
3011 reg = dsp->ops->region_to_reg(mem, mem_addr); in cs_dsp_read_raw_data_block()
3013 ret = regmap_raw_read(dsp->regmap, reg, data, in cs_dsp_read_raw_data_block()
3023 * cs_dsp_read_data_word() - Reads a word from DSP memory
3024 * @dsp: pointer to DSP structure
3025 * @mem_type: the type of DSP memory containing the data to be read
3031 int cs_dsp_read_data_word(struct cs_dsp *dsp, int mem_type, unsigned int mem_addr, u32 *data) in cs_dsp_read_data_word() argument
3036 ret = cs_dsp_read_raw_data_block(dsp, mem_type, mem_addr, 1, &raw); in cs_dsp_read_data_word()
3047 * cs_dsp_write_data_word() - Writes a word to DSP memory
3048 * @dsp: pointer to DSP structure
3049 * @mem_type: the type of DSP memory containing the data to be written
3055 int cs_dsp_write_data_word(struct cs_dsp *dsp, int mem_type, unsigned int mem_addr, u32 data) in cs_dsp_write_data_word() argument
3057 struct cs_dsp_region const *mem = cs_dsp_find_region(dsp, mem_type); in cs_dsp_write_data_word()
3061 lockdep_assert_held(&dsp->pwr_lock); in cs_dsp_write_data_word()
3066 reg = dsp->ops->region_to_reg(mem, mem_addr); in cs_dsp_write_data_word()
3068 return regmap_raw_write(dsp->regmap, reg, &val, sizeof(val)); in cs_dsp_write_data_word()
3074 * @buf: buffer containing DSP words read from DSP memory
3077 * DSP words from the register map have pad bytes and the data bytes
3097 * cs_dsp_adsp2_bus_error() - Handle a DSP bus error interrupt
3098 * @dsp: pointer to DSP structure
3100 * The firmware and DSP state will be logged for future analysis.
3102 void cs_dsp_adsp2_bus_error(struct cs_dsp *dsp) in cs_dsp_adsp2_bus_error() argument
3105 struct regmap *regmap = dsp->regmap; in cs_dsp_adsp2_bus_error()
3108 mutex_lock(&dsp->pwr_lock); in cs_dsp_adsp2_bus_error()
3110 ret = regmap_read(regmap, dsp->base + ADSP2_LOCK_REGION_CTRL, &val); in cs_dsp_adsp2_bus_error()
3112 cs_dsp_err(dsp, in cs_dsp_adsp2_bus_error()
3118 cs_dsp_err(dsp, "watchdog timeout error\n"); in cs_dsp_adsp2_bus_error()
3119 dsp->ops->stop_watchdog(dsp); in cs_dsp_adsp2_bus_error()
3120 if (dsp->client_ops->watchdog_expired) in cs_dsp_adsp2_bus_error()
3121 dsp->client_ops->watchdog_expired(dsp); in cs_dsp_adsp2_bus_error()
3126 cs_dsp_err(dsp, "bus error: address error\n"); in cs_dsp_adsp2_bus_error()
3128 cs_dsp_err(dsp, "bus error: region lock error\n"); in cs_dsp_adsp2_bus_error()
3130 ret = regmap_read(regmap, dsp->base + ADSP2_BUS_ERR_ADDR, &val); in cs_dsp_adsp2_bus_error()
3132 cs_dsp_err(dsp, in cs_dsp_adsp2_bus_error()
3138 cs_dsp_err(dsp, "bus error address = 0x%x\n", in cs_dsp_adsp2_bus_error()
3142 dsp->base + ADSP2_PMEM_ERR_ADDR_XMEM_ERR_ADDR, in cs_dsp_adsp2_bus_error()
3145 cs_dsp_err(dsp, in cs_dsp_adsp2_bus_error()
3151 cs_dsp_err(dsp, "xmem error address = 0x%x\n", in cs_dsp_adsp2_bus_error()
3153 cs_dsp_err(dsp, "pmem error address = 0x%x\n", in cs_dsp_adsp2_bus_error()
3158 regmap_update_bits(regmap, dsp->base + ADSP2_LOCK_REGION_CTRL, in cs_dsp_adsp2_bus_error()
3162 mutex_unlock(&dsp->pwr_lock); in cs_dsp_adsp2_bus_error()
3167 * cs_dsp_halo_bus_error() - Handle a DSP bus error interrupt
3168 * @dsp: pointer to DSP structure
3170 * The firmware and DSP state will be logged for future analysis.
3172 void cs_dsp_halo_bus_error(struct cs_dsp *dsp) in cs_dsp_halo_bus_error() argument
3174 struct regmap *regmap = dsp->regmap; in cs_dsp_halo_bus_error()
3177 { dsp->base + HALO_MPU_XM_VIO_STATUS, 0x0 }, in cs_dsp_halo_bus_error()
3178 { dsp->base + HALO_MPU_YM_VIO_STATUS, 0x0 }, in cs_dsp_halo_bus_error()
3179 { dsp->base + HALO_MPU_PM_VIO_STATUS, 0x0 }, in cs_dsp_halo_bus_error()
3183 mutex_lock(&dsp->pwr_lock); in cs_dsp_halo_bus_error()
3185 ret = regmap_read(regmap, dsp->base_sysinfo + HALO_AHBM_WINDOW_DEBUG_1, in cs_dsp_halo_bus_error()
3188 cs_dsp_warn(dsp, "Failed to read AHB DEBUG_1: %d\n", ret); in cs_dsp_halo_bus_error()
3192 cs_dsp_warn(dsp, "AHB: STATUS: 0x%x ADDR: 0x%x\n", in cs_dsp_halo_bus_error()
3197 ret = regmap_read(regmap, dsp->base_sysinfo + HALO_AHBM_WINDOW_DEBUG_0, in cs_dsp_halo_bus_error()
3200 cs_dsp_warn(dsp, "Failed to read AHB DEBUG_0: %d\n", ret); in cs_dsp_halo_bus_error()
3204 cs_dsp_warn(dsp, "AHB: SYS_ADDR: 0x%x\n", *fault); in cs_dsp_halo_bus_error()
3206 ret = regmap_bulk_read(regmap, dsp->base + HALO_MPU_XM_VIO_ADDR, in cs_dsp_halo_bus_error()
3209 cs_dsp_warn(dsp, "Failed to read MPU fault info: %d\n", ret); in cs_dsp_halo_bus_error()
3213 cs_dsp_warn(dsp, "XM: STATUS:0x%x ADDR:0x%x\n", fault[1], fault[0]); in cs_dsp_halo_bus_error()
3214 cs_dsp_warn(dsp, "YM: STATUS:0x%x ADDR:0x%x\n", fault[3], fault[2]); in cs_dsp_halo_bus_error()
3215 cs_dsp_warn(dsp, "PM: STATUS:0x%x ADDR:0x%x\n", fault[5], fault[4]); in cs_dsp_halo_bus_error()
3217 ret = regmap_multi_reg_write(dsp->regmap, clear, ARRAY_SIZE(clear)); in cs_dsp_halo_bus_error()
3219 cs_dsp_warn(dsp, "Failed to clear MPU status: %d\n", ret); in cs_dsp_halo_bus_error()
3222 mutex_unlock(&dsp->pwr_lock); in cs_dsp_halo_bus_error()
3227 * cs_dsp_halo_wdt_expire() - Handle DSP watchdog expiry
3228 * @dsp: pointer to DSP structure
3232 void cs_dsp_halo_wdt_expire(struct cs_dsp *dsp) in cs_dsp_halo_wdt_expire() argument
3234 mutex_lock(&dsp->pwr_lock); in cs_dsp_halo_wdt_expire()
3236 cs_dsp_warn(dsp, "WDT Expiry Fault\n"); in cs_dsp_halo_wdt_expire()
3238 dsp->ops->stop_watchdog(dsp); in cs_dsp_halo_wdt_expire()
3239 if (dsp->client_ops->watchdog_expired) in cs_dsp_halo_wdt_expire()
3240 dsp->client_ops->watchdog_expired(dsp); in cs_dsp_halo_wdt_expire()
3242 mutex_unlock(&dsp->pwr_lock); in cs_dsp_halo_wdt_expire()
3334 * cs_dsp_chunk_write() - Format data to a DSP memory chunk
3339 * This function sequentially writes values into the format required for DSP
3341 * big endian. Note that data is only committed to the chunk when a whole DSP
3380 * As cs_dsp_chunk_write only writes data when a whole DSP word is ready to
3382 * function will pad that data with zeros upto a whole DSP word and write out.
3396 * cs_dsp_chunk_read() - Parse data from a DSP memory chunk
3400 * This function sequentially reads values from a DSP memory formatted buffer,
3437 MODULE_DESCRIPTION("Cirrus Logic DSP Support");