61 	void __iomem *reg_base;  member
92 static inline void bcm_kona_gpio_write_lock_regs(void __iomem *reg_base,  in bcm_kona_gpio_write_lock_regs()  argument
95 	writel(BCM_GPIO_PASSWD, reg_base + GPIO_GPPWR_OFFSET);  in bcm_kona_gpio_write_lock_regs()
96 	writel(lockcode, reg_base + GPIO_PWD_STATUS(bank_id));  in bcm_kona_gpio_write_lock_regs()
117 		val = readl(kona_gpio->reg_base + GPIO_PWD_STATUS(bank_id));  in bcm_kona_gpio_lock_gpio()
119 		bcm_kona_gpio_write_lock_regs(kona_gpio->reg_base, bank_id, val);  in bcm_kona_gpio_lock_gpio()
137 		val = readl(kona_gpio->reg_base + GPIO_PWD_STATUS(bank_id));  in bcm_kona_gpio_unlock_gpio()
139 		bcm_kona_gpio_write_lock_regs(kona_gpio->reg_base, bank_id, val);  in bcm_kona_gpio_unlock_gpio()
150 	void __iomem *reg_base = kona_gpio->reg_base;  in bcm_kona_gpio_get_dir()  local
153 	val = readl(reg_base + GPIO_CONTROL(gpio)) & GPIO_GPCTR0_IOTR_MASK;  in bcm_kona_gpio_get_dir()
160 	void __iomem *reg_base;  in bcm_kona_gpio_set()  local
167 	reg_base = kona_gpio->reg_base;  in bcm_kona_gpio_set()
176 	val = readl(reg_base + reg_offset);  in bcm_kona_gpio_set()
178 	writel(val, reg_base + reg_offset);  in bcm_kona_gpio_set()
187 	void __iomem *reg_base;  in bcm_kona_gpio_get()  local
194 	reg_base = kona_gpio->reg_base;  in bcm_kona_gpio_get()
203 	val = readl(reg_base + reg_offset);  in bcm_kona_gpio_get()
229 	void __iomem *reg_base;  in bcm_kona_gpio_direction_input()  local
234 	reg_base = kona_gpio->reg_base;  in bcm_kona_gpio_direction_input()
237 	val = readl(reg_base + GPIO_CONTROL(gpio));  in bcm_kona_gpio_direction_input()
240 	writel(val, reg_base + GPIO_CONTROL(gpio));  in bcm_kona_gpio_direction_input()
251 	void __iomem *reg_base;  in bcm_kona_gpio_direction_output()  local
258 	reg_base = kona_gpio->reg_base;  in bcm_kona_gpio_direction_output()
261 	val = readl(reg_base + GPIO_CONTROL(gpio));  in bcm_kona_gpio_direction_output()
264 	writel(val, reg_base + GPIO_CONTROL(gpio));  in bcm_kona_gpio_direction_output()
267 	val = readl(reg_base + reg_offset);  in bcm_kona_gpio_direction_output()
269 	writel(val, reg_base + reg_offset);  in bcm_kona_gpio_direction_output()
290 	void __iomem *reg_base;  in bcm_kona_gpio_set_debounce()  local
295 	reg_base = kona_gpio->reg_base;  in bcm_kona_gpio_set_debounce()
317 	val = readl(reg_base + GPIO_CONTROL(gpio));  in bcm_kona_gpio_set_debounce()
328 	writel(val, reg_base + GPIO_CONTROL(gpio));  in bcm_kona_gpio_set_debounce()
365 	void __iomem *reg_base;  in bcm_kona_gpio_irq_ack()  local
373 	reg_base = kona_gpio->reg_base;  in bcm_kona_gpio_irq_ack()
376 	val = readl(reg_base + GPIO_INT_STATUS(bank_id));  in bcm_kona_gpio_irq_ack()
378 	writel(val, reg_base + GPIO_INT_STATUS(bank_id));  in bcm_kona_gpio_irq_ack()
386 	void __iomem *reg_base;  in bcm_kona_gpio_irq_mask()  local
394 	reg_base = kona_gpio->reg_base;  in bcm_kona_gpio_irq_mask()
398 	val = readl(reg_base + GPIO_INT_MASK(bank_id));  in bcm_kona_gpio_irq_mask()
400 	writel(val, reg_base + GPIO_INT_MASK(bank_id));  in bcm_kona_gpio_irq_mask()
409 	void __iomem *reg_base;  in bcm_kona_gpio_irq_unmask()  local
417 	reg_base = kona_gpio->reg_base;  in bcm_kona_gpio_irq_unmask()
421 	val = readl(reg_base + GPIO_INT_MSKCLR(bank_id));  in bcm_kona_gpio_irq_unmask()
423 	writel(val, reg_base + GPIO_INT_MSKCLR(bank_id));  in bcm_kona_gpio_irq_unmask()
432 	void __iomem *reg_base;  in bcm_kona_gpio_irq_set_type()  local
439 	reg_base = kona_gpio->reg_base;  in bcm_kona_gpio_irq_set_type()
464 	val = readl(reg_base + GPIO_CONTROL(gpio));  in bcm_kona_gpio_irq_set_type()
467 	writel(val, reg_base + GPIO_CONTROL(gpio));  in bcm_kona_gpio_irq_set_type()
476 	void __iomem *reg_base;  in bcm_kona_gpio_irq_handler()  local
489 	reg_base = bank->kona_gpio->reg_base;  in bcm_kona_gpio_irq_handler()
492 	while ((sta = readl(reg_base + GPIO_INT_STATUS(bank_id)) &  in bcm_kona_gpio_irq_handler()
493 		    (~(readl(reg_base + GPIO_INT_MASK(bank_id)))))) {  in bcm_kona_gpio_irq_handler()
500 			writel(readl(reg_base + GPIO_INT_STATUS(bank_id)) |  in bcm_kona_gpio_irq_handler()
501 			       BIT(bit), reg_base + GPIO_INT_STATUS(bank_id));  in bcm_kona_gpio_irq_handler()
587 	void __iomem *reg_base;  in bcm_kona_gpio_reset()  local
590 	reg_base = kona_gpio->reg_base;  in bcm_kona_gpio_reset()
594 		bcm_kona_gpio_write_lock_regs(reg_base, i, UNLOCK_CODE);  in bcm_kona_gpio_reset()
595 		writel(0xffffffff, reg_base + GPIO_INT_MASK(i));  in bcm_kona_gpio_reset()
596 		writel(0xffffffff, reg_base + GPIO_INT_STATUS(i));  in bcm_kona_gpio_reset()
598 		bcm_kona_gpio_write_lock_regs(reg_base, i, LOCK_CODE);  in bcm_kona_gpio_reset()
650 	kona_gpio->reg_base = devm_platform_ioremap_resource(pdev, 0);  in bcm_kona_gpio_probe()
651 	if (IS_ERR(kona_gpio->reg_base)) {  in bcm_kona_gpio_probe()
652 		ret = PTR_ERR(kona_gpio->reg_base);  in bcm_kona_gpio_probe()