1 // SPDX-License-Identifier: GPL-2.0
6 // based on previous work and know-how from:
28  * The hardware uses 3 bits to indicate interrupt "style".
31  * the style for 8 lines each for a total of 16 GPIO lines.
42  * struct ixp4xx_gpio - IXP4 GPIO state container
46  * @base: remapped I/O-memory base
47  * @irq_edge: Each bit represents an IRQ: 1: edge-triggered,
63 	__raw_writel(BIT(d->hwirq), g->base + IXP4XX_REG_GPIS);  in ixp4xx_gpio_irq_ack()
71 	gpiochip_disable_irq(gc, d->hwirq);  in ixp4xx_gpio_mask_irq()
79 	/* ACK when unmasking if not edge-triggered */  in ixp4xx_gpio_irq_unmask()
80 	if (!(g->irq_edge & BIT(d->hwirq)))  in ixp4xx_gpio_irq_unmask()
83 	gpiochip_enable_irq(gc, d->hwirq);  in ixp4xx_gpio_irq_unmask()
91 	int line = d->hwirq;  in ixp4xx_gpio_irq_set_type()
101 		g->irq_edge |= BIT(d->hwirq);  in ixp4xx_gpio_irq_set_type()
106 		g->irq_edge |= BIT(d->hwirq);  in ixp4xx_gpio_irq_set_type()
111 		g->irq_edge |= BIT(d->hwirq);  in ixp4xx_gpio_irq_set_type()
116 		g->irq_edge &= ~BIT(d->hwirq);  in ixp4xx_gpio_irq_set_type()
121 		g->irq_edge &= ~BIT(d->hwirq);  in ixp4xx_gpio_irq_set_type()
124 		return -EINVAL;  in ixp4xx_gpio_irq_set_type()
128 		/* pins 8-15 */  in ixp4xx_gpio_irq_set_type()
129 		line -= 8;  in ixp4xx_gpio_irq_set_type()
132 		/* pins 0-7 */  in ixp4xx_gpio_irq_set_type()
136 	raw_spin_lock_irqsave(&g->gc.bgpio_lock, flags);  in ixp4xx_gpio_irq_set_type()
138 	/* Clear the style for the appropriate pin */  in ixp4xx_gpio_irq_set_type()
139 	val = __raw_readl(g->base + int_reg);  in ixp4xx_gpio_irq_set_type()
141 	__raw_writel(val, g->base + int_reg);  in ixp4xx_gpio_irq_set_type()
143 	__raw_writel(BIT(line), g->base + IXP4XX_REG_GPIS);  in ixp4xx_gpio_irq_set_type()
145 	/* Set the new style */  in ixp4xx_gpio_irq_set_type()
146 	val = __raw_readl(g->base + int_reg);  in ixp4xx_gpio_irq_set_type()
148 	__raw_writel(val, g->base + int_reg);  in ixp4xx_gpio_irq_set_type()
150 	/* Force-configure this line as an input */  in ixp4xx_gpio_irq_set_type()
151 	val = __raw_readl(g->base + IXP4XX_REG_GPOE);  in ixp4xx_gpio_irq_set_type()
152 	val |= BIT(d->hwirq);  in ixp4xx_gpio_irq_set_type()
153 	__raw_writel(val, g->base + IXP4XX_REG_GPOE);  in ixp4xx_gpio_irq_set_type()
155 	raw_spin_unlock_irqrestore(&g->gc.bgpio_lock, flags);  in ixp4xx_gpio_irq_set_type()
193 	return -EINVAL;  in ixp4xx_gpio_child_to_parent_hwirq()
199 	struct device *dev = &pdev->dev;  in ixp4xx_gpio_probe()
200 	struct device_node *np = dev->of_node;  in ixp4xx_gpio_probe()
209 		return -ENOMEM;  in ixp4xx_gpio_probe()
210 	g->dev = dev;  in ixp4xx_gpio_probe()
212 	g->base = devm_platform_ioremap_resource(pdev, 0);  in ixp4xx_gpio_probe()
213 	if (IS_ERR(g->base))  in ixp4xx_gpio_probe()
214 		return PTR_ERR(g->base);  in ixp4xx_gpio_probe()
219 		return -ENODEV;  in ixp4xx_gpio_probe()
224 		return -ENODEV;  in ixp4xx_gpio_probe()
226 	g->fwnode = of_node_to_fwnode(np);  in ixp4xx_gpio_probe()
232 	if (of_machine_is_compatible("dlink,dsm-g600-a") ||  in ixp4xx_gpio_probe()
233 	    of_machine_is_compatible("iom,nas-100d"))  in ixp4xx_gpio_probe()
234 		__raw_writel(0x0, g->base + IXP4XX_REG_GPCLK);  in ixp4xx_gpio_probe()
237 	 * This is a very special big-endian ARM issue: when the IXP4xx is  in ixp4xx_gpio_probe()
239 	 * around to the CPU-native endianness. As you see mostly in the  in ixp4xx_gpio_probe()
252 	ret = bgpio_init(&g->gc, dev, 4,  in ixp4xx_gpio_probe()
253 			 g->base + IXP4XX_REG_GPIN,  in ixp4xx_gpio_probe()
254 			 g->base + IXP4XX_REG_GPOUT,  in ixp4xx_gpio_probe()
257 			 g->base + IXP4XX_REG_GPOE,  in ixp4xx_gpio_probe()
263 	g->gc.ngpio = 16;  in ixp4xx_gpio_probe()
264 	g->gc.label = "IXP4XX_GPIO_CHIP";  in ixp4xx_gpio_probe()
267 	 * are fetched using phandles, set this to -1 to get rid of  in ixp4xx_gpio_probe()
270 	g->gc.base = 0;  in ixp4xx_gpio_probe()
271 	g->gc.parent = &pdev->dev;  in ixp4xx_gpio_probe()
272 	g->gc.owner = THIS_MODULE;  in ixp4xx_gpio_probe()
274 	girq = &g->gc.irq;  in ixp4xx_gpio_probe()
276 	girq->fwnode = g->fwnode;  in ixp4xx_gpio_probe()
277 	girq->parent_domain = parent;  in ixp4xx_gpio_probe()
278 	girq->child_to_parent_hwirq = ixp4xx_gpio_child_to_parent_hwirq;  in ixp4xx_gpio_probe()
279 	girq->handler = handle_bad_irq;  in ixp4xx_gpio_probe()
280 	girq->default_type = IRQ_TYPE_NONE;  in ixp4xx_gpio_probe()
282 	ret = devm_gpiochip_add_data(dev, &g->gc, g);  in ixp4xx_gpio_probe()
296 		.compatible = "intel,ixp4xx-gpio",
304 		.name		= "ixp4xx-gpio",