105 	dispc_mgr_enable(priv->dispc, channel, true);  in omap_crtc_dss_start_update()
130 		dispc_mgr_enable(priv->dispc, channel, enable);  in omap_crtc_set_enabled()
143 	framedone_irq = dispc_mgr_get_framedone_irq(priv->dispc,  in omap_crtc_set_enabled()
145 	vsync_irq = dispc_mgr_get_vsync_irq(priv->dispc, channel);  in omap_crtc_set_enabled()
152 		 * FRAMEDONE to know that DISPC has finished with the output.  in omap_crtc_set_enabled()
165 	dispc_mgr_enable(priv->dispc, channel, enable);  in omap_crtc_set_enabled()
187 	dispc_mgr_set_timings(priv->dispc, omap_crtc->channel,  in omap_crtc_dss_enable()
221 	dispc_mgr_set_lcd_config(priv->dispc, omap_crtc->channel,  in omap_crtc_dss_set_lcd_config()
287 	 * If the dispc is busy we're racing the flush operation. Try again on  in omap_crtc_vblank_irq()
290 	if (dispc_mgr_go_busy(priv->dispc, omap_crtc->channel)) {  in omap_crtc_vblank_irq()
416 	dispc_mgr_setup(priv->dispc, omap_crtc->channel, &info);  in omap_crtc_write_crtc_properties()
457 	dispc_runtime_get(priv->dispc);  in omap_crtc_atomic_enable()
496 	dispc_runtime_put(priv->dispc);  in omap_crtc_atomic_disable()
511 	 * valid DISPC mode. DSI will calculate and configure the  in omap_crtc_mode_valid()
512 	 * proper DISPC mode later.  in omap_crtc_mode_valid()
515 		r = dispc_mgr_check_timings(priv->dispc,  in omap_crtc_mode_valid()
633 		dispc_mgr_set_gamma(priv->dispc, omap_crtc->channel,  in omap_crtc_atomic_flush()
658 	dispc_mgr_go(priv->dispc, omap_crtc->channel);  in omap_crtc_atomic_flush()
831 	/* The dispc API adapts to what ever size, but the HW supports  in omap_crtc_init()
838 	if (dispc_mgr_gamma_size(priv->dispc, channel)) {  in omap_crtc_init()